2010-08-19 13:36:01 +02:00
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/*
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2010-12-08 15:13:28 +01:00
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* Copyright (C) STMicroelectronics 2009
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* Copyright (C) ST-Ericsson SA 2010
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2010-08-19 13:36:01 +02:00
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*
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* License Terms: GNU General Public License v2
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2010-12-08 15:13:28 +01:00
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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* Author: Sundar Iyer <sundar.iyer@stericsson.com>
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2010-08-19 13:36:01 +02:00
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* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
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*
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2010-12-08 15:13:28 +01:00
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* U8500 PRCM Unit interface driver
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*
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2010-08-19 13:36:01 +02:00
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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#include <linux/completion.h>
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#include <linux/jiffies.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <mach/hardware.h>
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#include <mach/prcmu-regs.h>
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2010-12-08 15:13:28 +01:00
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#include <mach/prcmu-defs.h>
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2010-08-19 13:36:01 +02:00
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2010-12-02 16:20:42 +01:00
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/* Global var to runtime determine TCDM base for v2 or v1 */
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static __iomem void *tcdm_base;
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2010-08-19 13:36:01 +02:00
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2010-12-08 15:13:28 +01:00
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#define _MBOX_HEADER (tcdm_base + 0xFE8)
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#define MBOX_HEADER_REQ_MB0 (_MBOX_HEADER + 0x0)
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#define REQ_MB1 (tcdm_base + 0xFD0)
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2010-12-02 16:20:42 +01:00
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#define REQ_MB5 (tcdm_base + 0xE44)
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2010-12-08 15:13:28 +01:00
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#define REQ_MB1_ARMOPP (REQ_MB1 + 0x0)
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#define REQ_MB1_APEOPP (REQ_MB1 + 0x1)
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#define REQ_MB1_BOOSTOPP (REQ_MB1 + 0x2)
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#define ACK_MB1 (tcdm_base + 0xE04)
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2010-12-02 16:20:42 +01:00
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#define ACK_MB5 (tcdm_base + 0xDF4)
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2010-08-19 13:36:01 +02:00
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2010-12-08 15:13:28 +01:00
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#define ACK_MB1_CURR_ARMOPP (ACK_MB1 + 0x0)
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#define ACK_MB1_CURR_APEOPP (ACK_MB1 + 0x1)
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2010-08-19 13:36:01 +02:00
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#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
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#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
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#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
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#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
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#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
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#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
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2010-12-08 15:13:28 +01:00
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#define PRCM_AVS_VARM_MAX_OPP (tcdm_base + 0x2E4)
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#define PRCM_AVS_ISMODEENABLE 7
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#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
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2010-12-02 16:20:42 +01:00
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#define I2C_WRITE(slave) \
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(((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
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#define I2C_READ(slave) \
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(((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
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2010-08-19 13:36:01 +02:00
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#define I2C_STOP_EN BIT(3)
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2010-12-08 15:13:28 +01:00
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enum mb1_h {
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MB1H_ARM_OPP = 1,
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MB1H_APE_OPP,
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MB1H_ARM_APE_OPP,
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};
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static struct {
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struct mutex lock;
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struct completion work;
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struct {
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u8 arm_opp;
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u8 ape_opp;
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u8 arm_status;
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u8 ape_status;
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} ack;
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} mb1_transfer;
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2010-08-19 13:36:01 +02:00
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enum ack_mb5_status {
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I2C_WR_OK = 0x01,
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I2C_RD_OK = 0x02,
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};
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#define MBOX_BIT BIT
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#define NUM_MBOX 8
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static struct {
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struct mutex lock;
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struct completion work;
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bool failed;
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struct {
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u8 status;
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u8 value;
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} ack;
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} mb5_transfer;
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/**
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* prcmu_abb_read() - Read register value(s) from the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The read out value(s).
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* @size: The number of registers to read.
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*
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* Reads register value(s) from the ABB.
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* @size has to be 1 for the current firmware version.
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*/
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int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if (size != 1)
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return -EINVAL;
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r = mutex_lock_interruptible(&mb5_transfer.lock);
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if (r)
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return r;
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
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writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
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writeb(reg, REQ_MB5_I2C_REG);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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if (!wait_for_completion_timeout(&mb5_transfer.work,
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msecs_to_jiffies(500))) {
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pr_err("prcmu: prcmu_abb_read timed out.\n");
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r = -EIO;
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goto unlock_and_return;
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}
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r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
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if (!r)
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*value = mb5_transfer.ack.value;
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unlock_and_return:
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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EXPORT_SYMBOL(prcmu_abb_read);
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/**
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* prcmu_abb_write() - Write register value(s) to the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The value(s) to write.
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* @size: The number of registers to write.
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*
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* Reads register value(s) from the ABB.
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* @size has to be 1 for the current firmware version.
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*/
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int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if (size != 1)
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return -EINVAL;
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r = mutex_lock_interruptible(&mb5_transfer.lock);
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if (r)
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return r;
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
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writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
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writeb(reg, REQ_MB5_I2C_REG);
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writeb(*value, REQ_MB5_I2C_VAL);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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if (!wait_for_completion_timeout(&mb5_transfer.work,
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msecs_to_jiffies(500))) {
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pr_err("prcmu: prcmu_abb_write timed out.\n");
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r = -EIO;
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goto unlock_and_return;
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}
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r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
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unlock_and_return:
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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EXPORT_SYMBOL(prcmu_abb_write);
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2010-12-08 15:13:28 +01:00
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static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
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enum prcmu_cpu_opp cpu_opp)
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{
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bool do_ape;
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bool do_arm;
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int err = 0;
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do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
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do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
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mutex_lock(&mb1_transfer.lock);
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
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cpu_relax();
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writeb(0, MBOX_HEADER_REQ_MB0);
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writeb(cpu_opp, REQ_MB1_ARMOPP);
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writeb(ape_opp, REQ_MB1_APEOPP);
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writeb(0, REQ_MB1_BOOSTOPP);
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writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
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wait_for_completion(&mb1_transfer.work);
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if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
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err = -EIO;
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if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
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err = -EIO;
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mutex_unlock(&mb1_transfer.lock);
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return err;
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}
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/**
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* prcmu_set_ape_opp() - Set the OPP of the APE.
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* @opp: The OPP to set.
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*
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* This function sets the OPP of the APE.
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*/
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int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
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{
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return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
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}
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EXPORT_SYMBOL(prcmu_set_ape_opp);
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/**
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* prcmu_set_cpu_opp() - Set the OPP of the CPU.
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* @opp: The OPP to set.
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*
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* This function sets the OPP of the CPU.
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*/
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int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
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{
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return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
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}
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EXPORT_SYMBOL(prcmu_set_cpu_opp);
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/**
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* prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
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* @ape_opp: The APE OPP to set.
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* @cpu_opp: The CPU OPP to set.
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*
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* This function sets the OPPs of the APE and the CPU.
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*/
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int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
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enum prcmu_cpu_opp cpu_opp)
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{
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return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
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}
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EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
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/**
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* prcmu_get_ape_opp() - Get the OPP of the APE.
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*
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* This function gets the OPP of the APE.
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*/
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enum prcmu_ape_opp prcmu_get_ape_opp(void)
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{
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return readb(ACK_MB1_CURR_APEOPP);
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}
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EXPORT_SYMBOL(prcmu_get_ape_opp);
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/**
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* prcmu_get_cpu_opp() - Get the OPP of the CPU.
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*
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* This function gets the OPP of the CPU. The OPP is specified in %%.
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* PRCMU_OPP_EXT is a special OPP value, not specified in %%.
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*/
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int prcmu_get_cpu_opp(void)
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{
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return readb(ACK_MB1_CURR_ARMOPP);
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}
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EXPORT_SYMBOL(prcmu_get_cpu_opp);
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bool prcmu_has_arm_maxopp(void)
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{
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return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
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== PRCM_AVS_ISMODEENABLE_MASK;
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}
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2010-08-19 13:36:01 +02:00
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static void read_mailbox_0(void)
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{
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writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_1(void)
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{
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2010-12-08 15:13:28 +01:00
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mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
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mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
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complete(&mb1_transfer.work);
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2010-08-19 13:36:01 +02:00
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writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_2(void)
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{
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writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_3(void)
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{
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writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_4(void)
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{
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writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_5(void)
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{
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mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
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mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
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complete(&mb5_transfer.work);
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writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_6(void)
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{
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writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_7(void)
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{
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writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
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}
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static void (* const read_mailbox[NUM_MBOX])(void) = {
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read_mailbox_0,
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|
read_mailbox_1,
|
|
|
|
read_mailbox_2,
|
|
|
|
read_mailbox_3,
|
|
|
|
read_mailbox_4,
|
|
|
|
read_mailbox_5,
|
|
|
|
read_mailbox_6,
|
|
|
|
read_mailbox_7
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t prcmu_irq_handler(int irq, void *data)
|
|
|
|
{
|
|
|
|
u32 bits;
|
|
|
|
u8 n;
|
|
|
|
|
|
|
|
bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
|
|
|
|
if (unlikely(!bits))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
for (n = 0; bits; n++) {
|
|
|
|
if (bits & MBOX_BIT(n)) {
|
|
|
|
bits -= MBOX_BIT(n);
|
|
|
|
read_mailbox[n]();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2010-12-02 16:20:42 +01:00
|
|
|
void __init prcmu_early_init(void)
|
|
|
|
{
|
|
|
|
if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
|
|
|
|
tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
|
|
|
|
} else if (cpu_is_u8500v2()) {
|
|
|
|
tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
|
|
|
|
} else {
|
|
|
|
pr_err("prcmu: Unsupported chip version\n");
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-08-19 13:36:01 +02:00
|
|
|
static int __init prcmu_init(void)
|
|
|
|
{
|
2010-12-08 15:13:28 +01:00
|
|
|
if (cpu_is_u8500ed()) {
|
|
|
|
pr_err("prcmu: Unsupported chip version\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_init(&mb1_transfer.lock);
|
|
|
|
init_completion(&mb1_transfer.work);
|
2010-08-19 13:36:01 +02:00
|
|
|
mutex_init(&mb5_transfer.lock);
|
|
|
|
init_completion(&mb5_transfer.work);
|
|
|
|
|
|
|
|
/* Clean up the mailbox interrupts after pre-kernel code. */
|
|
|
|
writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
|
|
|
|
|
2010-12-08 06:37:56 +01:00
|
|
|
return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
|
|
|
|
"prcmu", NULL);
|
2010-08-19 13:36:01 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
arch_initcall(prcmu_init);
|