2009-05-04 20:11:14 +02:00
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#include "amd64_edac.h"
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static struct edac_pci_ctl_info *amd64_ctl_pci;
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static int report_gart_errors;
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module_param(report_gart_errors, int, 0644);
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/*
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* Set by command line parameter. If BIOS has enabled the ECC, this override is
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* cleared to prevent re-enabling the hardware by this driver.
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*/
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static int ecc_enable_override;
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module_param(ecc_enable_override, int, 0644);
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/* Lookup table for all possible MC control instances */
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struct amd64_pvt;
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static struct mem_ctl_info *mci_lookup[MAX_NUMNODES];
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static struct amd64_pvt *pvt_lookup[MAX_NUMNODES];
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/*
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* Memory scrubber control interface. For K8, memory scrubbing is handled by
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* hardware and can involve L2 cache, dcache as well as the main memory. With
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* F10, this is extended to L3 cache scrubbing on CPU models sporting that
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* functionality.
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*
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* This causes the "units" for the scrubbing speed to vary from 64 byte blocks
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* (dram) over to cache lines. This is nasty, so we will use bandwidth in
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* bytes/sec for the setting.
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*
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* Currently, we only do dram scrubbing. If the scrubbing is done in software on
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* other archs, we might not have access to the caches directly.
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*/
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/*
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* scan the scrub rate mapping table for a close or matching bandwidth value to
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* issue. If requested is too big, then use last maximum value found.
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*/
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static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw,
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u32 min_scrubrate)
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{
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u32 scrubval;
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int i;
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/*
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* map the configured rate (new_bw) to a value specific to the AMD64
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* memory controller and apply to register. Search for the first
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* bandwidth entry that is greater or equal than the setting requested
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* and program that. If at last entry, turn off DRAM scrubbing.
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*/
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for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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/*
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* skip scrub rates which aren't recommended
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* (see F10 BKDG, F3x58)
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*/
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if (scrubrates[i].scrubval < min_scrubrate)
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continue;
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if (scrubrates[i].bandwidth <= new_bw)
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break;
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/*
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* if no suitable bandwidth found, turn off DRAM scrubbing
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* entirely by falling back to the last element in the
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* scrubrates array.
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*/
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}
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scrubval = scrubrates[i].scrubval;
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if (scrubval)
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edac_printk(KERN_DEBUG, EDAC_MC,
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"Setting scrub rate bandwidth: %u\n",
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scrubrates[i].bandwidth);
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else
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edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n");
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pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F);
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return 0;
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}
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static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 min_scrubrate = 0x0;
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switch (boot_cpu_data.x86) {
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case 0xf:
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min_scrubrate = K8_MIN_SCRUB_RATE_BITS;
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break;
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case 0x10:
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min_scrubrate = F10_MIN_SCRUB_RATE_BITS;
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break;
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case 0x11:
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min_scrubrate = F11_MIN_SCRUB_RATE_BITS;
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break;
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default:
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amd64_printk(KERN_ERR, "Unsupported family!\n");
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break;
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}
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return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth,
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min_scrubrate);
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}
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static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 scrubval = 0;
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int status = -1, i, ret = 0;
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ret = pci_read_config_dword(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval);
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if (ret)
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debugf0("Reading K8_SCRCTRL failed\n");
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scrubval = scrubval & 0x001F;
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edac_printk(KERN_DEBUG, EDAC_MC,
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"pci-read, sdram scrub control value: %d \n", scrubval);
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for (i = 0; ARRAY_SIZE(scrubrates); i++) {
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if (scrubrates[i].scrubval == scrubval) {
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*bw = scrubrates[i].bandwidth;
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status = 0;
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break;
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}
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}
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return status;
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}
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2009-04-27 15:53:22 +02:00
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/* Map from a CSROW entry to the mask entry that operates on it */
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static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)
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{
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return csrow >> (pvt->num_dcsm >> 3);
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}
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/* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
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static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow)
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{
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if (dct == 0)
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return pvt->dcsb0[csrow];
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else
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return pvt->dcsb1[csrow];
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}
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/*
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* Return the 'mask' address the i'th CS entry. This function is needed because
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* there number of DCSM registers on Rev E and prior vs Rev F and later is
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* different.
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*/
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static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow)
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{
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if (dct == 0)
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return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)];
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else
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return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)];
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}
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/*
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* In *base and *limit, pass back the full 40-bit base and limit physical
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* addresses for the node given by node_id. This information is obtained from
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* DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
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* base and limit addresses are of type SysAddr, as defined at the start of
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* section 3.4.4 (p. 70). They are the lowest and highest physical addresses
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* in the address range they represent.
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*/
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static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id,
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u64 *base, u64 *limit)
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{
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*base = pvt->dram_base[node_id];
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*limit = pvt->dram_limit[node_id];
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}
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/*
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* Return 1 if the SysAddr given by sys_addr matches the base/limit associated
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* with node_id
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*/
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static int amd64_base_limit_match(struct amd64_pvt *pvt,
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u64 sys_addr, int node_id)
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{
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u64 base, limit, addr;
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amd64_get_base_and_limit(pvt, node_id, &base, &limit);
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/* The K8 treats this as a 40-bit value. However, bits 63-40 will be
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* all ones if the most significant implemented address bit is 1.
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* Here we discard bits 63-40. See section 3.4.2 of AMD publication
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* 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
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* Application Programming.
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*/
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addr = sys_addr & 0x000000ffffffffffull;
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return (addr >= base) && (addr <= limit);
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}
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/*
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* Attempt to map a SysAddr to a node. On success, return a pointer to the
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* mem_ctl_info structure for the node that the SysAddr maps to.
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*
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* On failure, return NULL.
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*/
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static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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u64 sys_addr)
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{
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struct amd64_pvt *pvt;
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int node_id;
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u32 intlv_en, bits;
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/*
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* Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
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* 3.4.4.2) registers to map the SysAddr to a node ID.
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*/
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pvt = mci->pvt_info;
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/*
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* The value of this field should be the same for all DRAM Base
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* registers. Therefore we arbitrarily choose to read it from the
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* register for node 0.
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*/
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intlv_en = pvt->dram_IntlvEn[0];
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if (intlv_en == 0) {
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for (node_id = 0; ; ) {
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if (amd64_base_limit_match(pvt, sys_addr, node_id))
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break;
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if (++node_id >= DRAM_REG_COUNT)
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goto err_no_match;
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}
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goto found;
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}
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if (unlikely((intlv_en != (0x01 << 8)) &&
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(intlv_en != (0x03 << 8)) &&
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(intlv_en != (0x07 << 8)))) {
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amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from "
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"IntlvEn field of DRAM Base Register for node 0: "
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"This probably indicates a BIOS bug.\n", intlv_en);
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return NULL;
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}
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bits = (((u32) sys_addr) >> 12) & intlv_en;
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for (node_id = 0; ; ) {
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if ((pvt->dram_limit[node_id] & intlv_en) == bits)
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break; /* intlv_sel field matches */
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if (++node_id >= DRAM_REG_COUNT)
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goto err_no_match;
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}
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/* sanity test for sys_addr */
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if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
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amd64_printk(KERN_WARNING,
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"%s(): sys_addr 0x%lx falls outside base/limit "
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"address range for node %d with node interleaving "
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"enabled.\n", __func__, (unsigned long)sys_addr,
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node_id);
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return NULL;
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}
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found:
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return edac_mc_find(node_id);
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err_no_match:
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debugf2("sys_addr 0x%lx doesn't match any node\n",
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(unsigned long)sys_addr);
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return NULL;
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}
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2009-04-27 15:57:12 +02:00
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/*
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* Extract the DRAM CS base address from selected csrow register.
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*/
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static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow)
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{
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return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) <<
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pvt->dcs_shift;
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}
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/*
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* Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
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*/
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static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow)
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{
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u64 dcsm_bits, other_bits;
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u64 mask;
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/* Extract bits from DRAM CS Mask. */
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dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask;
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other_bits = pvt->dcsm_mask;
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other_bits = ~(other_bits << pvt->dcs_shift);
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/*
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* The extracted bits from DCSM belong in the spaces represented by
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* the cleared bits in other_bits.
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*/
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mask = (dcsm_bits << pvt->dcs_shift) | other_bits;
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return mask;
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}
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/*
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* @input_addr is an InputAddr associated with the node given by mci. Return the
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* csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
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*/
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static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
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{
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struct amd64_pvt *pvt;
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int csrow;
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u64 base, mask;
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pvt = mci->pvt_info;
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/*
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* Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS
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* base/mask register pair, test the condition shown near the start of
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* section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
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*/
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for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {
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/* This DRAM chip select is disabled on this node */
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if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
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continue;
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base = base_from_dct_base(pvt, csrow);
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mask = ~mask_from_dct_mask(pvt, csrow);
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if ((input_addr & mask) == (base & mask)) {
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debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
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(unsigned long)input_addr, csrow,
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pvt->mc_node_id);
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return csrow;
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}
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}
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debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
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(unsigned long)input_addr, pvt->mc_node_id);
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return -1;
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}
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/*
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* Return the base value defined by the DRAM Base register for the node
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* represented by mci. This function returns the full 40-bit value despite the
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* fact that the register only stores bits 39-24 of the value. See section
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* 3.4.4.1 (BKDG #26094, K8, revA-E)
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*/
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static inline u64 get_dram_base(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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return pvt->dram_base[pvt->mc_node_id];
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}
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/*
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* Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
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* for the node represented by mci. Info is passed back in *hole_base,
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* *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
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* info is invalid. Info may be invalid for either of the following reasons:
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*
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* - The revision of the node is not E or greater. In this case, the DRAM Hole
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* Address Register does not exist.
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*
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* - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
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* indicating that its contents are not valid.
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*
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* The values passed back in *hole_base, *hole_offset, and *hole_size are
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* complete 32-bit values despite the fact that the bitfields in the DHAR
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* only represent bits 31-24 of the base and offset values.
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*/
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int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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u64 *hole_offset, u64 *hole_size)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u64 base;
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/* only revE and later have the DRAM Hole Address Register */
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if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_E) {
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|
debugf1(" revision %d for node %d does not support DHAR\n",
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pvt->ext_model, pvt->mc_node_id);
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|
return 1;
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|
}
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|
|
|
/* only valid for Fam10h */
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|
if (boot_cpu_data.x86 == 0x10 &&
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|
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(pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) {
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|
|
debugf1(" Dram Memory Hoisting is DISABLED on this system\n");
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|
|
return 1;
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|
}
|
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|
|
if ((pvt->dhar & DHAR_VALID) == 0) {
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|
|
debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",
|
|
|
|
pvt->mc_node_id);
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|
|
return 1;
|
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|
|
}
|
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|
|
|
|
|
|
/* This node has Memory Hoisting */
|
|
|
|
|
|
|
|
/* +------------------+--------------------+--------------------+-----
|
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|
|
* | memory | DRAM hole | relocated |
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|
|
* | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
|
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|
|
* | | | DRAM hole |
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|
* | | | [0x100000000, |
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|
* | | | (0x100000000+ |
|
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|
|
* | | | (0xffffffff-x))] |
|
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|
|
* +------------------+--------------------+--------------------+-----
|
|
|
|
*
|
|
|
|
* Above is a diagram of physical memory showing the DRAM hole and the
|
|
|
|
* relocated addresses from the DRAM hole. As shown, the DRAM hole
|
|
|
|
* starts at address x (the base address) and extends through address
|
|
|
|
* 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
|
|
|
|
* addresses in the hole so that they start at 0x100000000.
|
|
|
|
*/
|
|
|
|
|
|
|
|
base = dhar_base(pvt->dhar);
|
|
|
|
|
|
|
|
*hole_base = base;
|
|
|
|
*hole_size = (0x1ull << 32) - base;
|
|
|
|
|
|
|
|
if (boot_cpu_data.x86 > 0xf)
|
|
|
|
*hole_offset = f10_dhar_offset(pvt->dhar);
|
|
|
|
else
|
|
|
|
*hole_offset = k8_dhar_offset(pvt->dhar);
|
|
|
|
|
|
|
|
debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
|
|
|
|
pvt->mc_node_id, (unsigned long)*hole_base,
|
|
|
|
(unsigned long)*hole_offset, (unsigned long)*hole_size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);
|
|
|
|
|
|
|
|
|