2005-04-17 00:20:36 +02:00
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/*
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* linux/arch/m68k/mm/memory.c
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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2006-10-11 18:28:27 +02:00
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#include <linux/module.h>
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2005-04-17 00:20:36 +02:00
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/pagemap.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 09:04:11 +01:00
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#include <linux/gfp.h>
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2005-04-17 00:20:36 +02:00
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
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struct page instead of separately kmalloced struct. Stolen from
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arch/sparc/mm/srmmu.c ... */
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typedef struct list_head ptable_desc;
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static LIST_HEAD(ptable_list);
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#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
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#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
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#define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
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#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
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void __init init_pointer_table(unsigned long ptable)
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{
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ptable_desc *dp;
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unsigned long page = ptable & PAGE_MASK;
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unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
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dp = PD_PTABLE(page);
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if (!(PD_MARKBITS(dp) & mask)) {
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PD_MARKBITS(dp) = 0xff;
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list_add(dp, &ptable_list);
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}
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PD_MARKBITS(dp) &= ~mask;
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#ifdef DEBUG
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printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
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#endif
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/* unreserve the page so it's possible to free that page */
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PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
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2006-03-22 09:08:40 +01:00
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init_page_count(PD_PAGE(dp));
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2005-04-17 00:20:36 +02:00
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return;
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}
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pmd_t *get_pointer_table (void)
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{
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ptable_desc *dp = ptable_list.next;
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unsigned char mask = PD_MARKBITS (dp);
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unsigned char tmp;
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unsigned int off;
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/*
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* For a pointer table for a user process address space, a
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* table is taken from a page allocated for the purpose. Each
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* page can hold 8 pointer tables. The page is remapped in
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* virtual address space to be noncacheable.
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*/
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if (mask == 0) {
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void *page;
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ptable_desc *new;
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if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
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return NULL;
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flush_tlb_kernel_page(page);
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nocache_page(page);
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new = PD_PTABLE(page);
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PD_MARKBITS(new) = 0xfe;
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list_add_tail(new, dp);
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return (pmd_t *)page;
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}
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for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
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;
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PD_MARKBITS(dp) = mask & ~tmp;
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if (!PD_MARKBITS(dp)) {
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/* move to end of list */
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2006-06-26 09:24:39 +02:00
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list_move_tail(dp, &ptable_list);
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2005-04-17 00:20:36 +02:00
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}
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return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
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}
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int free_pointer_table (pmd_t *ptable)
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{
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ptable_desc *dp;
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unsigned long page = (unsigned long)ptable & PAGE_MASK;
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unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
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dp = PD_PTABLE(page);
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if (PD_MARKBITS (dp) & mask)
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panic ("table already free!");
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PD_MARKBITS (dp) |= mask;
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if (PD_MARKBITS(dp) == 0xff) {
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/* all tables in page are free, free page */
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list_del(dp);
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cache_page((void *)page);
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free_page (page);
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return 1;
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} else if (ptable_list.next != dp) {
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/*
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* move this descriptor to the front of the list, since
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* it has one or more free tables.
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*/
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2006-06-26 09:24:39 +02:00
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list_move(dp, &ptable_list);
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2005-04-17 00:20:36 +02:00
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}
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return 0;
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}
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/* invalidate page in both caches */
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static inline void clear040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* invalidate page in i-cache */
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static inline void cleari040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push page in both caches */
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/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
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static inline void push040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push and invalidate page in both caches, must disable ints
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* to avoid invalidating valid data */
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static inline void pushcl040(unsigned long paddr)
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{
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unsigned long flags;
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local_irq_save(flags);
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push040(paddr);
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if (CPU_IS_060)
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clear040(paddr);
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local_irq_restore(flags);
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}
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/*
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* 040: Hit every page containing an address in the range paddr..paddr+len-1.
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* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
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* Hit every page until there is a page or less to go. Hit the next page,
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* and the one after that if the range hits it.
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*/
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/* ++roman: A little bit more care is required here: The CINVP instruction
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* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
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* and the end of the region must be treated differently if they are not
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* exactly at the beginning or end of a page boundary. Else, maybe too much
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* data becomes invalidated and thus lost forever. CPUSHP does what we need:
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* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
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* for discovering the problem!)
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*/
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/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
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* the DPI bit in the CACR; would it cause problems with temporarily changing
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* this?). So we have to push first and then additionally to invalidate.
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*/
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/*
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* cache_clear() semantics: Clear any cache entries for the area in question,
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* without writing back dirty entries first. This is useful if the data will
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* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
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* _physical_ address.
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*/
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void cache_clear (unsigned long paddr, int len)
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{
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if (CPU_IS_040_OR_060) {
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int tmp;
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/*
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* We need special treatment for the first page, in case it
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* is not page-aligned. Page align the addresses to work
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* around bug I17 in the 68060.
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*/
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if ((tmp = -paddr & (PAGE_SIZE - 1))) {
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pushcl040(paddr & PAGE_MASK);
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if ((len -= tmp) <= 0)
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return;
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paddr += tmp;
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}
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tmp = PAGE_SIZE;
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paddr &= PAGE_MASK;
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while ((len -= tmp) >= 0) {
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clear040(paddr);
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paddr += tmp;
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}
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if ((len += tmp))
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/* a page boundary gets crossed at the end */
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pushcl040(paddr);
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}
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I_AND_D)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(0);
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#endif
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}
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2006-12-09 10:50:15 +01:00
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EXPORT_SYMBOL(cache_clear);
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2005-04-17 00:20:36 +02:00
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/*
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* cache_push() semantics: Write back any dirty cache data in the given area,
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* and invalidate the range in the instruction cache. It needs not (but may)
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* invalidate those entries also in the data cache. The range is defined by a
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* _physical_ address.
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*/
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void cache_push (unsigned long paddr, int len)
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{
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if (CPU_IS_040_OR_060) {
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int tmp = PAGE_SIZE;
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/*
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* on 68040 or 68060, push cache lines for pages in the range;
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* on the '040 this also invalidates the pushed lines, but not on
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* the '060!
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*/
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len += paddr & (PAGE_SIZE - 1);
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/*
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* Work around bug I17 in the 68060 affecting some instruction
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* lines not being invalidated properly.
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*/
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paddr &= PAGE_MASK;
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do {
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push040(paddr);
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paddr += tmp;
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} while ((len -= tmp) > 0);
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}
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/*
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* 68030/68020 have no writeback cache. On the other hand,
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* cache_push is actually a superset of cache_clear (the lines
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* get written back and invalidated), so we should make sure
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* to perform the corresponding actions. After all, this is getting
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* called in places where we've just loaded code, or whatever, so
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* flushing the icache is appropriate; flushing the dcache shouldn't
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* be required.
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*/
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(1);
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#endif
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}
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2006-12-09 10:50:15 +01:00
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EXPORT_SYMBOL(cache_push);
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2005-04-17 00:20:36 +02:00
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