ARM: mach-shmobile: Rely on run-time IRQ handlers
Remove now unused IRQ demux code. All R-Mobile and SH-Mobile processors should register IRQ demux handlers during run-time. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm
Paul Mundt
parent
e74a9625f8
commit
018a3fc7e3
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/*
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* Copyright (C) 2010 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/entry-macro-gic.S>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =(0xf0000100)
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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@ -1,61 +0,0 @@
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/*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <mach/irqs.h>
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#define INTCA_BASE 0xe6980000
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#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
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#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
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#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
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#define INTLVLB_OFFS 0x00000034 /* previous priority level */
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =INTCA_BASE
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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/* The single INTFLGA read access below results in the following:
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*
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* 1. INTLVLB is updated with old priority value from INTLVLA
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* 2. Highest priority interrupt is accepted
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* 3. INTLVLA is updated to contain priority of accepted interrupt
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* 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
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*/
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ldr \irqnr, [\base, #INTFLGA_OFFS]
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/* Restore INTLVLA with the value saved in INTLVLB.
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* This is required to support interrupt priorities properly.
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*/
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ldrb \tmp, [\base, #INTLVLB_OFFS]
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strb \tmp, [\base, #INTLVLA_OFFS]
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/* Handle invalid vector number case */
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cmp \irqnr, #0
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beq 1000f
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/* Convert vector to irq number, same as the evt2irq() macro */
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lsr \irqnr, \irqnr, #0x5
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subs \irqnr, \irqnr, #16
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1000:
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.endm
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@ -14,8 +14,21 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(CONFIG_ARM_GIC)
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#include <mach/entry-macro-gic.S>
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#else
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#include <mach/entry-macro-intc.S>
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#endif
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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.endm
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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.endm
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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@ -1,7 +1,4 @@
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#ifndef __ASM_MACH_HARDWARE_H
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#define __ASM_MACH_HARDWARE_H
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/* INTFLGA register - used by low level interrupt code in entry-macro.S */
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#define INTFLGA 0xe6980018
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#endif /* __ASM_MACH_HARDWARE_H */
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