Merge branch 'pci/trivial' into next
* pci/trivial: PCI: Clean up whitespace in linux/pci.h, pci/pci.h PCI: Tidy up pci/probe.c comments
This commit is contained in:
Bjorn Helgaas
Bjorn Helgaas
commit
01f095e46b
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@ -38,21 +38,21 @@ int pci_probe_reset_function(struct pci_dev *dev);
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* struct pci_platform_pm_ops - Firmware PM callbacks
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*
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* @is_manageable: returns 'true' if given device is power manageable by the
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* platform firmware
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* platform firmware
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*
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* @set_state: invokes the platform firmware to set the device's power state
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*
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* @get_state: queries the platform firmware for a device's current power state
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*
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* @choose_state: returns PCI power state of given device preferred by the
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* platform; to be used during system-wide transitions from a
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* sleeping state to the working state and vice versa
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* platform; to be used during system-wide transitions from a
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* sleeping state to the working state and vice versa
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*
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* @set_wakeup: enables/disables wakeup capability for the device
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*
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* @need_resume: returns 'true' if the given device (which is currently
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* suspended) needs to be resumed to be configured for system
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* wakeup.
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* suspended) needs to be resumed to be configured for system
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* wakeup.
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*
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* If given platform is generally capable of power managing PCI devices, all of
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* these callbacks are mandatory.
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@ -112,7 +112,7 @@ struct pci_vpd_ops {
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struct pci_vpd {
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const struct pci_vpd_ops *ops;
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struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
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struct bin_attribute *attr; /* Descriptor for sysfs VPD entry */
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struct mutex lock;
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unsigned int len;
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u16 flag;
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@ -199,7 +199,7 @@ extern const struct attribute_group *pci_bus_groups[];
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/**
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* pci_match_one_device - Tell if a PCI device structure has a matching
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* PCI device id structure
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* PCI device id structure
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* @id: single PCI device id structure to match
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* @dev: the PCI device structure to match against
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*
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@ -231,7 +231,7 @@ struct pci_slot_attribute {
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enum pci_bar_type {
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pci_bar_unknown, /* Standard PCI BAR probe */
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pci_bar_io, /* An io port BAR */
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pci_bar_io, /* An I/O port BAR */
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pci_bar_mem32, /* A 32-bit memory BAR */
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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@ -255,24 +255,24 @@ void pci_disable_bridge_window(struct pci_dev *dev);
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* capability position */
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int nres; /* number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total_VFs; /* total VFs associated with the PF */
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u16 initial_VFs; /* initial VFs associated with the PF */
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u16 num_VFs; /* number of VFs available */
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u16 offset; /* first VF Routing ID offset */
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u16 stride; /* following VF stride */
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u16 vf_device; /* VF device ID */
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u32 pgsz; /* page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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u8 max_VF_buses; /* max buses consumed by VFs */
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u16 driver_max_VFs; /* max num VFs driver supports */
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struct pci_dev *dev; /* lowest numbered PF */
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struct pci_dev *self; /* this PF */
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
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bool drivers_autoprobe; /* auto probing of VFs by driver */
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int pos; /* Capability position */
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int nres; /* Number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total_VFs; /* Total VFs associated with the PF */
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u16 initial_VFs; /* Initial VFs associated with the PF */
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u16 num_VFs; /* Number of VFs available */
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u16 offset; /* First VF Routing ID offset */
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u16 stride; /* Following VF stride */
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u16 vf_device; /* VF device ID */
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u32 pgsz; /* Page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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u8 max_VF_buses; /* Max buses consumed by VFs */
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u16 driver_max_VFs; /* Max num VFs driver supports */
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struct pci_dev *dev; /* Lowest numbered PF */
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struct pci_dev *self; /* This PF */
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
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bool drivers_autoprobe; /* Auto probing of VFs by driver */
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};
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/* pci_dev priv_flags */
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@ -335,7 +335,7 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
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if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
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return pci_sriov_resource_alignment(dev, resno);
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#endif
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
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return pci_cardbus_resource_alignment(res);
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return resource_alignment(res);
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}
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@ -69,8 +69,8 @@ static int find_anything(struct device *dev, void *data)
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}
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/*
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* Some device drivers need know if pci is initiated.
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* Basically, we think pci is not initiated when there
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* Some device drivers need know if PCI is initiated.
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* Basically, we think PCI is not initiated when there
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* is no device to be found on the pci_bus_type.
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*/
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int no_pci_devices(void)
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@ -116,12 +116,16 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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/*
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* Get the lowest of them to find the decode size, and from that
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* the extent.
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*/
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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/*
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* base == maxbase can be valid only if the BAR has already been
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* programmed with all 1s.
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*/
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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@ -164,7 +168,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
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#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
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/**
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* pci_read_base - read a PCI BAR
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* pci_read_base - Read a PCI BAR
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* @dev: the PCI device
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* @type: type of the BAR
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* @res: resource buffer to be filled in
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@ -764,7 +768,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
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bridge->bus = bus;
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/* temporarily move resources off the list */
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/* Temporarily move resources off the list */
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list_splice_init(&bridge->windows, &resources);
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bus->sysdata = bridge->sysdata;
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bus->msi = bridge->msi;
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@ -776,7 +780,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
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b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
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if (b) {
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/* If we already got to this bus through a different bridge, ignore it */
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/* Ignore it if we already got here via a different bridge */
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dev_dbg(&b->dev, "bus already known\n");
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err = -EEXIST;
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goto free;
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@ -869,9 +873,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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int i;
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int ret;
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/*
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* Allocate a new bus, and inherit stuff from the parent..
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*/
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/* Allocate a new bus and inherit stuff from the parent */
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child = pci_alloc_bus(parent);
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if (!child)
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return NULL;
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@ -882,16 +884,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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child->sysdata = parent->sysdata;
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child->bus_flags = parent->bus_flags;
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/* initialize some portions of the bus device, but don't register it
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* now as the parent is not properly set up yet.
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/*
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* Initialize some portions of the bus device, but don't register
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* it now as the parent is not properly set up yet.
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*/
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child->dev.class = &pcibus_class;
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dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
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/*
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* Set up the primary, secondary and subordinate
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* bus numbers.
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*/
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/* Set up the primary, secondary and subordinate bus numbers */
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child->number = child->busn_res.start = busnr;
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child->primary = parent->busn_res.start;
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child->busn_res.end = 0xff;
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@ -907,7 +907,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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pci_set_bus_of_node(child);
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pci_set_bus_speed(child);
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/* Set up default resource pointers and names.. */
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/* Set up default resource pointers and names */
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for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
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child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
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child->resource[i]->name = child->name;
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@ -1022,8 +1022,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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broken = 1;
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}
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/* Disable MasterAbortMode during probing to avoid reporting
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of bus errors (in some architectures) */
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/*
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* Disable Master-Abort Mode during probing to avoid reporting of
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* bus errors in some architectures.
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*/
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
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bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
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@ -1033,18 +1035,19 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
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!is_cardbus && !broken) {
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unsigned int cmax;
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/*
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* Bus already configured by firmware, process it in the first
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* pass and just note the configuration.
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* Bus already configured by firmware, process it in the
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* first pass and just note the configuration.
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*/
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if (pass)
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goto out;
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/*
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* The bus might already exist for two reasons: Either we are
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* rescanning the bus or the bus is reachable through more than
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* one bridge. The second case can happen with the i450NX
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* chipset.
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* The bus might already exist for two reasons: Either we
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* are rescanning the bus or the bus is reachable through
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* more than one bridge. The second case can happen with
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* the i450NX chipset.
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*/
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child = pci_find_bus(pci_domain_nr(bus), secondary);
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if (!child) {
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@ -1060,22 +1063,27 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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if (cmax > subordinate)
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pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
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subordinate, cmax);
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/* subordinate should equal child->busn_res.end */
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/* Subordinate should equal child->busn_res.end */
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if (subordinate > max)
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max = subordinate;
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} else {
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/*
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* We need to assign a number to this bus which we always
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* do in the second pass.
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*/
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if (!pass) {
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if (pcibios_assign_all_busses() || broken || is_cardbus)
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/* Temporarily disable forwarding of the
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configuration cycles on all bridges in
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this bus segment to avoid possible
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conflicts in the second pass between two
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bridges programmed with overlapping
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bus ranges. */
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/*
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* Temporarily disable forwarding of the
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* configuration cycles on all bridges in
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* this bus segment to avoid possible
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* conflicts in the second pass between two
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* bridges programmed with overlapping bus
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* ranges.
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*/
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pci_write_config_dword(dev, PCI_PRIMARY_BUS,
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buses & ~0xffffff);
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goto out;
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@ -1084,9 +1092,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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/* Clear errors */
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pci_write_config_word(dev, PCI_STATUS, 0xffff);
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/* Prevent assigning a bus number that already exists.
|
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* This can happen when a bridge is hot-plugged, so in
|
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* this case we only re-scan this bus. */
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||||
/*
|
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* Prevent assigning a bus number that already exists.
|
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* This can happen when a bridge is hot-plugged, so in this
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* case we only re-scan this bus.
|
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*/
|
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child = pci_find_bus(pci_domain_nr(bus), max+1);
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||||
if (!child) {
|
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child = pci_add_new_bus(bus, dev, max+1);
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||||
|
|
@ -1113,19 +1123,18 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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|||
buses |= CARDBUS_LATENCY_TIMER << 24;
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||||
}
|
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|
||||
/*
|
||||
* We need to blast all three values with a single write.
|
||||
*/
|
||||
/* We need to blast all three values with a single write */
|
||||
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
|
||||
|
||||
if (!is_cardbus) {
|
||||
child->bridge_ctl = bctl;
|
||||
max = pci_scan_child_bus_extend(child, available_buses);
|
||||
} else {
|
||||
|
||||
/*
|
||||
* For CardBus bridges, we leave 4 bus numbers
|
||||
* as cards with a PCI-to-PCI bridge can be
|
||||
* inserted later.
|
||||
* For CardBus bridges, we leave 4 bus numbers as
|
||||
* cards with a PCI-to-PCI bridge can be inserted
|
||||
* later.
|
||||
*/
|
||||
for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
|
||||
struct pci_bus *parent = bus;
|
||||
|
|
@ -1141,10 +1150,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
|
|||
parent = parent->parent;
|
||||
}
|
||||
if (j) {
|
||||
|
||||
/*
|
||||
* Often, there are two cardbus bridges
|
||||
* -- try to leave one valid bus number
|
||||
* for each one.
|
||||
* Often, there are two CardBus
|
||||
* bridges -- try to leave one
|
||||
* valid bus number for each one.
|
||||
*/
|
||||
i /= 2;
|
||||
break;
|
||||
|
|
@ -1152,9 +1162,8 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
|
|||
}
|
||||
max += i;
|
||||
}
|
||||
/*
|
||||
* Set the subordinate bus number to its real value.
|
||||
*/
|
||||
|
||||
/* Set subordinate bus number to its real value */
|
||||
pci_bus_update_busn_res_end(child, max);
|
||||
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
|
||||
}
|
||||
|
|
@ -1295,7 +1304,7 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
|
||||
* pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
|
||||
* @dev: PCI device
|
||||
*
|
||||
* PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
|
||||
|
|
@ -1332,7 +1341,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_cfg_space_size - get the configuration space size of the PCI device.
|
||||
* pci_cfg_space_size - Get the configuration space size of the PCI device
|
||||
* @dev: PCI device
|
||||
*
|
||||
* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
|
||||
|
|
@ -1398,7 +1407,7 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
|
||||
* pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
|
||||
* @dev: PCI device
|
||||
*
|
||||
* Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
|
||||
|
|
@ -1426,11 +1435,11 @@ static int pci_intx_mask_broken(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_setup_device - fill in class and map information of a device
|
||||
* pci_setup_device - Fill in class and map information of a device
|
||||
* @dev: the device structure to fill
|
||||
*
|
||||
* Initialize the device structure with information about the device's
|
||||
* vendor,class,memory and IO-space addresses,IRQ lines etc.
|
||||
* vendor,class,memory and IO-space addresses, IRQ lines etc.
|
||||
* Called at initialisation of the PCI subsystem and by CardBus services.
|
||||
* Returns 0 on success and negative if unknown type of device (not normal,
|
||||
* bridge or CardBus).
|
||||
|
|
@ -1456,8 +1465,11 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
set_pcie_port_type(dev);
|
||||
|
||||
pci_dev_assign_slot(dev);
|
||||
/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
|
||||
set this higher, assuming the system even supports it. */
|
||||
|
||||
/*
|
||||
* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
|
||||
* set this higher, assuming the system even supports it.
|
||||
*/
|
||||
dev->dma_mask = 0xffffffff;
|
||||
|
||||
dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
|
||||
|
|
@ -1471,10 +1483,10 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
|
||||
dev->vendor, dev->device, dev->hdr_type, dev->class);
|
||||
|
||||
/* need to have dev->class ready */
|
||||
/* Need to have dev->class ready */
|
||||
dev->cfg_size = pci_cfg_space_size(dev);
|
||||
|
||||
/* need to have dev->cfg_size ready */
|
||||
/* Need to have dev->cfg_size ready */
|
||||
set_pcie_thunderbolt(dev);
|
||||
|
||||
/* "Unknown power state" */
|
||||
|
|
@ -1482,7 +1494,8 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
|
||||
/* Early fixups, before probing the BARs */
|
||||
pci_fixup_device(pci_fixup_early, dev);
|
||||
/* device class may be changed after fixup */
|
||||
|
||||
/* Device class may be changed after fixup */
|
||||
class = dev->class >> 8;
|
||||
|
||||
if (dev->non_compliant_bars) {
|
||||
|
|
@ -1553,9 +1566,12 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
|
||||
if (class != PCI_CLASS_BRIDGE_PCI)
|
||||
goto bad;
|
||||
/* The PCI-to-PCI bridge spec requires that subtractive
|
||||
decoding (i.e. transparent) bridge must have programming
|
||||
interface code of 0x01. */
|
||||
|
||||
/*
|
||||
* The PCI-to-PCI bridge spec requires that subtractive
|
||||
* decoding (i.e. transparent) bridge must have programming
|
||||
* interface code of 0x01.
|
||||
*/
|
||||
pci_read_irq(dev);
|
||||
dev->transparent = ((dev->class & 0xff) == 1);
|
||||
pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
|
||||
|
|
@ -1771,6 +1787,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
|
|||
/* Initialize Advanced Error Capabilities and Control Register */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
|
||||
reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
|
||||
|
||||
/* Don't enable ECRC generation or checking if unsupported */
|
||||
if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
|
||||
reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
|
||||
|
|
@ -1934,10 +1951,11 @@ static void pci_release_capabilities(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_release_dev - free a pci device structure when all users of it are finished.
|
||||
* pci_release_dev - Free a PCI device structure when all users of it are
|
||||
* finished
|
||||
* @dev: device that's been disconnected
|
||||
*
|
||||
* Will be called only by the device core when all users of this pci device are
|
||||
* Will be called only by the device core when all users of this PCI device are
|
||||
* done.
|
||||
*/
|
||||
static void pci_release_dev(struct device *dev)
|
||||
|
|
@ -2025,7 +2043,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
|
|||
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
|
||||
return false;
|
||||
|
||||
/* some broken boards return 0 or ~0 if a slot is empty: */
|
||||
/* Some broken boards return 0 or ~0 if a slot is empty: */
|
||||
if (*l == 0xffffffff || *l == 0x00000000 ||
|
||||
*l == 0x0000ffff || *l == 0xffff0000)
|
||||
return false;
|
||||
|
|
@ -2038,8 +2056,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
|
|||
EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
|
||||
|
||||
/*
|
||||
* Read the config data for a PCI device, sanity-check it
|
||||
* and fill in the dev structure...
|
||||
* Read the config data for a PCI device, sanity-check it,
|
||||
* and fill in the dev structure.
|
||||
*/
|
||||
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
|
||||
{
|
||||
|
|
@ -2105,7 +2123,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/*
|
||||
* This is the equivalent of pci_host_bridge_msi_domain that acts on
|
||||
* This is the equivalent of pci_host_bridge_msi_domain() that acts on
|
||||
* devices. Firmware interfaces that can select the MSI domain on a
|
||||
* per-device basis should be called from here.
|
||||
*/
|
||||
|
|
@ -2114,7 +2132,7 @@ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
|
|||
struct irq_domain *d;
|
||||
|
||||
/*
|
||||
* If a domain has been set through the pcibios_add_device
|
||||
* If a domain has been set through the pcibios_add_device()
|
||||
* callback, then this is the one (platform code knows best).
|
||||
*/
|
||||
d = dev_get_msi_domain(&dev->dev);
|
||||
|
|
@ -2168,10 +2186,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
|||
/* Fix up broken headers */
|
||||
pci_fixup_device(pci_fixup_header, dev);
|
||||
|
||||
/* moved out from quirk header fixup code */
|
||||
/* Moved out from quirk header fixup code */
|
||||
pci_reassigndev_resource_alignment(dev);
|
||||
|
||||
/* Clear the state_saved flag. */
|
||||
/* Clear the state_saved flag */
|
||||
dev->state_saved = false;
|
||||
|
||||
/* Initialize various capabilities */
|
||||
|
|
@ -2188,7 +2206,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
|||
ret = pcibios_add_device(dev);
|
||||
WARN_ON(ret < 0);
|
||||
|
||||
/* Setup MSI irq domain */
|
||||
/* Set up MSI IRQ domain */
|
||||
pci_set_msi_domain(dev);
|
||||
|
||||
/* Notifier could use PCI capabilities */
|
||||
|
|
@ -2272,9 +2290,9 @@ static int only_one_child(struct pci_bus *bus)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_scan_slot - scan a PCI slot on a bus for devices.
|
||||
* pci_scan_slot - Scan a PCI slot on a bus for devices
|
||||
* @bus: PCI bus to scan
|
||||
* @devfn: slot number to scan (must have zero function.)
|
||||
* @devfn: slot number to scan (must have zero function)
|
||||
*
|
||||
* Scan a PCI slot on the specified PCI bus for devices, adding
|
||||
* discovered devices to the @bus->devices list. New devices
|
||||
|
|
@ -2305,7 +2323,7 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
|
|||
}
|
||||
}
|
||||
|
||||
/* only one slot has pcie device */
|
||||
/* Only one slot has PCIe device */
|
||||
if (bus->self && nr)
|
||||
pcie_aspm_init_link_state(bus->self);
|
||||
|
||||
|
|
@ -2354,7 +2372,9 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
|
|||
|
||||
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
dev->bus->self)
|
||||
/* For "Performance", the assumption is made that
|
||||
|
||||
/*
|
||||
* For "Performance", the assumption is made that
|
||||
* downstream communication will never be larger than
|
||||
* the MRRS. So, the MPS only needs to be configured
|
||||
* for the upstream communication. This being the case,
|
||||
|
|
@ -2378,20 +2398,23 @@ static void pcie_write_mrrs(struct pci_dev *dev)
|
|||
{
|
||||
int rc, mrrs;
|
||||
|
||||
/* In the "safe" case, do not configure the MRRS. There appear to be
|
||||
/*
|
||||
* In the "safe" case, do not configure the MRRS. There appear to be
|
||||
* issues with setting MRRS to 0 on a number of devices.
|
||||
*/
|
||||
if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
|
||||
return;
|
||||
|
||||
/* For Max performance, the MRRS must be set to the largest supported
|
||||
/*
|
||||
* For max performance, the MRRS must be set to the largest supported
|
||||
* value. However, it cannot be configured larger than the MPS the
|
||||
* device or the bus can support. This should already be properly
|
||||
* configured by a prior call to pcie_write_mps.
|
||||
* configured by a prior call to pcie_write_mps().
|
||||
*/
|
||||
mrrs = pcie_get_mps(dev);
|
||||
|
||||
/* MRRS is a R/W register. Invalid values can be written, but a
|
||||
/*
|
||||
* MRRS is a R/W register. Invalid values can be written, but a
|
||||
* subsequent read will verify if the value is acceptable or not.
|
||||
* If the MRRS value provided is not acceptable (e.g., too large),
|
||||
* shrink the value until it is acceptable to the HW.
|
||||
|
|
@ -2433,7 +2456,8 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
|
||||
/*
|
||||
* pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
|
||||
* parents then children fashion. If this changes, then this code will not
|
||||
* work as designed.
|
||||
*/
|
||||
|
|
@ -2447,7 +2471,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus)
|
|||
if (!pci_is_pcie(bus->self))
|
||||
return;
|
||||
|
||||
/* FIXME - Peer to peer DMA is possible, though the endpoint would need
|
||||
/*
|
||||
* FIXME - Peer to peer DMA is possible, though the endpoint would need
|
||||
* to be aware of the MPS of the destination. To work around this,
|
||||
* simply force the MPS of the entire system to the smallest possible.
|
||||
*/
|
||||
|
|
@ -2501,7 +2526,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
|
|||
for (devfn = 0; devfn < 0x100; devfn += 8)
|
||||
pci_scan_slot(bus, devfn);
|
||||
|
||||
/* Reserve buses for SR-IOV capability. */
|
||||
/* Reserve buses for SR-IOV capability */
|
||||
used_buses = pci_iov_bus_range(bus);
|
||||
max += used_buses;
|
||||
|
||||
|
|
@ -2543,6 +2568,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
|
|||
unsigned int buses = 0;
|
||||
|
||||
if (!hotplug_bridges && normal_bridges == 1) {
|
||||
|
||||
/*
|
||||
* There is only one bridge on the bus (upstream
|
||||
* port) so it gets all available buses which it
|
||||
|
|
@ -2551,6 +2577,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
|
|||
*/
|
||||
buses = available_buses;
|
||||
} else if (dev->is_hotplug_bridge) {
|
||||
|
||||
/*
|
||||
* Distribute the extra buses between hotplug
|
||||
* bridges if any.
|
||||
|
|
@ -2609,8 +2636,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
|
|||
EXPORT_SYMBOL_GPL(pci_scan_child_bus);
|
||||
|
||||
/**
|
||||
* pcibios_root_bridge_prepare - Platform-specific host bridge setup.
|
||||
* @bridge: Host bridge to set up.
|
||||
* pcibios_root_bridge_prepare - Platform-specific host bridge setup
|
||||
* @bridge: Host bridge to set up
|
||||
*
|
||||
* Default empty implementation. Replace with an architecture-specific setup
|
||||
* routine, if necessary.
|
||||
|
|
@ -2813,7 +2840,7 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
|
|||
EXPORT_SYMBOL(pci_scan_bus);
|
||||
|
||||
/**
|
||||
* pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
|
||||
* pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
|
||||
* @bridge: PCI bridge for the bus to scan
|
||||
*
|
||||
* Scan a PCI bus and child buses for new devices, add them,
|
||||
|
|
@ -2838,11 +2865,11 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
|
|||
}
|
||||
|
||||
/**
|
||||
* pci_rescan_bus - scan a PCI bus for devices.
|
||||
* pci_rescan_bus - Scan a PCI bus for devices
|
||||
* @bus: PCI bus to scan
|
||||
*
|
||||
* Scan a PCI bus and child buses for new devices, adds them,
|
||||
* and enables them.
|
||||
* Scan a PCI bus and child buses for new devices, add them,
|
||||
* and enable them.
|
||||
*
|
||||
* Returns the max number of subordinate bus discovered.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -48,17 +48,17 @@
|
|||
* In the interest of not exposing interfaces to user-space unnecessarily,
|
||||
* the following kernel-only defines are being added here.
|
||||
*/
|
||||
#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
|
||||
#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
|
||||
/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
|
||||
#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
|
||||
|
||||
/* pci_slot represents a physical slot */
|
||||
struct pci_slot {
|
||||
struct pci_bus *bus; /* The bus this slot is on */
|
||||
struct list_head list; /* node in list of slots on this bus */
|
||||
struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
|
||||
unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
|
||||
struct kobject kobj;
|
||||
struct pci_bus *bus; /* Bus this slot is on */
|
||||
struct list_head list; /* Node in list of slots */
|
||||
struct hotplug_slot *hotplug; /* Hotplug info (move here) */
|
||||
unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
|
||||
struct kobject kobj;
|
||||
};
|
||||
|
||||
static inline const char *pci_slot_name(const struct pci_slot *slot)
|
||||
|
|
@ -72,9 +72,7 @@ enum pci_mmap_state {
|
|||
pci_mmap_mem
|
||||
};
|
||||
|
||||
/*
|
||||
* For PCI devices, the region numbers are assigned this way:
|
||||
*/
|
||||
/* For PCI devices, the region numbers are assigned this way: */
|
||||
enum {
|
||||
/* #0-5: standard PCI resources */
|
||||
PCI_STD_RESOURCES,
|
||||
|
|
@ -83,23 +81,23 @@ enum {
|
|||
/* #6: expansion ROM resource */
|
||||
PCI_ROM_RESOURCE,
|
||||
|
||||
/* device specific resources */
|
||||
/* Device-specific resources */
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
PCI_IOV_RESOURCES,
|
||||
PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
|
||||
#endif
|
||||
|
||||
/* resources assigned to buses behind the bridge */
|
||||
/* Resources assigned to buses behind the bridge */
|
||||
#define PCI_BRIDGE_RESOURCE_NUM 4
|
||||
|
||||
PCI_BRIDGE_RESOURCES,
|
||||
PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
|
||||
PCI_BRIDGE_RESOURCE_NUM - 1,
|
||||
|
||||
/* total resources associated with a PCI device */
|
||||
/* Total resources associated with a PCI device */
|
||||
PCI_NUM_RESOURCES,
|
||||
|
||||
/* preserve this for compatibility */
|
||||
/* Preserve this for compatibility */
|
||||
DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
|
||||
};
|
||||
|
||||
|
|
@ -152,9 +150,10 @@ static inline const char *pci_power_name(pci_power_t state)
|
|||
#define PCI_PM_D3COLD_WAIT 100
|
||||
#define PCI_PM_BUS_WAIT 50
|
||||
|
||||
/** The pci_channel state describes connectivity between the CPU and
|
||||
* the pci device. If some PCI bus between here and the pci device
|
||||
* has crashed or locked up, this info is reflected here.
|
||||
/**
|
||||
* The pci_channel state describes connectivity between the CPU and
|
||||
* the PCI device. If some PCI bus between here and the PCI device
|
||||
* has crashed or locked up, this info is reflected here.
|
||||
*/
|
||||
typedef unsigned int __bitwise pci_channel_state_t;
|
||||
|
||||
|
|
@ -184,9 +183,7 @@ enum pcie_reset_state {
|
|||
|
||||
typedef unsigned short __bitwise pci_dev_flags_t;
|
||||
enum pci_dev_flags {
|
||||
/* INTX_DISABLE in PCI_COMMAND register disables MSI
|
||||
* generation too.
|
||||
*/
|
||||
/* INTX_DISABLE in PCI_COMMAND register disables MSI too */
|
||||
PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
|
||||
/* Device configuration is irrevocably lost if disabled into D3 */
|
||||
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
|
||||
|
|
@ -202,7 +199,7 @@ enum pci_dev_flags {
|
|||
PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
|
||||
/* Get VPD from function 0 VPD */
|
||||
PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
|
||||
/* a non-root bridge where translation occurs, stop alias search here */
|
||||
/* A non-root bridge where translation occurs, stop alias search here */
|
||||
PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
|
||||
/* Do not use FLR even if device advertises PCI_AF_CAP */
|
||||
PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
|
||||
|
|
@ -222,17 +219,17 @@ enum pci_bus_flags {
|
|||
PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
|
||||
};
|
||||
|
||||
/* These values come from the PCI Express Spec */
|
||||
/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
|
||||
enum pcie_link_width {
|
||||
PCIE_LNK_WIDTH_RESRV = 0x00,
|
||||
PCIE_LNK_X1 = 0x01,
|
||||
PCIE_LNK_X2 = 0x02,
|
||||
PCIE_LNK_X4 = 0x04,
|
||||
PCIE_LNK_X8 = 0x08,
|
||||
PCIE_LNK_X12 = 0x0C,
|
||||
PCIE_LNK_X12 = 0x0c,
|
||||
PCIE_LNK_X16 = 0x10,
|
||||
PCIE_LNK_X32 = 0x20,
|
||||
PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
|
||||
PCIE_LNK_WIDTH_UNKNOWN = 0xff,
|
||||
};
|
||||
|
||||
/* Based on the PCI Hotplug Spec, but some values are made up by us */
|
||||
|
|
@ -263,15 +260,15 @@ enum pci_bus_speed {
|
|||
};
|
||||
|
||||
struct pci_cap_saved_data {
|
||||
u16 cap_nr;
|
||||
bool cap_extended;
|
||||
unsigned int size;
|
||||
u32 data[0];
|
||||
u16 cap_nr;
|
||||
bool cap_extended;
|
||||
unsigned int size;
|
||||
u32 data[0];
|
||||
};
|
||||
|
||||
struct pci_cap_saved_state {
|
||||
struct hlist_node next;
|
||||
struct pci_cap_saved_data cap;
|
||||
struct hlist_node next;
|
||||
struct pci_cap_saved_data cap;
|
||||
};
|
||||
|
||||
struct irq_affinity;
|
||||
|
|
@ -280,19 +277,17 @@ struct pci_vpd;
|
|||
struct pci_sriov;
|
||||
struct pci_ats;
|
||||
|
||||
/*
|
||||
* The pci_dev structure is used to describe PCI devices.
|
||||
*/
|
||||
/* The pci_dev structure describes PCI devices */
|
||||
struct pci_dev {
|
||||
struct list_head bus_list; /* node in per-bus list */
|
||||
struct pci_bus *bus; /* bus this device is on */
|
||||
struct pci_bus *subordinate; /* bus this device bridges to */
|
||||
struct list_head bus_list; /* Node in per-bus list */
|
||||
struct pci_bus *bus; /* Bus this device is on */
|
||||
struct pci_bus *subordinate; /* Bus this device bridges to */
|
||||
|
||||
void *sysdata; /* hook for sys-specific extension */
|
||||
struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
|
||||
void *sysdata; /* Hook for sys-specific extension */
|
||||
struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
|
||||
struct pci_slot *slot; /* Physical slot this device is in */
|
||||
|
||||
unsigned int devfn; /* encoded device & function index */
|
||||
unsigned int devfn; /* Encoded device & function index */
|
||||
unsigned short vendor;
|
||||
unsigned short device;
|
||||
unsigned short subsystem_vendor;
|
||||
|
|
@ -307,12 +302,12 @@ struct pci_dev {
|
|||
u8 msi_cap; /* MSI capability offset */
|
||||
u8 msix_cap; /* MSI-X capability offset */
|
||||
u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
|
||||
u8 rom_base_reg; /* which config register controls the ROM */
|
||||
u8 pin; /* which interrupt pin this device uses */
|
||||
u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
|
||||
unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
|
||||
u8 rom_base_reg; /* Config register controlling ROM */
|
||||
u8 pin; /* Interrupt pin this device uses */
|
||||
u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
|
||||
unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
|
||||
|
||||
struct pci_driver *driver; /* which driver has allocated this device */
|
||||
struct pci_driver *driver; /* Driver bound to this device */
|
||||
u64 dma_mask; /* Mask of the bits of bus address this
|
||||
device implements. Normally this is
|
||||
0xffffffff. You only need to change
|
||||
|
|
@ -321,9 +316,9 @@ struct pci_dev {
|
|||
|
||||
struct device_dma_parameters dma_parms;
|
||||
|
||||
pci_power_t current_state; /* Current operating state. In ACPI-speak,
|
||||
this is D0-D3, D0 being fully functional,
|
||||
and D3 being off. */
|
||||
pci_power_t current_state; /* Current operating state. In ACPI,
|
||||
this is D0-D3, D0 being fully
|
||||
functional, and D3 being off. */
|
||||
u8 pm_cap; /* PM capability offset */
|
||||
unsigned int pme_support:5; /* Bitmask of states from which PME#
|
||||
can be generated */
|
||||
|
|
@ -334,10 +329,10 @@ struct pci_dev {
|
|||
unsigned int no_d3cold:1; /* D3cold is forbidden */
|
||||
unsigned int bridge_d3:1; /* Allow D3 for bridge */
|
||||
unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
|
||||
unsigned int mmio_always_on:1; /* disallow turning off io/mem
|
||||
decoding during bar sizing */
|
||||
unsigned int mmio_always_on:1; /* Disallow turning off io/mem
|
||||
decoding during BAR sizing */
|
||||
unsigned int wakeup_prepared:1;
|
||||
unsigned int runtime_d3cold:1; /* whether go through runtime
|
||||
unsigned int runtime_d3cold:1; /* Whether go through runtime
|
||||
D3cold, not set for devices
|
||||
powered on/off by the
|
||||
corresponding bridge */
|
||||
|
|
@ -354,10 +349,10 @@ struct pci_dev {
|
|||
supported from root to here */
|
||||
#endif
|
||||
|
||||
pci_channel_state_t error_state; /* current connectivity state */
|
||||
struct device dev; /* Generic device interface */
|
||||
pci_channel_state_t error_state; /* Current connectivity state */
|
||||
struct device dev; /* Generic device interface */
|
||||
|
||||
int cfg_size; /* Size of configuration space */
|
||||
int cfg_size; /* Size of config space */
|
||||
|
||||
/*
|
||||
* Instead of touching interrupt line and base address registers
|
||||
|
|
@ -366,47 +361,47 @@ struct pci_dev {
|
|||
unsigned int irq;
|
||||
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
|
||||
|
||||
bool match_driver; /* Skip attaching driver */
|
||||
/* These fields are used by common fixups */
|
||||
unsigned int transparent:1; /* Subtractive decode PCI bridge */
|
||||
unsigned int multifunction:1;/* Part of multi-function device */
|
||||
/* keep track of device state */
|
||||
bool match_driver; /* Skip attaching driver */
|
||||
|
||||
unsigned int transparent:1; /* Subtractive decode bridge */
|
||||
unsigned int multifunction:1; /* Multi-function device */
|
||||
|
||||
unsigned int is_added:1;
|
||||
unsigned int is_busmaster:1; /* device is busmaster */
|
||||
unsigned int no_msi:1; /* device may not use msi */
|
||||
unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
|
||||
unsigned int block_cfg_access:1; /* config space access is blocked */
|
||||
unsigned int broken_parity_status:1; /* Device generates false positive parity */
|
||||
unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
|
||||
unsigned int is_busmaster:1; /* Is busmaster */
|
||||
unsigned int no_msi:1; /* May not use MSI */
|
||||
unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
|
||||
unsigned int block_cfg_access:1; /* Config space access blocked */
|
||||
unsigned int broken_parity_status:1; /* Generates false positive parity */
|
||||
unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
|
||||
unsigned int msi_enabled:1;
|
||||
unsigned int msix_enabled:1;
|
||||
unsigned int ari_enabled:1; /* ARI forwarding */
|
||||
unsigned int ats_enabled:1; /* Address Translation Service */
|
||||
unsigned int ari_enabled:1; /* ARI forwarding */
|
||||
unsigned int ats_enabled:1; /* Address Translation Svc */
|
||||
unsigned int pasid_enabled:1; /* Process Address Space ID */
|
||||
unsigned int pri_enabled:1; /* Page Request Interface */
|
||||
unsigned int is_managed:1;
|
||||
unsigned int needs_freset:1; /* Dev requires fundamental reset */
|
||||
unsigned int needs_freset:1; /* Requires fundamental reset */
|
||||
unsigned int state_saved:1;
|
||||
unsigned int is_physfn:1;
|
||||
unsigned int is_virtfn:1;
|
||||
unsigned int reset_fn:1;
|
||||
unsigned int is_hotplug_bridge:1;
|
||||
unsigned int is_thunderbolt:1; /* Thunderbolt controller */
|
||||
unsigned int __aer_firmware_first_valid:1;
|
||||
unsigned int is_hotplug_bridge:1;
|
||||
unsigned int is_thunderbolt:1; /* Thunderbolt controller */
|
||||
unsigned int __aer_firmware_first_valid:1;
|
||||
unsigned int __aer_firmware_first:1;
|
||||
unsigned int broken_intx_masking:1; /* INTx masking can't be used */
|
||||
unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
|
||||
unsigned int broken_intx_masking:1; /* INTx masking can't be used */
|
||||
unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
|
||||
unsigned int irq_managed:1;
|
||||
unsigned int has_secondary_link:1;
|
||||
unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
|
||||
unsigned int is_probed:1; /* device probing in progress */
|
||||
unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
|
||||
unsigned int is_probed:1; /* Device probing in progress */
|
||||
pci_dev_flags_t dev_flags;
|
||||
atomic_t enable_cnt; /* pci_enable_device has been called */
|
||||
|
||||
u32 saved_config_space[16]; /* config space saved at suspend time */
|
||||
u32 saved_config_space[16]; /* Config space saved at suspend time */
|
||||
struct hlist_head saved_cap_space;
|
||||
struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
|
||||
int rom_attr_enabled; /* has display of the rom attribute been enabled? */
|
||||
struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
|
||||
int rom_attr_enabled; /* Display of ROM attribute enabled? */
|
||||
struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
|
||||
struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
|
||||
|
||||
|
|
@ -421,12 +416,12 @@ struct pci_dev {
|
|||
struct pci_vpd *vpd;
|
||||
#ifdef CONFIG_PCI_ATS
|
||||
union {
|
||||
struct pci_sriov *sriov; /* SR-IOV capability related */
|
||||
struct pci_dev *physfn; /* the PF this VF is associated with */
|
||||
struct pci_sriov *sriov; /* PF: SR-IOV info */
|
||||
struct pci_dev *physfn; /* VF: related PF */
|
||||
};
|
||||
u16 ats_cap; /* ATS Capability offset */
|
||||
u8 ats_stu; /* ATS Smallest Translation Unit */
|
||||
atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
|
||||
atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_PRI
|
||||
u32 pri_reqs_alloc; /* Number of PRI requests allocated */
|
||||
|
|
@ -434,11 +429,11 @@ struct pci_dev {
|
|||
#ifdef CONFIG_PCI_PASID
|
||||
u16 pasid_features;
|
||||
#endif
|
||||
phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
|
||||
size_t romlen; /* Length of ROM if it's not from the BAR */
|
||||
char *driver_override; /* Driver name to force a match */
|
||||
phys_addr_t rom; /* Physical address if not from BAR */
|
||||
size_t romlen; /* Length if not from BAR */
|
||||
char *driver_override; /* Driver name to force a match */
|
||||
|
||||
unsigned long priv_flags; /* Private flags for the pci driver */
|
||||
unsigned long priv_flags; /* Private flags for the PCI driver */
|
||||
};
|
||||
|
||||
static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
|
||||
|
|
@ -461,26 +456,26 @@ static inline int pci_channel_offline(struct pci_dev *pdev)
|
|||
}
|
||||
|
||||
struct pci_host_bridge {
|
||||
struct device dev;
|
||||
struct pci_bus *bus; /* root bus */
|
||||
struct pci_ops *ops;
|
||||
void *sysdata;
|
||||
int busnr;
|
||||
struct device dev;
|
||||
struct pci_bus *bus; /* Root bus */
|
||||
struct pci_ops *ops;
|
||||
void *sysdata;
|
||||
int busnr;
|
||||
struct list_head windows; /* resource_entry */
|
||||
u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
|
||||
u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
|
||||
int (*map_irq)(const struct pci_dev *, u8, u8);
|
||||
void (*release_fn)(struct pci_host_bridge *);
|
||||
void *release_data;
|
||||
void *release_data;
|
||||
struct msi_controller *msi;
|
||||
unsigned int ignore_reset_delay:1; /* for entire hierarchy */
|
||||
unsigned int no_ext_tags:1; /* no Extended Tags */
|
||||
unsigned int ignore_reset_delay:1; /* For entire hierarchy */
|
||||
unsigned int no_ext_tags:1; /* No Extended Tags */
|
||||
/* Resource alignment requirements */
|
||||
resource_size_t (*align_resource)(struct pci_dev *dev,
|
||||
const struct resource *res,
|
||||
resource_size_t start,
|
||||
resource_size_t size,
|
||||
resource_size_t align);
|
||||
unsigned long private[0] ____cacheline_aligned;
|
||||
unsigned long private[0] ____cacheline_aligned;
|
||||
};
|
||||
|
||||
#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
|
||||
|
|
@ -502,8 +497,8 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge);
|
|||
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
|
||||
|
||||
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
|
||||
void (*release_fn)(struct pci_host_bridge *),
|
||||
void *release_data);
|
||||
void (*release_fn)(struct pci_host_bridge *),
|
||||
void *release_data);
|
||||
|
||||
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
|
||||
|
||||
|
|
@ -523,32 +518,32 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
|
|||
#define PCI_SUBTRACTIVE_DECODE 0x1
|
||||
|
||||
struct pci_bus_resource {
|
||||
struct list_head list;
|
||||
struct resource *res;
|
||||
unsigned int flags;
|
||||
struct list_head list;
|
||||
struct resource *res;
|
||||
unsigned int flags;
|
||||
};
|
||||
|
||||
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
|
||||
|
||||
struct pci_bus {
|
||||
struct list_head node; /* node in list of buses */
|
||||
struct pci_bus *parent; /* parent bus this bridge is on */
|
||||
struct list_head children; /* list of child buses */
|
||||
struct list_head devices; /* list of devices on this bus */
|
||||
struct pci_dev *self; /* bridge device as seen by parent */
|
||||
struct list_head slots; /* list of slots on this bus;
|
||||
struct list_head node; /* Node in list of buses */
|
||||
struct pci_bus *parent; /* Parent bus this bridge is on */
|
||||
struct list_head children; /* List of child buses */
|
||||
struct list_head devices; /* List of devices on this bus */
|
||||
struct pci_dev *self; /* Bridge device as seen by parent */
|
||||
struct list_head slots; /* List of slots on this bus;
|
||||
protected by pci_slot_mutex */
|
||||
struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
|
||||
struct list_head resources; /* address space routed to this bus */
|
||||
struct resource busn_res; /* bus numbers routed to this bus */
|
||||
struct list_head resources; /* Address space routed to this bus */
|
||||
struct resource busn_res; /* Bus numbers routed to this bus */
|
||||
|
||||
struct pci_ops *ops; /* configuration access functions */
|
||||
struct pci_ops *ops; /* Configuration access functions */
|
||||
struct msi_controller *msi; /* MSI controller */
|
||||
void *sysdata; /* hook for sys-specific extension */
|
||||
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
|
||||
void *sysdata; /* Hook for sys-specific extension */
|
||||
struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
|
||||
|
||||
unsigned char number; /* bus number */
|
||||
unsigned char primary; /* number of primary bridge */
|
||||
unsigned char number; /* Bus number */
|
||||
unsigned char primary; /* Number of primary bridge */
|
||||
unsigned char max_bus_speed; /* enum pci_bus_speed */
|
||||
unsigned char cur_bus_speed; /* enum pci_bus_speed */
|
||||
#ifdef CONFIG_PCI_DOMAINS_GENERIC
|
||||
|
|
@ -557,12 +552,12 @@ struct pci_bus {
|
|||
|
||||
char name[48];
|
||||
|
||||
unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
|
||||
pci_bus_flags_t bus_flags; /* inherited by child buses */
|
||||
unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
|
||||
pci_bus_flags_t bus_flags; /* Inherited by child buses */
|
||||
struct device *bridge;
|
||||
struct device dev;
|
||||
struct bin_attribute *legacy_io; /* legacy I/O for this bus */
|
||||
struct bin_attribute *legacy_mem; /* legacy mem */
|
||||
struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
|
||||
struct bin_attribute *legacy_mem; /* Legacy mem */
|
||||
unsigned int is_added:1;
|
||||
};
|
||||
|
||||
|
|
@ -619,9 +614,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
|
|||
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Error values that may be returned by PCI functions.
|
||||
*/
|
||||
/* Error values that may be returned by PCI functions */
|
||||
#define PCIBIOS_SUCCESSFUL 0x00
|
||||
#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
|
||||
#define PCIBIOS_BAD_VENDOR_ID 0x83
|
||||
|
|
@ -630,9 +623,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
|
|||
#define PCIBIOS_SET_FAILED 0x88
|
||||
#define PCIBIOS_BUFFER_TOO_SMALL 0x89
|
||||
|
||||
/*
|
||||
* Translate above to generic errno for passing back through non-PCI code.
|
||||
*/
|
||||
/* Translate above to generic errno for passing back through non-PCI code */
|
||||
static inline int pcibios_err_to_errno(int err)
|
||||
{
|
||||
if (err <= PCIBIOS_SUCCESSFUL)
|
||||
|
|
@ -682,13 +673,13 @@ typedef u32 pci_bus_addr_t;
|
|||
#endif
|
||||
|
||||
struct pci_bus_region {
|
||||
pci_bus_addr_t start;
|
||||
pci_bus_addr_t end;
|
||||
pci_bus_addr_t start;
|
||||
pci_bus_addr_t end;
|
||||
};
|
||||
|
||||
struct pci_dynids {
|
||||
spinlock_t lock; /* protects list, index */
|
||||
struct list_head list; /* for IDs added at runtime */
|
||||
spinlock_t lock; /* Protects list, index */
|
||||
struct list_head list; /* For IDs added at runtime */
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -702,13 +693,13 @@ struct pci_dynids {
|
|||
typedef unsigned int __bitwise pci_ers_result_t;
|
||||
|
||||
enum pci_ers_result {
|
||||
/* no result/none/not supported in device driver */
|
||||
/* No result/none/not supported in device driver */
|
||||
PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
|
||||
|
||||
/* Device driver can recover without slot reset */
|
||||
PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
|
||||
|
||||
/* Device driver wants slot to be reset. */
|
||||
/* Device driver wants slot to be reset */
|
||||
PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
|
||||
|
||||
/* Device has completely failed, is unrecoverable */
|
||||
|
|
@ -744,27 +735,27 @@ struct pci_error_handlers {
|
|||
|
||||
struct module;
|
||||
struct pci_driver {
|
||||
struct list_head node;
|
||||
const char *name;
|
||||
const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
|
||||
int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
|
||||
void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
|
||||
int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
|
||||
int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
|
||||
int (*resume_early) (struct pci_dev *dev);
|
||||
int (*resume) (struct pci_dev *dev); /* Device woken up */
|
||||
struct list_head node;
|
||||
const char *name;
|
||||
const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
|
||||
int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
|
||||
void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
|
||||
int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
|
||||
int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
|
||||
int (*resume_early)(struct pci_dev *dev);
|
||||
int (*resume) (struct pci_dev *dev); /* Device woken up */
|
||||
void (*shutdown) (struct pci_dev *dev);
|
||||
int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
|
||||
int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
|
||||
const struct pci_error_handlers *err_handler;
|
||||
const struct attribute_group **groups;
|
||||
struct device_driver driver;
|
||||
struct pci_dynids dynids;
|
||||
struct pci_dynids dynids;
|
||||
};
|
||||
|
||||
#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
|
||||
|
||||
/**
|
||||
* PCI_DEVICE - macro used to describe a specific pci device
|
||||
* PCI_DEVICE - macro used to describe a specific PCI device
|
||||
* @vend: the 16 bit PCI Vendor ID
|
||||
* @dev: the 16 bit PCI Device ID
|
||||
*
|
||||
|
|
@ -777,7 +768,7 @@ struct pci_driver {
|
|||
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
|
||||
|
||||
/**
|
||||
* PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
|
||||
* PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
|
||||
* @vend: the 16 bit PCI Vendor ID
|
||||
* @dev: the 16 bit PCI Device ID
|
||||
* @subvend: the 16 bit PCI Subvendor ID
|
||||
|
|
@ -791,7 +782,7 @@ struct pci_driver {
|
|||
.subvendor = (subvend), .subdevice = (subdev)
|
||||
|
||||
/**
|
||||
* PCI_DEVICE_CLASS - macro used to describe a specific pci device class
|
||||
* PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
|
||||
* @dev_class: the class, subclass, prog-if triple for this device
|
||||
* @dev_class_mask: the class mask for this device
|
||||
*
|
||||
|
|
@ -805,7 +796,7 @@ struct pci_driver {
|
|||
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
|
||||
|
||||
/**
|
||||
* PCI_VDEVICE - macro used to describe a specific pci device in short form
|
||||
* PCI_VDEVICE - macro used to describe a specific PCI device in short form
|
||||
* @vend: the vendor name
|
||||
* @dev: the 16 bit PCI Device ID
|
||||
*
|
||||
|
|
@ -814,22 +805,21 @@ struct pci_driver {
|
|||
* to PCI_ANY_ID. The macro allows the next field to follow as the device
|
||||
* private data.
|
||||
*/
|
||||
|
||||
#define PCI_VDEVICE(vend, dev) \
|
||||
.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
|
||||
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
|
||||
|
||||
enum {
|
||||
PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
|
||||
PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
|
||||
PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
|
||||
PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
|
||||
PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
|
||||
PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
|
||||
PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
|
||||
PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
|
||||
PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
|
||||
PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
|
||||
PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
|
||||
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
|
||||
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
|
||||
};
|
||||
|
||||
/* these external functions are only available when PCI support is enabled */
|
||||
/* These external functions are only available when PCI support is enabled */
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
extern unsigned int pci_flags;
|
||||
|
|
@ -842,11 +832,11 @@ static inline int pci_has_flag(int flag) { return pci_flags & flag; }
|
|||
void pcie_bus_configure_settings(struct pci_bus *bus);
|
||||
|
||||
enum pcie_bus_config_types {
|
||||
PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
|
||||
PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
|
||||
PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
|
||||
PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
|
||||
PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
|
||||
PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
|
||||
PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
|
||||
PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
|
||||
PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
|
||||
PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
|
||||
};
|
||||
|
||||
extern enum pcie_bus_config_types pcie_bus_config;
|
||||
|
|
@ -855,7 +845,7 @@ extern struct bus_type pci_bus_type;
|
|||
|
||||
/* Do NOT directly access these two variables, unless you are arch-specific PCI
|
||||
* code, or PCI core code. */
|
||||
extern struct list_head pci_root_buses; /* list of all known PCI buses */
|
||||
extern struct list_head pci_root_buses; /* List of all known PCI buses */
|
||||
/* Some device drivers need know if PCI is initiated */
|
||||
int no_pci_devices(void);
|
||||
|
||||
|
|
@ -893,8 +883,8 @@ int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
|
|||
int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
|
||||
void pci_bus_release_busn_res(struct pci_bus *b);
|
||||
struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
|
||||
struct pci_ops *ops, void *sysdata,
|
||||
struct list_head *resources);
|
||||
struct pci_ops *ops, void *sysdata,
|
||||
struct list_head *resources);
|
||||
int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
|
||||
struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
|
||||
int busnr);
|
||||
|
|
@ -951,10 +941,10 @@ int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
|
|||
struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
|
||||
|
||||
struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
|
||||
struct pci_dev *from);
|
||||
struct pci_dev *from);
|
||||
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
|
||||
unsigned int ss_vendor, unsigned int ss_device,
|
||||
struct pci_dev *from);
|
||||
unsigned int ss_vendor, unsigned int ss_device,
|
||||
struct pci_dev *from);
|
||||
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
|
||||
struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
|
||||
unsigned int devfn);
|
||||
|
|
@ -1030,7 +1020,7 @@ static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
|
|||
return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
|
||||
}
|
||||
|
||||
/* user-space driven config access */
|
||||
/* User-space driven config access */
|
||||
int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
|
||||
int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
|
||||
int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
|
||||
|
|
@ -1172,7 +1162,7 @@ unsigned int pci_rescan_bus(struct pci_bus *bus);
|
|||
void pci_lock_rescan_remove(void);
|
||||
void pci_unlock_rescan_remove(void);
|
||||
|
||||
/* Vital product data routines */
|
||||
/* Vital Product Data routines */
|
||||
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
|
||||
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
|
||||
int pci_set_vpd_size(struct pci_dev *dev, size_t len);
|
||||
|
|
@ -1257,9 +1247,7 @@ static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
|
|||
int __must_check __pci_register_driver(struct pci_driver *, struct module *,
|
||||
const char *mod_name);
|
||||
|
||||
/*
|
||||
* pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
|
||||
*/
|
||||
/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
|
||||
#define pci_register_driver(driver) \
|
||||
__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
|
||||
|
||||
|
|
@ -1274,8 +1262,7 @@ void pci_unregister_driver(struct pci_driver *dev);
|
|||
* use this macro once, and calling it replaces module_init() and module_exit()
|
||||
*/
|
||||
#define module_pci_driver(__pci_driver) \
|
||||
module_driver(__pci_driver, pci_register_driver, \
|
||||
pci_unregister_driver)
|
||||
module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
|
||||
|
||||
/**
|
||||
* builtin_pci_driver() - Helper macro for registering a PCI driver
|
||||
|
|
@ -1314,10 +1301,10 @@ resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
|
|||
int pci_set_vga_state(struct pci_dev *pdev, bool decode,
|
||||
unsigned int command_bits, u32 flags);
|
||||
|
||||
#define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
|
||||
#define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
|
||||
#define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
|
||||
#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
|
||||
#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
|
||||
#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
|
||||
#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
|
||||
#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
|
||||
#define PCI_IRQ_ALL_TYPES \
|
||||
(PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
|
||||
|
||||
|
|
@ -1336,8 +1323,8 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
|
|||
#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
|
||||
|
||||
struct msix_entry {
|
||||
u32 vector; /* kernel uses to write allocated vector */
|
||||
u16 entry; /* driver uses to specify entry, OS writes */
|
||||
u32 vector; /* Kernel uses to write allocated vector */
|
||||
u16 entry; /* Driver uses to specify entry, OS writes */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
|
|
@ -1377,10 +1364,10 @@ static inline int pci_msi_enabled(void) { return 0; }
|
|||
static inline int pci_enable_msi(struct pci_dev *dev)
|
||||
{ return -ENOSYS; }
|
||||
static inline int pci_enable_msix_range(struct pci_dev *dev,
|
||||
struct msix_entry *entries, int minvec, int maxvec)
|
||||
struct msix_entry *entries, int minvec, int maxvec)
|
||||
{ return -ENOSYS; }
|
||||
static inline int pci_enable_msix_exact(struct pci_dev *dev,
|
||||
struct msix_entry *entries, int nvec)
|
||||
struct msix_entry *entries, int nvec)
|
||||
{ return -ENOSYS; }
|
||||
|
||||
static inline int
|
||||
|
|
@ -1545,9 +1532,9 @@ static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
|
|||
int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
|
||||
#endif
|
||||
|
||||
/* some architectures require additional setup to direct VGA traffic */
|
||||
/* Some architectures require additional setup to direct VGA traffic */
|
||||
typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
|
||||
unsigned int command_bits, u32 flags);
|
||||
unsigned int command_bits, u32 flags);
|
||||
void pci_register_set_vga_state(arch_set_vga_state_t func);
|
||||
|
||||
static inline int
|
||||
|
|
@ -1586,10 +1573,9 @@ static inline void pci_clear_flags(int flags) { }
|
|||
static inline int pci_has_flag(int flag) { return 0; }
|
||||
|
||||
/*
|
||||
* If the system does not have PCI, clearly these return errors. Define
|
||||
* these as simple inline functions to avoid hair in drivers.
|
||||
* If the system does not have PCI, clearly these return errors. Define
|
||||
* these as simple inline functions to avoid hair in drivers.
|
||||
*/
|
||||
|
||||
#define _PCI_NOP(o, s, t) \
|
||||
static inline int pci_##o##_config_##s(struct pci_dev *dev, \
|
||||
int where, t val) \
|
||||
|
|
@ -1735,8 +1721,10 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
|
|||
#define pci_root_bus_fwnode(bus) NULL
|
||||
#endif
|
||||
|
||||
/* these helpers provide future and backwards compatibility
|
||||
* for accessing popular PCI BAR info */
|
||||
/*
|
||||
* These helpers provide future and backwards compatibility
|
||||
* for accessing popular PCI BAR info
|
||||
*/
|
||||
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
|
||||
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
|
||||
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
|
||||
|
|
@ -1748,7 +1736,8 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
|
|||
(pci_resource_end((dev), (bar)) - \
|
||||
pci_resource_start((dev), (bar)) + 1))
|
||||
|
||||
/* Similar to the helpers above, these manipulate per-pci_dev
|
||||
/*
|
||||
* Similar to the helpers above, these manipulate per-pci_dev
|
||||
* driver-specific data. They are really just a wrapper around
|
||||
* the generic device structure functions of these calls.
|
||||
*/
|
||||
|
|
@ -1762,16 +1751,14 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
|
|||
dev_set_drvdata(&pdev->dev, data);
|
||||
}
|
||||
|
||||
/* If you want to know what to call your pci_dev, ask this function.
|
||||
* Again, it's a wrapper around the generic device.
|
||||
*/
|
||||
static inline const char *pci_name(const struct pci_dev *pdev)
|
||||
{
|
||||
return dev_name(&pdev->dev);
|
||||
}
|
||||
|
||||
|
||||
/* Some archs don't want to expose struct resource to userland as-is
|
||||
/*
|
||||
* Some archs don't want to expose struct resource to userland as-is
|
||||
* in sysfs and /proc
|
||||
*/
|
||||
#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
|
||||
|
|
@ -1790,16 +1777,16 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
|||
|
||||
|
||||
/*
|
||||
* The world is not perfect and supplies us with broken PCI devices.
|
||||
* For at least a part of these bugs we need a work-around, so both
|
||||
* generic (drivers/pci/quirks.c) and per-architecture code can define
|
||||
* fixup hooks to be called for particular buggy devices.
|
||||
* The world is not perfect and supplies us with broken PCI devices.
|
||||
* For at least a part of these bugs we need a work-around, so both
|
||||
* generic (drivers/pci/quirks.c) and per-architecture code can define
|
||||
* fixup hooks to be called for particular buggy devices.
|
||||
*/
|
||||
|
||||
struct pci_fixup {
|
||||
u16 vendor; /* You can use PCI_ANY_ID here of course */
|
||||
u16 device; /* You can use PCI_ANY_ID here of course */
|
||||
u32 class; /* You can use PCI_ANY_ID here too */
|
||||
u16 vendor; /* Or PCI_ANY_ID */
|
||||
u16 device; /* Or PCI_ANY_ID */
|
||||
u32 class; /* Or PCI_ANY_ID */
|
||||
unsigned int class_shift; /* should be 0, 8, 16 */
|
||||
void (*hook)(struct pci_dev *dev);
|
||||
};
|
||||
|
|
@ -1841,23 +1828,19 @@ enum pci_fixup_pass {
|
|||
#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
|
||||
class_shift, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
|
||||
resume##hook, vendor, device, class, \
|
||||
class_shift, hook)
|
||||
resume##hook, vendor, device, class, class_shift, hook)
|
||||
#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
|
||||
class_shift, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
|
||||
resume_early##hook, vendor, device, \
|
||||
class, class_shift, hook)
|
||||
resume_early##hook, vendor, device, class, class_shift, hook)
|
||||
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
|
||||
class_shift, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
|
||||
suspend##hook, vendor, device, class, \
|
||||
class_shift, hook)
|
||||
suspend##hook, vendor, device, class, class_shift, hook)
|
||||
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
|
||||
class_shift, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
|
||||
suspend_late##hook, vendor, device, \
|
||||
class, class_shift, hook)
|
||||
suspend_late##hook, vendor, device, class, class_shift, hook)
|
||||
|
||||
#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
|
||||
|
|
@ -1873,20 +1856,16 @@ enum pci_fixup_pass {
|
|||
hook, vendor, device, PCI_ANY_ID, 0, hook)
|
||||
#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
|
||||
resume##hook, vendor, device, \
|
||||
PCI_ANY_ID, 0, hook)
|
||||
resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
||||
#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
|
||||
resume_early##hook, vendor, device, \
|
||||
PCI_ANY_ID, 0, hook)
|
||||
resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
||||
#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
|
||||
suspend##hook, vendor, device, \
|
||||
PCI_ANY_ID, 0, hook)
|
||||
suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
||||
#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
|
||||
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
|
||||
suspend_late##hook, vendor, device, \
|
||||
PCI_ANY_ID, 0, hook)
|
||||
suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
||||
|
||||
#ifdef CONFIG_PCI_QUIRKS
|
||||
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
|
||||
|
|
@ -2122,7 +2101,7 @@ static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
|
|||
*/
|
||||
static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
|
||||
{
|
||||
return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
|
||||
return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2207,7 +2186,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
|
|||
return bus ? bus->dev.of_node : NULL;
|
||||
}
|
||||
|
||||
#else /* CONFIG_OF */
|
||||
#else /* CONFIG_OF */
|
||||
static inline void pci_set_of_node(struct pci_dev *dev) { }
|
||||
static inline void pci_release_of_node(struct pci_dev *dev) { }
|
||||
static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
|
||||
|
|
@ -2216,7 +2195,7 @@ static inline struct device_node *
|
|||
pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
|
||||
static inline struct irq_domain *
|
||||
pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
|
||||
#endif /* CONFIG_OF */
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
|
||||
|
|
@ -2241,7 +2220,7 @@ int pci_for_each_dma_alias(struct pci_dev *pdev,
|
|||
int (*fn)(struct pci_dev *pdev,
|
||||
u16 alias, void *data), void *data);
|
||||
|
||||
/* helper functions for operation of device flag */
|
||||
/* Helper functions for operation of device flag */
|
||||
static inline void pci_set_dev_assigned(struct pci_dev *pdev)
|
||||
{
|
||||
pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
|
||||
|
|
@ -2288,7 +2267,7 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
|
|||
return false;
|
||||
}
|
||||
|
||||
/* provide the legacy pci_dma_* API */
|
||||
/* Provide the legacy pci_dma_* API */
|
||||
#include <linux/pci-dma-compat.h>
|
||||
|
||||
#define pci_printk(level, pdev, fmt, arg...) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue