ARM: local timers: Add A15 architected timer support
Add support for the A15 generic timer and clocksource. As the timer generates interrupts on a different PPI depending on the execution mode (normal or secure), it is possible to register two different PPIs. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier
parent
bfa05f4f33
commit
022c03a2d6
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@ -1543,6 +1543,12 @@ config HAVE_ARM_SCU
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help
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This option enables support for the ARM system coherency unit
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config ARM_ARCH_TIMER
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bool "Architected timer support"
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depends on CPU_V7
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help
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This option enables support for the ARM architected timer
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config HAVE_ARM_TWD
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bool
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depends on SMP
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@ -0,0 +1,19 @@
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#ifndef __ASMARM_ARCH_TIMER_H
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#define __ASMARM_ARCH_TIMER_H
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#include <linux/ioport.h>
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struct arch_timer {
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struct resource res[2];
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};
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#ifdef CONFIG_ARM_ARCH_TIMER
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int arch_timer_register(struct arch_timer *);
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#else
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static inline int arch_timer_register(struct arch_timer *at)
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{
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return -ENXIO;
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}
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#endif
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#endif
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@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o
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obj-$(CONFIG_SMP) += smp.o smp_tlb.o
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obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
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obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o
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obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o
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@ -0,0 +1,288 @@
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/*
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* linux/arch/arm/kernel/arch_timer.c
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*
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* Copyright (C) 2011 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/jiffies.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <asm/localtimer.h>
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#include <asm/arch_timer.h>
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#include <asm/system_info.h>
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static unsigned long arch_timer_rate;
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static int arch_timer_ppi;
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static int arch_timer_ppi2;
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static struct clock_event_device __percpu **arch_timer_evt;
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/*
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* Architected system timer support.
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*/
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
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#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
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#define ARCH_TIMER_REG_CTRL 0
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#define ARCH_TIMER_REG_FREQ 1
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#define ARCH_TIMER_REG_TVAL 2
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static void arch_timer_reg_write(int reg, u32 val)
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{
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
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break;
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}
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isb();
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}
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static u32 arch_timer_reg_read(int reg)
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{
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u32 val;
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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break;
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case ARCH_TIMER_REG_FREQ:
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
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break;
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default:
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BUG();
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}
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return val;
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}
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static irqreturn_t arch_timer_handler(int irq, void *dev_id)
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{
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struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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ctrl |= ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static void arch_timer_disable(void)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
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}
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static void arch_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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arch_timer_disable();
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break;
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default:
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break;
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}
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}
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static int arch_timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
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return 0;
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}
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static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
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{
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/* Be safe... */
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arch_timer_disable();
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clk->features = CLOCK_EVT_FEAT_ONESHOT;
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clk->name = "arch_sys_timer";
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clk->rating = 450;
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clk->set_mode = arch_timer_set_mode;
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clk->set_next_event = arch_timer_set_next_event;
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clk->irq = arch_timer_ppi;
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clockevents_config_and_register(clk, arch_timer_rate,
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0xf, 0x7fffffff);
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*__this_cpu_ptr(arch_timer_evt) = clk;
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enable_percpu_irq(clk->irq, 0);
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if (arch_timer_ppi2)
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enable_percpu_irq(arch_timer_ppi2, 0);
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return 0;
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}
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/* Is the optional system timer available? */
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static int local_timer_is_architected(void)
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{
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return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
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((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
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}
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static int arch_timer_available(void)
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{
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unsigned long freq;
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if (!local_timer_is_architected())
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return -ENXIO;
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if (arch_timer_rate == 0) {
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arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
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freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
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/* Check the timer frequency. */
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if (freq == 0) {
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pr_warn("Architected timer frequency not available\n");
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return -EINVAL;
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}
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arch_timer_rate = freq;
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}
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pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
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arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
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return 0;
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}
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static inline cycle_t arch_counter_get_cntpct(void)
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{
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u32 cvall, cvalh;
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asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
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return ((cycle_t) cvalh << 32) | cvall;
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}
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static inline cycle_t arch_counter_get_cntvct(void)
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{
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u32 cvall, cvalh;
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asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
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return ((cycle_t) cvalh << 32) | cvall;
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}
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static cycle_t arch_counter_read(struct clocksource *cs)
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{
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return arch_counter_get_cntpct();
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}
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static struct clocksource clocksource_counter = {
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.name = "arch_sys_counter",
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.rating = 400,
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.read = arch_counter_read,
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.mask = CLOCKSOURCE_MASK(56),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
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{
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pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
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clk->irq, smp_processor_id());
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disable_percpu_irq(clk->irq);
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if (arch_timer_ppi2)
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disable_percpu_irq(arch_timer_ppi2);
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arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
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}
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static struct local_timer_ops arch_timer_ops __cpuinitdata = {
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.setup = arch_timer_setup,
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.stop = arch_timer_stop,
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};
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int __init arch_timer_register(struct arch_timer *at)
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{
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int err;
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if (at->res[0].start <= 0 || !(at->res[0].flags & IORESOURCE_IRQ))
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return -EINVAL;
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err = arch_timer_available();
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if (err)
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return err;
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arch_timer_evt = alloc_percpu(struct clock_event_device *);
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if (!arch_timer_evt)
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return -ENOMEM;
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clocksource_register_hz(&clocksource_counter, arch_timer_rate);
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arch_timer_ppi = at->res[0].start;
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err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
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"arch_timer", arch_timer_evt);
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if (err) {
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pr_err("arch_timer: can't register interrupt %d (%d)\n",
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arch_timer_ppi, err);
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goto out_free;
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}
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if (at->res[1].start > 0 || (at->res[1].flags & IORESOURCE_IRQ)) {
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arch_timer_ppi2 = at->res[1].start;
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err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
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"arch_timer", arch_timer_evt);
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if (err) {
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pr_err("arch_timer: can't register interrupt %d (%d)\n",
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arch_timer_ppi2, err);
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arch_timer_ppi2 = 0;
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goto out_free_irq;
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}
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}
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err = local_timer_register(&arch_timer_ops);
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if (err)
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goto out_free_irq;
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return 0;
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out_free_irq:
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free_percpu_irq(arch_timer_ppi, arch_timer_evt);
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if (arch_timer_ppi2)
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free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
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out_free:
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free_percpu(arch_timer_evt);
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return err;
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}
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