pinctrl: exynos: add exynos5410 SoC specific data
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5410. Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> [AF: Rebased onto Exynos5260, irq_chip consolidation, const'ification] Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Pavel Fedin <p.fedin@samsung.com> [k.kozlowski: Rebased on current v4.3] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
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@ -17,6 +17,7 @@ Required Properties:
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- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
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- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
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- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
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- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
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- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
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- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
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@ -1150,6 +1150,109 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
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},
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};
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/* pin banks of exynos5410 pin-controller 0 */
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static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
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EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
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EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
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EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
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EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
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EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
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EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
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EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
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EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
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EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
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EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
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EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
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EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
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EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
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EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
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EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
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EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
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EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
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EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
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EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
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EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
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EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
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EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
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EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
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EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
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EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
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EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
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EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
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EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
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};
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/* pin banks of exynos5410 pin-controller 1 */
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static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
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EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
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EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
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EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
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EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
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EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
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EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
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EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
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};
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/* pin banks of exynos5410 pin-controller 2 */
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static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
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EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
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EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
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EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
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};
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/* pin banks of exynos5410 pin-controller 3 */
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static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
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};
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/*
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* Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
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* four gpio/pin-mux/pinconfig controllers.
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*/
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const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 data */
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.pin_banks = exynos5410_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 1 data */
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.pin_banks = exynos5410_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 2 data */
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.pin_banks = exynos5410_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 3 data */
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.pin_banks = exynos5410_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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},
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};
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/* pin banks of exynos5420 pin-controller 0 */
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static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
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@ -1222,6 +1222,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = (void *)exynos5250_pin_ctrl },
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{ .compatible = "samsung,exynos5260-pinctrl",
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.data = (void *)exynos5260_pin_ctrl },
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{ .compatible = "samsung,exynos5410-pinctrl",
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.data = (void *)exynos5410_pin_ctrl },
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{ .compatible = "samsung,exynos5420-pinctrl",
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.data = (void *)exynos5420_pin_ctrl },
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{ .compatible = "samsung,exynos5433-pinctrl",
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@ -270,6 +270,7 @@ extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[];
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extern const struct samsung_pin_ctrl exynos7_pin_ctrl[];
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