mvebu cleanup for v3.10
- plat-orion: prep for mvebu-mbus driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQEcBAABAgAGBQJRRgjnAAoJEAi3KVZQDZAeJWsH/03OAVvN/yBHrWHoi++RWJyx sX9BL2i+dqFXpjN82OtPh3z2D1CRZSiJhGsbSZznY6Le1JhzeKXon2BErU0B9hO4 ZYWKzlDIbQ8Rls41mrDlAFhqmbw9w7lXux70yaYFyXY42JfNMDQ7yKDvcmlyOOdY X0fDSaUkSuMRQpEqOCSvp1bZ8BTcgJr3dICUYgxWvQlV/CUfUXI+FXwybZxadwGk XwXe03f4ZcKp/jl/+Ttd4wKtwowKuD/yM7Z/VYirmHSgnfGXD41EZrIZJspUVUX8 rfWnUoCJ1As+jjE3GKD17ZpD98NSdlf7PDju5RKK+6TSfjXl4Nl/AHwTsmoz3fA= =2Udw -----END PGP SIGNATURE----- Merge tag 'tags/cleanup_for_v3.10' into mvebu/soc mvebu cleanup for v3.10 - plat-orion: prep for mvebu-mbus driver
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02ac5b3fc5
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@ -402,8 +402,9 @@ static void __init orion5x_pci_master_slave_enable(void)
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orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
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}
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static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
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static void __init orion5x_setup_pci_wins(void)
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{
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const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
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u32 win_enable;
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int bus;
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int i;
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@ -420,7 +421,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
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bus = orion5x_pci_local_bus_nr();
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for (i = 0; i < dram->num_cs; i++) {
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struct mbus_dram_window *cs = dram->cs + i;
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const struct mbus_dram_window *cs = dram->cs + i;
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u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
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u32 reg;
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u32 val;
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@ -467,7 +468,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
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/*
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* Point PCI unit MBUS decode windows to DRAM space.
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*/
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orion5x_setup_pci_wins(&orion_mbus_dram_info);
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orion5x_setup_pci_wins();
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/*
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* Master + Slave enable
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@ -3,7 +3,11 @@
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#
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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obj-y += addr-map.o
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obj-$(CONFIG_ARCH_MVEBU) += addr-map.o
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obj-$(CONFIG_ARCH_KIRKWOOD) += addr-map.o
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obj-$(CONFIG_ARCH_DOVE) += addr-map.o
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obj-$(CONFIG_ARCH_ORION5X) += addr-map.o
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obj-$(CONFIG_ARCH_MV78XX0) += addr-map.o
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orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
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obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
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@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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static void __init orion_pcie_setup_wins(void __iomem *base,
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struct mbus_dram_target_info *dram)
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static void __init orion_pcie_setup_wins(void __iomem *base)
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{
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const struct mbus_dram_target_info *dram;
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u32 size;
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int i;
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dram = mv_mbus_dram_info();
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/*
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* First, disable and clear BARs and windows.
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*/
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@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
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*/
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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struct mbus_dram_window *cs = dram->cs + i;
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
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writel(0, base + PCIE_WIN04_REMAP_OFF(i));
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@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
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/*
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* Point PCIe unit MBUS decode windows to DRAM space.
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*/
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orion_pcie_setup_wins(base, &orion_mbus_dram_info);
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orion_pcie_setup_wins(base);
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/*
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* Master + slave enable.
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