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Merge branch 'v3.17-next/cleanup-samsung' into v3.17-next/power-exynos

This commit is contained in:
Kukjin Kim 2014-07-23 08:18:08 +09:00
parent 9a3c4145af fce9e5bb25
commit 036c37c580
13 changed files with 77 additions and 50 deletions
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20
arch/arm/Kconfig.debug
View File

@ -617,53 +617,41 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 0 for low-level debug"
bool "Use Samsung S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 1 for low-level debug"
bool "Use Samsung S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 1. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 2 for low-level debug"
bool "Use Samsung S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 2. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C_UART3
depends on PLAT_SAMSUNG && ARCH_EXYNOS
select DEBUG_EXYNOS_UART
bool "Use S3C UART 3 for low-level debug"
bool "Use Samsung S3C UART 3 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 3. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C2410_UART0
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART

13
arch/arm/mach-exynos/common.h
View File

@ -111,25 +111,14 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
soc_is_exynos5420() || soc_is_exynos5800())
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
struct map_desc;
extern void __iomem *sysram_ns_base_addr;
extern void __iomem *sysram_base_addr;
void exynos_init_io(void);
void exynos_restart(enum reboot_mode mode, const char *cmd);
extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
void exynos_cpuidle_init(void);
void exynos_cpufreq_init(void);
void exynos_init_late(void);
void exynos_firmware_init(void);
#ifdef CONFIG_PINCTRL_EXYNOS
extern u32 exynos_get_eint_wake_mask(void);
#else
static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
#endif
#ifdef CONFIG_PM_SLEEP
extern void __init exynos_pm_init(void);

44
arch/arm/mach-exynos/exynos.c
View File

@ -19,6 +19,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/irqchip.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
@ -29,6 +30,9 @@
#include "common.h"
#include "mfc.h"
#include "regs-pmu.h"
#include "regs-sys.h"
void __iomem *pmu_base_addr;
static struct map_desc exynos4_iodesc[] __initdata = {
{
@ -143,7 +147,7 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
void exynos_restart(enum reboot_mode mode, const char *cmd)
static void exynos_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
u32 val = 0x1;
@ -204,7 +208,7 @@ void __init exynos_sysram_init(void)
}
}
void __init exynos_init_late(void)
static void __init exynos_init_late(void)
{
if (of_machine_is_compatible("samsung,exynos5440"))
/* to be supported later */
@ -251,7 +255,7 @@ static void __init exynos_map_io(void)
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
}
void __init exynos_init_io(void)
static void __init exynos_init_io(void)
{
debug_ll_io_init();
@ -263,6 +267,39 @@ void __init exynos_init_io(void)
exynos_map_io();
}
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = "samsung,exynos3250-pmu" },
{ .compatible = "samsung,exynos4210-pmu" },
{ .compatible = "samsung,exynos4212-pmu" },
{ .compatible = "samsung,exynos4412-pmu" },
{ .compatible = "samsung,exynos5250-pmu" },
{ .compatible = "samsung,exynos5420-pmu" },
{ /*sentinel*/ },
};
static void exynos_map_pmu(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
if (!pmu_base_addr)
panic("failed to find exynos pmu register\n");
}
static void __init exynos_init_irq(void)
{
irqchip_init();
/*
* Since platsmp.c needs pmu base address by the time
* DT is not unflatten so we can't use DT APIs before
* init_irq
*/
exynos_map_pmu();
}
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@ -343,6 +380,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_irq = exynos_init_irq,
.init_machine = exynos_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos_dt_compat,

1
arch/arm/mach-exynos/headsmp.S
View File

@ -1,5 +1,4 @@
/*
* linux/arch/arm/mach-exynos4/headsmp.S
*
* Cloned from linux/arch/arm/mach-realview/headsmp.S
*

3
arch/arm/mach-exynos/hotplug.c
View File

@ -1,5 +1,4 @@
/* linux arch/arm/mach-exynos4/hotplug.c
*
/*
* Cloned from linux/arch/arm/mach-realview/hotplug.c
*
* Copyright (C) 2002 ARM Ltd.

3
arch/arm/mach-exynos/include/mach/map.h
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-exynos/include/mach/map.h
*
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*

3
arch/arm/mach-exynos/include/mach/memory.h
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-exynos4/include/mach/memory.h
*
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

3
arch/arm/mach-exynos/platsmp.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-exynos4/platsmp.c
*
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

1
arch/arm/mach-exynos/pm.c
View File

@ -35,6 +35,7 @@
#include "common.h"
#include "regs-pmu.h"
#include "regs-sys.h"
/**
* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping

9
arch/arm/mach-exynos/pm_domains.c
View File

@ -23,8 +23,7 @@
#include <linux/of_platform.h>
#include <linux/sched.h>
#include "regs-pmu.h"
#define INT_LOCAL_PWR_EN 0x7
#define MAX_CLK_PER_DOMAIN 4
/*
@ -63,13 +62,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
}
}
pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
pwr = power_on ? INT_LOCAL_PWR_EN : 0;
__raw_writel(pwr, base);
/* Wait max 1ms */
timeout = 10;
while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
if (!timeout) {
op = (power_on) ? "enable" : "disable";
pr_err("Power domain %s %s failed\n", domain->name, op);
@ -231,7 +230,7 @@ static __init int exynos4_pm_init_power_domain(void)
no_clk:
platform_set_drvdata(pdev, pd);
on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
pm_genpd_init(&pd->pd, NULL, !on);
}

1
arch/arm/mach-exynos/pmu.c
View File

@ -11,7 +11,6 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include "common.h"
#include "regs-pmu.h"

4
arch/arm/mach-exynos/regs-pmu.h
View File

@ -15,7 +15,6 @@
#include <mach/map.h>
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
@ -127,7 +126,6 @@
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_INT_LOCAL_PWR_EN 0x7
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
@ -188,8 +186,6 @@
/* For EXYNOS5 */
#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)

22
arch/arm/mach-exynos/regs-sys.h Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - system register definition
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_SYS_H
#define __ASM_ARCH_REGS_SYS_H __FILE__
#include <mach/map.h>
#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
/* For EXYNOS5 */
#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
#endif /* __ASM_ARCH_REGS_SYS_H */