drivers/perf: hisi: update the sccl_id/ccl_id when MT is supported
MT bit in MPIDR_EL1 is now supported in certain HiSilicon platforms, so the mapping between sccl_id/ccl_id and affinity level needs to be updated from the generic encoding we originally used. Cc: John Garry <john.garry@huawei.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> [will: fixed comment] Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -350,19 +350,21 @@ void hisi_uncore_pmu_disable(struct pmu *pmu)
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/*
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/*
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* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
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* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
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* If multi-threading is supported, SCCL_ID is in MPIDR[aff3] and CCL_ID
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* If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
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* is in MPIDR[aff2]; if not, SCCL_ID is in MPIDR[aff2] and CCL_ID is
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* and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
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* in MPIDR[aff1]. If this changes in future, this shall be updated.
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* is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
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*/
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*/
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static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
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static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
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{
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{
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u64 mpidr = read_cpuid_mpidr();
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u64 mpidr = read_cpuid_mpidr();
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if (mpidr & MPIDR_MT_BITMASK) {
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if (mpidr & MPIDR_MT_BITMASK) {
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int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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if (sccl_id)
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if (sccl_id)
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*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
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*sccl_id = aff2 >> 3;
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if (ccl_id)
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if (ccl_id)
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*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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*ccl_id = aff2 & 0x7;
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} else {
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} else {
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if (sccl_id)
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if (sccl_id)
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*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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