dt-bindings: clock: meson: add resets to the audio clock controller
Add the documentation and bindings for the resets provided by the g12a audio clock controller Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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@ -22,6 +22,7 @@ Required Properties:
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components.
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components.
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- resets : phandle of the internal reset line
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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- #clock-cells : should be 1.
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- #reset-cells : should be 1 on the g12a (and following) soc family
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Each clock is assigned an identifier and client nodes can use this identifier
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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to specify the clock which they consume. All available clocks are defined as
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@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
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#define AUD_RESET_PDM 0
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#define AUD_RESET_TDMIN_A 1
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#define AUD_RESET_TDMIN_B 2
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#define AUD_RESET_TDMIN_C 3
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#define AUD_RESET_TDMIN_LB 4
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#define AUD_RESET_LOOPBACK 5
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#define AUD_RESET_TODDR_A 6
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#define AUD_RESET_TODDR_B 7
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#define AUD_RESET_TODDR_C 8
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#define AUD_RESET_FRDDR_A 9
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#define AUD_RESET_FRDDR_B 10
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#define AUD_RESET_FRDDR_C 11
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#define AUD_RESET_TDMOUT_A 12
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#define AUD_RESET_TDMOUT_B 13
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#define AUD_RESET_TDMOUT_C 14
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#define AUD_RESET_SPDIFOUT 15
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#define AUD_RESET_SPDIFOUT_B 16
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#define AUD_RESET_SPDIFIN 17
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#define AUD_RESET_EQDRC 18
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#define AUD_RESET_RESAMPLE 19
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#define AUD_RESET_DDRARB 20
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#define AUD_RESET_POWDET 21
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#define AUD_RESET_TORAM 22
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#define AUD_RESET_TOACODEC 23
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#define AUD_RESET_TOHDMITX 24
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#define AUD_RESET_CLKTREE 25
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#endif
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