[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.
The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra opposes it being called that) where invalid instructions in the same I-cache line worth of instructions being fetched may case spurious exceptions. The workaround for this was only enabled for E9000 cores; enable it also for all RM7000-based platforms. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -177,18 +177,22 @@
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#endif
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#endif
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/*
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/*
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* The RM9000 has a bug (though PMC-Sierra opposes it being called that)
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* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
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* where invalid instructions in the same I-cache line worth of instructions
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* opposes it being called that) where invalid instructions in the same
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* being fetched may case spurious exceptions.
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* I-cache line worth of instructions being fetched may case spurious
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* exceptions.
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*/
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*/
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#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
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#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \
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defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
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defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \
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defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \
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defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \
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defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#endif
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#endif
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/*
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/*
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* ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
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* On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
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* may cause ll / sc and lld / scd sequences to execute non-atomically.
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* may cause ll / sc and lld / scd sequences to execute non-atomically.
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*/
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*/
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#ifdef CONFIG_SGI_IP27
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#ifdef CONFIG_SGI_IP27
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