Microblaze patches for 4.17-rc1
- Use generic pci_mmap_resoruce_range() -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlrMWo4ACgkQykllyylKDCGrrQCfZHss5ank6e1H+EApm0KqEQFu kbwAoIj6TdCVMH44kJwqtraIhBXV9dhX =vYT3 -----END PGP SIGNATURE----- Merge tag 'microblaze-4.17-rc1' of git://git.monstr.eu/linux-2.6-microblaze Pull microblaze updates from Michal Simek: "Use generic pci_mmap_resource_range()" * tag 'microblaze-4.17-rc1' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Use generic pci_mmap_resource_range() microblaze: Provide pgprot_device/writecombine macros for nommu
This commit is contained in:
Linus Torvalds
commit
07820c3bf1
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@ -47,9 +47,10 @@ extern int pci_proc_domain(struct pci_bus *bus);
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struct vm_area_struct;
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/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
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#define HAVE_PCI_MMAP 1
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#define arch_can_pci_mmap_io() 1
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/* Tell PCI code what kind of PCI resource mappings we support */
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#define HAVE_PCI_MMAP 1
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#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
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#define arch_can_pci_mmap_io() 1
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extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
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size_t count);
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@ -33,6 +33,8 @@ extern int mem_init_done;
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#define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */
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#define pgprot_noncached(x) (x)
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#define pgprot_writecombine pgprot_noncached
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#define pgprot_device pgprot_noncached
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#define __swp_type(x) (0)
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#define __swp_offset(x) (0)
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@ -151,72 +151,22 @@ void pcibios_set_master(struct pci_dev *dev)
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}
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/*
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* Platform support for /proc/bus/pci/X/Y mmap()s,
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* modelled on the sparc64 implementation by Dave Miller.
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* -- paulus.
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* Platform support for /proc/bus/pci/X/Y mmap()s.
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*/
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/*
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* Adjust vm_pgoff of VMA such that it is the physical page offset
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* corresponding to the 32-bit pci bus offset for DEV requested by the user.
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*
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* Basically, the user finds the base address for his device which he wishes
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* to mmap. They read the 32-bit value from the config space base register,
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* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
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* offset parameter of mmap on /proc/bus/pci/XXX for that device.
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*
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* Returns negative error code on failure, zero on success.
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*/
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static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
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resource_size_t *offset,
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enum pci_mmap_state mmap_state)
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int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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unsigned long io_offset = 0;
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int i, res_bit;
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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resource_size_t ioaddr = pci_resource_start(pdev, bar);
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if (!hose)
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return NULL; /* should never happen */
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return -EINVAL; /* should never happen */
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/* If memory, add on the PCI bridge address offset */
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if (mmap_state == pci_mmap_mem) {
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#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
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*offset += hose->pci_mem_offset;
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#endif
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res_bit = IORESOURCE_MEM;
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} else {
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io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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*offset += io_offset;
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res_bit = IORESOURCE_IO;
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}
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/* Convert to an offset within this PCI controller */
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ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
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/*
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* Check that the offset requested corresponds to one of the
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* resources of the device.
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*/
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *rp = &dev->resource[i];
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int flags = rp->flags;
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/* treat ROM as memory (should be already) */
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if (i == PCI_ROM_RESOURCE)
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flags |= IORESOURCE_MEM;
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/* Active and same type? */
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if ((flags & res_bit) == 0)
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continue;
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/* In the range of this resource? */
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if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
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continue;
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/* found it! construct the final physical address */
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if (mmap_state == pci_mmap_io)
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*offset += hose->io_base_phys - io_offset;
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return rp;
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}
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return NULL;
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vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
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return 0;
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}
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/*
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@ -268,37 +218,6 @@ pgprot_t pci_phys_mem_access_prot(struct file *file,
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return prot;
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}
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/*
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* Perform the actual remap of the pages for a PCI device mapping, as
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* appropriate for this architecture. The region in the process to map
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* is described by vm_start and vm_end members of VMA, the base physical
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* address is found in vm_pgoff.
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* The pci device structure is provided so that architectures may make mapping
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* decisions on a per-device or per-bus basis.
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*
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* Returns a negative error code on failure, zero on success.
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*/
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int pci_mmap_page_range(struct pci_dev *dev, int bar, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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resource_size_t offset =
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((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
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struct resource *rp;
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int ret;
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rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
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if (rp == NULL)
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return -EINVAL;
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vma->vm_pgoff = offset >> PAGE_SHIFT;
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start, vma->vm_page_prot);
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return ret;
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}
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/* This provides legacy IO read access on a bus */
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int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
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{
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