Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/st-ssc4' and 'spi/topic/stm32' into spi-next
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082f6968bb
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@ -0,0 +1,59 @@
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STMicroelectronics STM32 SPI Controller
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The STM32 SPI controller is used to communicate with external devices using
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the Serial Peripheral Interface. It supports full-duplex, half-duplex and
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simplex synchronous serial communication with external devices. It supports
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from 4 to 32-bit data size. Although it can be configured as master or slave,
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only master is supported by the driver.
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Required properties:
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- compatible: Must be "st,stm32h7-spi".
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- reg: Offset and length of the device's register set.
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- interrupts: Must contain the interrupt id.
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- clocks: Must contain an entry for spiclk (which feeds the internal clock
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generator).
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- #address-cells: Number of cells required to define a chip select address.
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- #size-cells: Should be zero.
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Optional properties:
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- resets: Must contain the phandle to the reset controller.
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- A pinctrl state named "default" may be defined to set pins in mode of
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operation for SPI transfer.
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- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the
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STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt.
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- dma-names: DMA request names should include "tx" and "rx" if present.
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- cs-gpios: list of GPIO chip selects. See the SPI bus bindings,
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Child nodes represent devices on the SPI bus
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See ../spi/spi-bus.txt
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Optional properties:
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- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in
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nanoseconds inserted between two consecutive data frames.
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Example:
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spi2: spi@40003800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40003800 0x400>;
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interrupts = <36>;
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clocks = <&rcc SPI2_CK>;
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resets = <&rcc 1166>;
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dmas = <&dmamux1 0 39 0x400 0x01>,
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<&dmamux1 1 40 0x400 0x01>;
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dma-names = "rx", "tx";
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pinctrl-0 = <&spi2_pins_b>;
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pinctrl-names = "default";
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cs-gpios = <&gpioa 11 0>;
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aardvark@0 {
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compatible = "totalphase,aardvark";
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reg = <0>;
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spi-max-frequency = <4000000>;
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st,spi-midi-ns = <4000>;
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};
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};
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@ -627,6 +627,16 @@ config SPI_SIRF
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help
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help
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SPI driver for CSR SiRFprimaII SoCs
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SPI driver for CSR SiRFprimaII SoCs
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config SPI_STM32
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tristate "STMicroelectronics STM32 SPI controller"
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depends on ARCH_STM32 || COMPILE_TEST
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help
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SPI driver for STMicroelectonics STM32 SoCs.
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STM32 SPI controller supports DMA and PIO modes. When DMA
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is not available, the driver automatically falls back to
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PIO mode.
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config SPI_ST_SSC4
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config SPI_ST_SSC4
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tristate "STMicroelectronics SPI SSC-based driver"
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tristate "STMicroelectronics SPI SSC-based driver"
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depends on ARCH_STI || COMPILE_TEST
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depends on ARCH_STI || COMPILE_TEST
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@ -90,6 +90,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_STM32) += spi-stm32.o
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obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
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obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
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obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
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obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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@ -229,42 +229,42 @@ static int spi_st_setup(struct spi_device *spi)
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"setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
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"setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
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hz, spi_st->baud, sscbrg);
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hz, spi_st->baud, sscbrg);
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/* Set SSC_CTL and enable SSC */
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/* Set SSC_CTL and enable SSC */
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var = readl_relaxed(spi_st->base + SSC_CTL);
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var = readl_relaxed(spi_st->base + SSC_CTL);
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var |= SSC_CTL_MS;
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var |= SSC_CTL_MS;
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if (spi->mode & SPI_CPOL)
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if (spi->mode & SPI_CPOL)
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var |= SSC_CTL_PO;
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var |= SSC_CTL_PO;
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else
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else
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var &= ~SSC_CTL_PO;
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var &= ~SSC_CTL_PO;
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if (spi->mode & SPI_CPHA)
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if (spi->mode & SPI_CPHA)
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var |= SSC_CTL_PH;
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var |= SSC_CTL_PH;
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else
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else
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var &= ~SSC_CTL_PH;
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var &= ~SSC_CTL_PH;
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if ((spi->mode & SPI_LSB_FIRST) == 0)
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if ((spi->mode & SPI_LSB_FIRST) == 0)
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var |= SSC_CTL_HB;
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var |= SSC_CTL_HB;
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else
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else
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var &= ~SSC_CTL_HB;
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var &= ~SSC_CTL_HB;
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if (spi->mode & SPI_LOOP)
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if (spi->mode & SPI_LOOP)
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var |= SSC_CTL_LPB;
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var |= SSC_CTL_LPB;
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else
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else
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var &= ~SSC_CTL_LPB;
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var &= ~SSC_CTL_LPB;
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var &= ~SSC_CTL_DATA_WIDTH_MSK;
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var &= ~SSC_CTL_DATA_WIDTH_MSK;
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var |= (spi->bits_per_word - 1);
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var |= (spi->bits_per_word - 1);
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var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
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var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
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var |= SSC_CTL_EN;
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var |= SSC_CTL_EN;
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writel_relaxed(var, spi_st->base + SSC_CTL);
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writel_relaxed(var, spi_st->base + SSC_CTL);
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/* Clear the status register */
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/* Clear the status register */
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readl_relaxed(spi_st->base + SSC_RBUF);
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readl_relaxed(spi_st->base + SSC_RBUF);
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return 0;
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return 0;
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out_free_gpio:
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out_free_gpio:
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gpio_free(cs);
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gpio_free(cs);
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File diff suppressed because it is too large
Load Diff
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@ -99,7 +99,6 @@ MODULE_PARM_DESC(bufsiz, "data bytes in biggest supported SPI message");
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static ssize_t
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static ssize_t
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spidev_sync(struct spidev_data *spidev, struct spi_message *message)
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spidev_sync(struct spidev_data *spidev, struct spi_message *message)
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{
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{
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DECLARE_COMPLETION_ONSTACK(done);
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int status;
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int status;
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struct spi_device *spi;
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struct spi_device *spi;
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@ -325,7 +324,6 @@ static struct spi_ioc_transfer *
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spidev_get_ioc_message(unsigned int cmd, struct spi_ioc_transfer __user *u_ioc,
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spidev_get_ioc_message(unsigned int cmd, struct spi_ioc_transfer __user *u_ioc,
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unsigned *n_ioc)
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unsigned *n_ioc)
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{
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{
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struct spi_ioc_transfer *ioc;
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u32 tmp;
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u32 tmp;
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/* Check type, command number and direction */
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/* Check type, command number and direction */
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return NULL;
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return NULL;
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/* copy into scratch area */
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/* copy into scratch area */
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ioc = kmalloc(tmp, GFP_KERNEL);
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return memdup_user(u_ioc, tmp);
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if (!ioc)
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return ERR_PTR(-ENOMEM);
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if (__copy_from_user(ioc, u_ioc, tmp)) {
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kfree(ioc);
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return ERR_PTR(-EFAULT);
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}
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return ioc;
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}
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}
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static long
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static long
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