[IA64] improve flush_icache_range()
Check with PAL to see what the i-cache line size is for each level of the cache, and so use the correct stride when flushing the cache. Acked-by: David Mosberger Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
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60a762b6a6
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08357f82d4
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@ -20,6 +20,7 @@
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* 02/01/00 R.Seth fixed get_cpuinfo for SMP
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* 02/01/00 R.Seth fixed get_cpuinfo for SMP
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* 01/07/99 S.Eranian added the support for command line argument
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* 01/07/99 S.Eranian added the support for command line argument
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* 06/24/99 W.Drummond added boot_cpu_data.
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* 06/24/99 W.Drummond added boot_cpu_data.
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* 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
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*/
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*/
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#include <linux/config.h>
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/module.h>
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@ -82,6 +83,13 @@ struct io_space io_space[MAX_IO_SPACES];
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EXPORT_SYMBOL(io_space);
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EXPORT_SYMBOL(io_space);
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unsigned int num_io_spaces;
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unsigned int num_io_spaces;
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/*
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* "flush_icache_range()" needs to know what processor dependent stride size to use
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* when it makes i-cache(s) coherent with d-caches.
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*/
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#define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
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unsigned long ia64_i_cache_stride_shift = ~0;
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/*
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/*
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* The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
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* The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
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* mask specifies a mask of address bits that must be 0 in order for two buffers to be
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* mask specifies a mask of address bits that must be 0 in order for two buffers to be
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@ -626,6 +634,12 @@ setup_per_cpu_areas (void)
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/* start_kernel() requires this... */
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/* start_kernel() requires this... */
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}
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}
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/*
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* Calculate the max. cache line size.
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*
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* In addition, the minimum of the i-cache stride sizes is calculated for
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* "flush_icache_range()".
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*/
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static void
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static void
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get_max_cacheline_size (void)
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get_max_cacheline_size (void)
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{
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{
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@ -639,6 +653,8 @@ get_max_cacheline_size (void)
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printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
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printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
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__FUNCTION__, status);
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__FUNCTION__, status);
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max = SMP_CACHE_BYTES;
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max = SMP_CACHE_BYTES;
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/* Safest setup for "flush_icache_range()" */
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ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
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goto out;
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goto out;
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}
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}
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@ -647,14 +663,31 @@ get_max_cacheline_size (void)
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&cci);
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&cci);
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if (status != 0) {
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if (status != 0) {
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printk(KERN_ERR
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printk(KERN_ERR
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"%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
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"%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
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__FUNCTION__, l, status);
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__FUNCTION__, l, status);
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max = SMP_CACHE_BYTES;
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max = SMP_CACHE_BYTES;
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/* The safest setup for "flush_icache_range()" */
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cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
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cci.pcci_unified = 1;
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}
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}
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line_size = 1 << cci.pcci_line_size;
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line_size = 1 << cci.pcci_line_size;
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if (line_size > max)
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if (line_size > max)
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max = line_size;
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max = line_size;
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}
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if (!cci.pcci_unified) {
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status = ia64_pal_cache_config_info(l,
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/* cache_type (instruction)= */ 1,
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&cci);
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if (status != 0) {
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printk(KERN_ERR
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"%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
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__FUNCTION__, l, status);
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/* The safest setup for "flush_icache_range()" */
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cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
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}
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}
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if (cci.pcci_stride < ia64_i_cache_stride_shift)
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ia64_i_cache_stride_shift = cci.pcci_stride;
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}
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out:
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out:
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if (max > ia64_max_cacheline_size)
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if (max > ia64_max_cacheline_size)
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ia64_max_cacheline_size = max;
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ia64_max_cacheline_size = max;
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@ -3,37 +3,59 @@
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*
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*
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* Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
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* Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* 05/28/05 Zoltan Menyhart Dynamic stride size
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*/
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*/
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#include <asm/asmmacro.h>
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#include <asm/asmmacro.h>
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#include <asm/page.h>
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/*
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/*
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* flush_icache_range(start,end)
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* flush_icache_range(start,end)
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* Must flush range from start to end-1 but nothing else (need to
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*
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* Make i-cache(s) coherent with d-caches.
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*
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* Must deal with range from start to end-1 but nothing else (need to
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* be careful not to touch addresses that may be unmapped).
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* be careful not to touch addresses that may be unmapped).
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*
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* Note: "in0" and "in1" are preserved for debugging purposes.
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*/
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*/
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GLOBAL_ENTRY(flush_icache_range)
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GLOBAL_ENTRY(flush_icache_range)
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.prologue
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.prologue
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alloc r2=ar.pfs,2,0,0,0
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alloc r2=ar.pfs,2,0,0,0
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sub r8=in1,in0,1
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movl r3=ia64_i_cache_stride_shift
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mov r21=1
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;;
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;;
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shr.u r8=r8,5 // we flush 32 bytes per iteration
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ld8 r20=[r3] // r20: stride shift
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.save ar.lc, r3
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sub r22=in1,r0,1 // last byte address
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mov r3=ar.lc // save ar.lc
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;;
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shr.u r23=in0,r20 // start / (stride size)
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shr.u r22=r22,r20 // (last byte address) / (stride size)
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shl r21=r21,r20 // r21: stride size of the i-cache(s)
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;;
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sub r8=r22,r23 // number of strides - 1
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shl r24=r23,r20 // r24: addresses for "fc.i" =
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// "start" rounded down to stride boundary
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.save ar.lc,r3
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mov r3=ar.lc // save ar.lc
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;;
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;;
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.body
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.body
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mov ar.lc=r8
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mov ar.lc=r8
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;;
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;;
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.Loop: fc.i in0 // issuable on M2 only
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/*
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add in0=32,in0
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* 32 byte aligned loop, even number of (actually 2) bundles
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*/
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.Loop: fc.i r24 // issuable on M0 only
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add r24=r21,r24 // we flush "stride size" bytes per iteration
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nop.i 0
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br.cloop.sptk.few .Loop
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br.cloop.sptk.few .Loop
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;;
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;;
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sync.i
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sync.i
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;;
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;;
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srlz.i
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srlz.i
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;;
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;;
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mov ar.lc=r3 // restore ar.lc
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mov ar.lc=r3 // restore ar.lc
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br.ret.sptk.many rp
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br.ret.sptk.many rp
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END(flush_icache_range)
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END(flush_icache_range)
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