ARM: SoC fixes
The latest and greatest fixes for ARM platform code. Worth pointing out are: - Lines-wise, largest is a PXA fix for dealing with interrupts on DT that was quite broken. It's still newish code so while we could have held this off, it seemed appropriate to include now - Some GPIO fixes for OMAP platforms added a few lines. This was also fixes for code recently added (this release). - Small OMAP timer fix to behave better with partially upstreamed platforms, which is quite welcome. - Allwinner fixes about operating point control, reducing overclocking in some cases for better stability. + a handful of other smaller fixes across the map. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVGGpHAAoJEIwa5zzehBx3vi8QAKRlHuJzKlEAGOglrmaYLNwr /eSx6wQQlMa+DFr6YVgypYvImCpvbOVPRGMFpaAyriKDrWcu1HiEF4nvq+3Iq1Qt yqPRbTh2xU1qZ9kmidcY5rhSX7IO7Bgeo0fV4q1Dyt5rgUKfIRhE6BnYO5C9TbY5 CoFri3sFSyeAwIUYcbvt7OElVTB2ro6xmqfc6ZspPqPLYnbc9wSSWSKLV8EFM+OS 6DD3UFiTPN1o0nb/Vo/fuOsryCE3oR2wfomWAr7XMeTbB2DOugocre0ttyxhhbBt Dkc0u3/a75AtisIPkoHPGQZX3671SnUKmge9VYGeMWBHpGCvXJMMvPonbkr2yema gxH5/KPBwmv4c/asL/nfKiQnHowxLGdCDVCQ+NKfhyvEKZ7WzwVzXekrWn3L8u1W xUy3O0XU3YQJVXX/S2ec5RwsGe9K/5OanKTkjeJ8q5zLtJA0ax0fJGyQ+/iEcjFy CnlW857EL1ChXQ2WItKvaLyxe/mea4HGonHe5nZSRVZtTVTYTSFASrJchmRR/eu2 NXnZPBtvAEn8MqTuNyVVjqwifojK8jdVox+mlNoQUoehLhyAYc4IHbC6+/2c5HU7 dW5tFMGPOlQNmYbXqe+oKSUaaSWcxUaPTzmD6IRUrozrhabyv/lb79GXDLb2c6QL Vz7WtY1qTD7TOwPv+Xyd =OclH -----END PGP SIGNATURE----- Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "The latest and greatest fixes for ARM platform code. Worth pointing out are: - Lines-wise, largest is a PXA fix for dealing with interrupts on DT that was quite broken. It's still newish code so while we could have held this off, it seemed appropriate to include now - Some GPIO fixes for OMAP platforms added a few lines. This was also fixes for code recently added (this release). - Small OMAP timer fix to behave better with partially upstreamed platforms, which is quite welcome. - Allwinner fixes about operating point control, reducing overclocking in some cases for better stability. plus a handful of other smaller fixes across the map" * tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: juno: Fix misleading name of UART reference clock ARM: dts: sunxi: Remove overclocked/overvoltaged OPP ARM: dts: sun4i: a10-lime: Override and remove 1008MHz OPP setting ARM: socfpga: dts: fix spi1 interrupt ARM: dts: Fix gpio interrupts for dm816x ARM: dts: dra7: remove ti,hwmod property from pcie phy ARM: OMAP: dmtimer: disable pm runtime on remove ARM: OMAP: dmtimer: check for pm_runtime_get_sync() failure ARM: OMAP2+: Fix socbus family info for AM33xx devices ARM: dts: omap3: Add missing dmas for crypto ARM: dts: rockchip: disable gmac by default in rk3288.dtsi MAINTAINERS: add rockchip regexp to the ARM/Rockchip entry ARM: pxa: fix pxa interrupts handling in DT ARM: pxa: Fix typo in zeus.c ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage
This commit is contained in:
commit
08f41f7c35
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@ -1362,6 +1362,7 @@ F: drivers/i2c/busses/i2c-rk3x.c
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|||
F: drivers/*/*rockchip*
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F: drivers/*/*/*rockchip*
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F: sound/soc/rockchip/
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N: rockchip
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||||
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ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
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M: Kukjin Kim <kgene@kernel.org>
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|
|
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@ -619,6 +619,7 @@ config ARCH_PXA
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select GENERIC_CLOCKEVENTS
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select GPIO_PXA
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select HAVE_IDE
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select PLAT_PXA
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select SPARSE_IRQ
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|
|
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@ -36,6 +36,20 @@
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>;
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};
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mmc_pins: pinmux_mmc_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
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DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
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DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
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DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
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DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
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DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
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DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
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DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
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DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
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>;
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};
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usb0_pins: pinmux_usb0_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
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|
@ -137,7 +151,12 @@
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc_pins>;
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vmmc-supply = <&vmmcsd_fixed>;
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bus-width = <4>;
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cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
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};
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/* At least dm8168-evm rev c won't support multipoint, later may */
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|
|
|
@ -150,17 +150,27 @@
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};
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gpio1: gpio@48032000 {
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compatible = "ti,omap3-gpio";
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio1";
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ti,gpio-always-on;
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reg = <0x48032000 0x1000>;
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interrupts = <97>;
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interrupts = <96>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@4804c000 {
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compatible = "ti,omap3-gpio";
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio2";
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ti,gpio-always-on;
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reg = <0x4804c000 0x1000>;
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interrupts = <99>;
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interrupts = <98>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpmc: gpmc@50000000 {
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|
|
|
@ -1111,7 +1111,6 @@
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"wkupclk", "refclk",
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"div-clk", "phy-div";
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#phy-cells = <0>;
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ti,hwmods = "pcie1-phy";
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};
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|
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pcie2_phy: pciephy@4a095000 {
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|
@ -1130,7 +1129,6 @@
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"wkupclk", "refclk",
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"div-clk", "phy-div";
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#phy-cells = <0>;
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ti,hwmods = "pcie2-phy";
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status = "disabled";
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};
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};
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|
|
|
@ -92,6 +92,8 @@
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ti,hwmods = "aes";
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reg = <0x480c5000 0x50>;
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interrupts = <0>;
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dmas = <&sdma 65 &sdma 66>;
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dma-names = "tx", "rx";
|
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};
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|
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prm: prm@48306000 {
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||||
|
@ -550,6 +552,8 @@
|
|||
ti,hwmods = "sham";
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reg = <0x480c3000 0x64>;
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interrupts = <49>;
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dmas = <&sdma 69>;
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dma-names = "rx";
|
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};
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||||
|
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smartreflex_core: smartreflex@480cb000 {
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||||
|
|
|
@ -411,6 +411,7 @@
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|||
"mac_clk_rx", "mac_clk_tx",
|
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@ff500000 {
|
||||
|
|
|
@ -660,7 +660,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff01000 0x1000>;
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interrupts = <0 156 4>;
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||||
interrupts = <0 155 4>;
|
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num-cs = <4>;
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clocks = <&spi_m_clk>;
|
||||
status = "disabled";
|
||||
|
|
|
@ -56,6 +56,22 @@
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model = "Olimex A10-OLinuXino-LIME";
|
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compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
|
||||
|
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cpus {
|
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cpu0: cpu@0 {
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/*
|
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* The A10-Lime is known to be unstable
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* when running at 1008 MHz
|
||||
*/
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
912000 1350000
|
||||
864000 1300000
|
||||
624000 1250000
|
||||
>;
|
||||
cooling-max-level = <2>;
|
||||
};
|
||||
};
|
||||
|
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soc@01c00000 {
|
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emac: ethernet@01c0b000 {
|
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pinctrl-names = "default";
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|
|
|
@ -75,7 +75,6 @@
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
|
||||
1056000 1500000
|
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1008000 1400000
|
||||
912000 1350000
|
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864000 1300000
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||||
|
@ -83,7 +82,7 @@
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>;
|
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#cooling-cells = <2>;
|
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cooling-min-level = <0>;
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cooling-max-level = <4>;
|
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cooling-max-level = <3>;
|
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};
|
||||
};
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||||
|
||||
|
|
|
@ -47,7 +47,6 @@
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
|
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/* kHz uV */
|
||||
1104000 1500000
|
||||
1008000 1400000
|
||||
912000 1350000
|
||||
864000 1300000
|
||||
|
@ -57,7 +56,7 @@
|
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <6>;
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cooling-max-level = <5>;
|
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};
|
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};
|
||||
|
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|
|
|
@ -105,7 +105,6 @@
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|||
clock-latency = <244144>; /* 8 32k periods */
|
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operating-points = <
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||||
/* kHz uV */
|
||||
1008000 1450000
|
||||
960000 1400000
|
||||
912000 1400000
|
||||
864000 1300000
|
||||
|
@ -116,7 +115,7 @@
|
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>;
|
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#cooling-cells = <2>;
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cooling-min-level = <0>;
|
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cooling-max-level = <7>;
|
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cooling-max-level = <6>;
|
||||
};
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||||
|
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cpu@1 {
|
||||
|
|
|
@ -720,6 +720,8 @@ static const char * __init omap_get_family(void)
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return kasprintf(GFP_KERNEL, "OMAP4");
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else if (soc_is_omap54xx())
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return kasprintf(GFP_KERNEL, "OMAP5");
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else if (soc_is_am33xx() || soc_is_am335x())
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return kasprintf(GFP_KERNEL, "AM33xx");
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else if (soc_is_am43xx())
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return kasprintf(GFP_KERNEL, "AM43xx");
|
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else if (soc_is_dra7xx())
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|
|
|
@ -11,6 +11,7 @@
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* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
|
||||
*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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|
@ -40,7 +41,6 @@
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#define ICHP_VAL_IRQ (1 << 31)
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#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
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#define IPR_VALID (1 << 31)
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#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
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#define MAX_INTERNAL_IRQS 128
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|
@ -51,6 +51,7 @@
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static void __iomem *pxa_irq_base;
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static int pxa_internal_irq_nr;
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static bool cpu_has_ipr;
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static struct irq_domain *pxa_irq_domain;
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|
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static inline void __iomem *irq_base(int i)
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{
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|
@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i)
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void pxa_mask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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irq_hw_number_t irq = irqd_to_hwirq(d);
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uint32_t icmr = __raw_readl(base + ICMR);
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icmr &= ~(1 << IRQ_BIT(d->irq));
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icmr &= ~BIT(irq & 0x1f);
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__raw_writel(icmr, base + ICMR);
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}
|
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|
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void pxa_unmask_irq(struct irq_data *d)
|
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{
|
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void __iomem *base = irq_data_get_irq_chip_data(d);
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irq_hw_number_t irq = irqd_to_hwirq(d);
|
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uint32_t icmr = __raw_readl(base + ICMR);
|
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|
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icmr |= 1 << IRQ_BIT(d->irq);
|
||||
icmr |= BIT(irq & 0x1f);
|
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__raw_writel(icmr, base + ICMR);
|
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}
|
||||
|
||||
|
@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
|
|||
} while (1);
|
||||
}
|
||||
|
||||
void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
|
||||
static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
int irq, i, n;
|
||||
void __iomem *base = irq_base(hw / 32);
|
||||
|
||||
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
|
||||
/* initialize interrupt priority */
|
||||
if (cpu_has_ipr)
|
||||
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
|
||||
|
||||
irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(virq, base);
|
||||
set_irq_flags(virq, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops pxa_irq_ops = {
|
||||
.map = pxa_irq_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static __init void
|
||||
pxa_init_irq_common(struct device_node *node, int irq_nr,
|
||||
int (*fn)(struct irq_data *, unsigned int))
|
||||
{
|
||||
int n;
|
||||
|
||||
pxa_internal_irq_nr = irq_nr;
|
||||
cpu_has_ipr = !cpu_is_pxa25x();
|
||||
pxa_irq_base = io_p2v(0x40d00000);
|
||||
pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
|
||||
PXA_IRQ(0), 0,
|
||||
&pxa_irq_ops, NULL);
|
||||
if (!pxa_irq_domain)
|
||||
panic("Unable to add PXA IRQ domain\n");
|
||||
irq_set_default_host(pxa_irq_domain);
|
||||
|
||||
for (n = 0; n < irq_nr; n += 32) {
|
||||
void __iomem *base = irq_base(n >> 5);
|
||||
|
||||
__raw_writel(0, base + ICMR); /* disable all IRQs */
|
||||
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
|
||||
for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
|
||||
/* initialize interrupt priority */
|
||||
if (cpu_has_ipr)
|
||||
__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
|
||||
|
||||
irq = PXA_IRQ(i);
|
||||
irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(irq, base);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
|
||||
/* only unmasked interrupts kick us out of idle */
|
||||
__raw_writel(1, irq_base(0) + ICCR);
|
||||
|
||||
pxa_internal_irq_chip.irq_set_wake = fn;
|
||||
}
|
||||
|
||||
void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
|
||||
{
|
||||
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
|
||||
|
||||
pxa_irq_base = io_p2v(0x40d00000);
|
||||
cpu_has_ipr = !cpu_is_pxa25x();
|
||||
pxa_init_irq_common(NULL, irq_nr, fn);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
|
||||
static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
|
||||
|
@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct irq_domain *pxa_irq_domain;
|
||||
|
||||
static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
void __iomem *base = irq_base(hw / 32);
|
||||
|
||||
/* initialize interrupt priority */
|
||||
if (cpu_has_ipr)
|
||||
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
|
||||
|
||||
irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(hw, base);
|
||||
set_irq_flags(hw, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops pxa_irq_ops = {
|
||||
.map = pxa_irq_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static const struct of_device_id intc_ids[] __initconst = {
|
||||
{ .compatible = "marvell,pxa-intc", },
|
||||
{}
|
||||
|
@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
|
|||
{
|
||||
struct device_node *node;
|
||||
struct resource res;
|
||||
int n, ret;
|
||||
int ret;
|
||||
|
||||
node = of_find_matching_node(NULL, intc_ids);
|
||||
if (!node) {
|
||||
|
@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
|
|||
return;
|
||||
}
|
||||
|
||||
pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
|
||||
&pxa_irq_ops, NULL);
|
||||
if (!pxa_irq_domain)
|
||||
panic("Unable to add PXA IRQ domain\n");
|
||||
|
||||
irq_set_default_host(pxa_irq_domain);
|
||||
|
||||
for (n = 0; n < pxa_internal_irq_nr; n += 32) {
|
||||
void __iomem *base = irq_base(n >> 5);
|
||||
|
||||
__raw_writel(0, base + ICMR); /* disable all IRQs */
|
||||
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
|
||||
}
|
||||
|
||||
/* only unmasked interrupts kick us out of idle */
|
||||
__raw_writel(1, irq_base(0) + ICCR);
|
||||
|
||||
pxa_internal_irq_chip.irq_set_wake = fn;
|
||||
pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
|
|
@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = {
|
|||
};
|
||||
|
||||
static struct platform_device can_regulator_device = {
|
||||
.name = "reg-fixed-volage",
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &can_regulator_pdata,
|
||||
|
|
|
@ -1,10 +1,12 @@
|
|||
menuconfig ARCH_SUNXI
|
||||
bool "Allwinner SoCs" if ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select PINCTRL
|
||||
select SUN4I_TIMER
|
||||
select RESET_CONTROLLER
|
||||
|
||||
if ARCH_SUNXI
|
||||
|
||||
|
@ -20,10 +22,8 @@ config MACH_SUN5I
|
|||
config MACH_SUN6I
|
||||
bool "Allwinner A31 (sun6i) SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARM_GIC
|
||||
select MFD_SUN6I_PRCM
|
||||
select RESET_CONTROLLER
|
||||
select SUN5I_HSTIMER
|
||||
|
||||
config MACH_SUN7I
|
||||
|
@ -37,16 +37,12 @@ config MACH_SUN7I
|
|||
config MACH_SUN8I
|
||||
bool "Allwinner A23 (sun8i) SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARM_GIC
|
||||
select MFD_SUN6I_PRCM
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config MACH_SUN9I
|
||||
bool "Allwinner (sun9i) SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARM_GIC
|
||||
select RESET_CONTROLLER
|
||||
|
||||
endif
|
||||
|
|
|
@ -799,6 +799,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
const struct of_device_id *match;
|
||||
const struct dmtimer_platform_data *pdata;
|
||||
int ret;
|
||||
|
||||
match = of_match_device(of_match_ptr(omap_timer_match), dev);
|
||||
pdata = match ? match->data : dev->platform_data;
|
||||
|
@ -860,7 +861,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
if (!timer->reserved) {
|
||||
pm_runtime_get_sync(dev);
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
|
||||
__func__);
|
||||
goto err_get_sync;
|
||||
}
|
||||
__omap_dm_timer_init_regs(timer);
|
||||
pm_runtime_put(dev);
|
||||
}
|
||||
|
@ -873,6 +879,11 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
|||
dev_dbg(dev, "Device Probed.\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_get_sync:
|
||||
pm_runtime_put_noidle(dev);
|
||||
pm_runtime_disable(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -899,6 +910,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev)
|
|||
}
|
||||
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
/* SoC fixed clocks */
|
||||
soc_uartclk: refclk72738khz {
|
||||
soc_uartclk: refclk7273800hz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <7273800>;
|
||||
|
|
Loading…
Reference in New Issue