ARM: imx: define an enum for gpt timer device type

Define an enum for gpt timer device type in include/soc/imx/timer.h to
tell the gpt block differences among SoCs.  Update non-DT users (clock
drivers) to pass the device type.

As we now have include/soc/imx/timer.h, the declaration of
mxc_timer_init() is moved into there as the best fit.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo 2015-05-15 11:41:39 +08:00
parent 6dd747825b
commit 0931aff722
8 changed files with 41 additions and 13 deletions

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@ -32,6 +32,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/timer.h>
#include <asm/mach/time.h>
@ -86,6 +87,7 @@ static struct clock_event_device clockevent_mxc;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
struct imx_timer {
enum imx_gpt_type type;
void __iomem *base;
int irq;
struct clk *clk_per;
@ -356,7 +358,7 @@ static void __init _mxc_timer_init(struct imx_timer *imxtm)
setup_irq(imxtm->irq, &mxc_timer_irq);
}
void __init mxc_timer_init(unsigned long pbase, int irq)
void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
{
struct imx_timer *imxtm;
@ -369,6 +371,8 @@ void __init mxc_timer_init(unsigned long pbase, int irq)
imxtm->base = ioremap(pbase, SZ_4K);
BUG_ON(!imxtm->base);
imxtm->type = type;
_mxc_timer_init(imxtm);
}

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@ -23,6 +23,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx1-clock.h>
#include <soc/imx/timer.h>
#include <asm/irq.h>
#include "clk.h"
@ -102,7 +103,7 @@ int __init mx1_clocks_init(unsigned long fref)
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT);
mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT, GPT_TYPE_IMX1);
return 0;
}

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@ -15,6 +15,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx21-clock.h>
#include <soc/imx/timer.h>
#include <asm/irq.h>
#include "clk.h"
@ -156,7 +157,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1);
mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1, GPT_TYPE_IMX21);
return 0;
}

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@ -6,6 +6,7 @@
#include <linux/of_address.h>
#include <dt-bindings/clock/imx27-clock.h>
#include <soc/imx/revision.h>
#include <soc/imx/timer.h>
#include <asm/irq.h>
#include "clk.h"
@ -233,7 +234,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1);
mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21);
return 0;
}

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@ -22,6 +22,7 @@
#include <linux/err.h>
#include <linux/of.h>
#include <soc/imx/revision.h>
#include <soc/imx/timer.h>
#include <asm/irq.h>
#include "clk.h"
@ -198,7 +199,7 @@ int __init mx31_clocks_init(unsigned long fref)
mx31_revision();
clk_disable_unprepare(clk[iim_gate]);
mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT);
mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
return 0;
}

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@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/err.h>
#include <soc/imx/revision.h>
#include <soc/imx/timer.h>
#include <asm/irq.h>
#include "clk.h"
@ -293,7 +294,7 @@ int __init mx35_clocks_init(void)
imx_print_silicon_rev("i.MX35", mx35_revision());
mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT);
mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
return 0;
}

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@ -6,13 +6,6 @@
extern spinlock_t imx_ccm_lock;
/*
* This is a stop-gap solution for clock drivers like imx1/imx21 which call
* mxc_timer_init() to initialize timer for non-DT boot. It can be removed
* when these legacy non-DT support is converted or dropped.
*/
void mxc_timer_init(unsigned long pbase, int irq);
void imx_check_clocks(struct clk *clks[], unsigned int count);
extern void imx_cscmr1_fixup(u32 *val);

26
include/soc/imx/timer.h Normal file
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@ -0,0 +1,26 @@
/*
* Copyright 2015 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __SOC_IMX_TIMER_H__
#define __SOC_IMX_TIMER_H__
enum imx_gpt_type {
GPT_TYPE_IMX1, /* i.MX1 */
GPT_TYPE_IMX21, /* i.MX21/27 */
GPT_TYPE_IMX31, /* i.MX31/35/25/37/51/6Q */
GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */
};
/*
* This is a stop-gap solution for clock drivers like imx1/imx21 which call
* mxc_timer_init() to initialize timer for non-DT boot. It can be removed
* when these legacy non-DT support is converted or dropped.
*/
void mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type);
#endif /* __SOC_IMX_TIMER_H__ */