From 09e71a6f13445974fe9b70b6d4b68ac362cd68b6 Mon Sep 17 00:00:00 2001
From: Dave Jiang <dave.jiang@intel.com>
Date: Tue, 13 Dec 2016 09:03:13 -0700
Subject: [PATCH] ntb: fix SKX NTB config space size register offsets

The offsets for the SZ registers are wrong. Updated.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reported-by: Sandeep Mann <sandeep@purestorage.com>
Tested-by: Zachary Ross <zacharyx.ross@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
---
 drivers/ntb/hw/intel/ntb_hw_intel.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index 6e8c1824eb19..f2cf8a783f1e 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -152,10 +152,10 @@
 #define XEON_SPAD_COUNT			16
 
 /* Intel Skylake Xeon hardware */
-#define SKX_IMBAR1SZ_OFFSET		0x00d1
-#define SKX_IMBAR2SZ_OFFSET		0x00d5
-#define SKX_EMBAR1SZ_OFFSET		0x00d3
-#define SKX_EMBAR2SZ_OFFSET		0x00d6
+#define SKX_IMBAR1SZ_OFFSET		0x00d0
+#define SKX_IMBAR2SZ_OFFSET		0x00d1
+#define SKX_EMBAR1SZ_OFFSET		0x00d2
+#define SKX_EMBAR2SZ_OFFSET		0x00d3
 #define SKX_DEVCTRL_OFFSET		0x0098
 #define SKX_DEVSTS_OFFSET		0x009a
 #define SKX_UNCERRSTS_OFFSET		0x014c