OpenE2K
/
linux
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

ARM: SoC cleanups for 3.16 

Cleanups for 3.16. Among these are:
 
 - A bunch of misc cleanups for Broadcom platforms, mostly housekeeping
 - Enabling Common Clock Framework on the older s3c24xx Samsung chipsets
 - Cleanup of the Versatile Express system controller code, moving it to syscon
 - Power management cleanups for OMAP platforms
 
 + a handful of other cleanups across the place
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJTjMwHAAoJEIwa5zzehBx3MjMP/iELgDsqbNE2wxF9Fb5EEnoe
 S11q1QIvVrMVdMcKFN5HfW7f+xNso6+4SwXW0cRrJokGvaqRE758WZWuZq0QBUeS
 RYMhfpqmI6pTTJUyy6i6OyXhuRqu8rQ1NPEAatYrKzmtwFX1H4t25f1YtZWhBcK8
 ONi45FHeH1OKGGpjpT63uhWEzLk+LZI2MtgxmWoFcemf7guX6vEPJVuVRi8eqLoS
 9vl1cAkweYgGhjvQFcSXENaguV50dZlLc9C41dJk9KVvJfRt7o+/cRbG5YpGvnp5
 Liu+OWM72w0BkgNk6wDN4kaPX5UGLF8QX11JlvDRCJ2FcPtM4NBG/C9TqLMfkKDR
 Ze+ITiXh6NjefdTZWJaM4vzsd6vFws8EYAP24IWFlZ451bNLVN1lzlgqluPNoKmj
 CAsFPZhY/x5X9a8VLZ72ohx3N17T/iMsOlbiWtnlfqDcL6N0IoLG1YkFFeQIKEAH
 mpobWus8Myq1miWqSaeXh5wOqUVQmYR0I8jNoTfte1nBYSaIGhtMixoQhM6Zw50C
 dgSh4p7qhrZUOnYmkPqFXr7NCJ9n3RD10Xu8d/3IIp0u9RJ5Kx6NCEg9adq22jZQ
 XGrr/vH0sM8MzpKmfTMi5t2Cx5kP2G+O3enq0hQi4x3Cb4o8vwWQlMgydTd+xBjj
 aLo3WTTw0h6nTuKkZL2p
 =wuX4
 -----END PGP SIGNATURE-----

Merge tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC cleanups from Olof Johansson:
 "Cleanups for 3.16.  Among these are:

   - a bunch of misc cleanups for Broadcom platforms, mostly
     housekeeping
   - enabling Common Clock Framework on the older s3c24xx Samsung
     chipsets
   - cleanup of the Versatile Express system controller code, moving it
     to syscon
   - power management cleanups for OMAP platforms

  plus a handful of other cleanups across the place"

* tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
  ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
  clk: samsung: fix build error
  ARM: vexpress: refine dependencies for new code
  clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
  cpufreq: exynos: Fix the compile error
  ARM: S3C24XX: move debug-macro.S into the common space
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: trim down debug uart handling
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
  ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
  ARM: EXYNOS: Remove exynos_subsys registration
  ARM: EXYNOS: Remove duplicate lines in Makefile
  ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
  ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
  ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
  ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
  ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
  ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
  ARM: OMAP2+: PRCM: cleanup some header includes
  ...
This commit is contained in:
Linus Torvalds 2014-06-02 16:14:07 -07:00
parent ff933a0817 08d38bebb4
commit 0a58471541
211 changed files with 4689 additions and 5195 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
View File

@ -8,6 +8,8 @@ interrupt generation, MMC and NOR Flash control etc.
Required node properties:
- compatible value : = "arm,vexpress,sysreg";
- reg : physical base address and the size of the registers window
Deprecated properties, replaced by GPIO subnodes (see below):
- gpio-controller : specifies that the node is a GPIO controller
- #gpio-cells : size of the GPIO specifier, should be 2:
- first cell is the pseudo-GPIO line number:
@ -16,35 +18,86 @@ Required node properties:
2 - NOR FLASH WPn
- second cell can take standard GPIO flags (currently ignored).
Control registers providing pseudo-GPIO lines must be represented
by subnodes, each of them requiring the following properties:
- compatible value : one of
"arm,vexpress-sysreg,sys_led"
"arm,vexpress-sysreg,sys_mci"
"arm,vexpress-sysreg,sys_flash"
- gpio-controller : makes the node a GPIO controller
- #gpio-cells : size of the GPIO specifier, must be 2:
- first cell is the function number:
- for sys_led : 0..7 = LED 0..7
- for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
- for sys_flash : 0 = NOR FLASH WPn
- second cell can take standard GPIO flags (currently ignored).
Example:
v2m_sysreg: sysreg@10000000 {
compatible = "arm,vexpress-sysreg";
reg = <0x10000000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
v2m_led_gpios: sys_led@08 {
compatible = "arm,vexpress-sysreg,sys_led";
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: sys_mci@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: sys_flash@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
gpio-controller;
#gpio-cells = <2>;
};
};
This block also can also act a bridge to the platform's configuration
bus via "system control" interface, addressing devices with site number,
position in the board stack, config controller, function and device
numbers - see motherboard's TRM for more details.
The node describing a config device must refer to the sysreg node via
"arm,vexpress,config-bridge" phandle (can be also defined in the node's
parent) and relies on the board topology properties - see main vexpress
node documentation for more details. It must also define the following
property:
- arm,vexpress-sysreg,func : must contain two cells:
- first cell defines function number (eg. 1 for clock generator,
2 for voltage regulators etc.)
- device number (eg. osc 0, osc 1 etc.)
numbers - see motherboard's TRM for more details. All configuration
controller accessible via this interface must reference the sysreg
node via "arm,vexpress,config-bridge" phandle and define appropriate
topology properties - see main vexpress node documentation for more
details. Each child of such node describes one function and must
define the following properties:
- compatible value : must be one of (corresponding to the TRM):
"arm,vexpress-amp"
"arm,vexpress-dvimode"
"arm,vexpress-energy"
"arm,vexpress-muxfpga"
"arm,vexpress-osc"
"arm,vexpress-power"
"arm,vexpress-reboot"
"arm,vexpress-reset"
"arm,vexpress-scc"
"arm,vexpress-shutdown"
"arm,vexpress-temp"
"arm,vexpress-volt"
- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
- first cell of each group defines the function number
(eg. 1 for clock generator, 2 for voltage regulators etc.)
- second cell of each group defines device number (eg. osc 0,
osc 1 etc.)
- some functions (eg. energy meter, with its 64 bit long counter)
are using more than one function/device number pair
Example:
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
};
energy@0 {
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>, <13 1>;
};
};

15
Documentation/devicetree/bindings/arm/vexpress.txt
View File

@ -80,12 +80,17 @@ but also control clock generators, voltage regulators, gather
environmental data like temperature, power consumption etc. Even
the video output switch (FPGA) is controlled that way.
Nodes describing devices controlled by this infrastructure should
point at the bridge device node:
The controllers are not mapped into normal memory address space
and must be accessed through bridges - other devices capable
of generating transactions on the configuration bus.
The nodes describing configuration controllers must define
the following properties:
- compatible value:
compatible = "arm,vexpress,config-bus";
- bridge phandle:
arm,vexpress,config-bridge = <phandle>;
This property can be also defined in a parent node (eg. for a DCC)
and is effective for all children.
and children describing available functions.
Platform topology
@ -197,7 +202,7 @@ Example of a VE tile description (simplified)
};
dcc {
compatible = "simple-bus";
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {

50
Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt Normal file
View File

@ -0,0 +1,50 @@
* Samsung S3C2410 Clock Controller
The S3C2410 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2410,
s3c2440 and s3c2442 SoCs in the s3c24x family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
- "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
- "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/samsung,s3c2410-clock.h header and can be used in device
tree sources.
External clocks:
The xti clock used as input for the plls is generated outside the SoC. It is
expected that is are defined using standard clock bindings with a
clock-output-names value of "xti".
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2410-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
status = "disabled";
};

50
Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt Normal file
View File

@ -0,0 +1,50 @@
* Samsung S3C2412 Clock Controller
The S3C2412 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2412
and s3c2413 SoCs in the s3c24x family.
Required Properties:
- compatible: should be "samsung,s3c2412-clock"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2412.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2412-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2412-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
status = "disabled";
};

56
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt Normal file
View File

@ -0,0 +1,56 @@
* Samsung S3C2443 Clock Controller
The S3C2443 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the s3c24x family starting with the s3c2443.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
- "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
- "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2443.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
- "ext_i2s" - external I2S clock - optional,
- "ext_uart" - external uart clock - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
status = "disabled";
};

1
arch/arm/Kconfig
View File

@ -314,6 +314,7 @@ config ARCH_MULTIPLATFORM
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select USE_OF

54
arch/arm/Kconfig.debug
View File

@ -625,6 +625,7 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -637,6 +638,7 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -649,6 +651,7 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -670,6 +673,33 @@ choice
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C2410_UART0
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART1
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 1. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART2
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 2. The port must have been initialised
by the boot-loader before use.
config DEBUG_SOCFPGA_UART
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART for low-level debug"
@ -921,6 +951,13 @@ endchoice
config DEBUG_EXYNOS_UART
bool
config DEBUG_S3C2410_UART
bool
select DEBUG_S3C24XX_UART
config DEBUG_S3C24XX_UART
bool
config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
@ -973,6 +1010,7 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX6SL_UART
default "debug/msm.S" if DEBUG_MSM_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/sti.S" if DEBUG_STI_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
@ -1029,6 +1067,12 @@ config DEBUG_UART_PHYS
default 0x40090000 if ARCH_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
default 0x42000000 if ARCH_GEMINI
default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0x7c0003f8 if FOOTBRIDGE
default 0x80070000 if DEBUG_IMX23_UART
default 0x80074000 if DEBUG_IMX28_UART
@ -1058,7 +1102,7 @@ config DEBUG_UART_PHYS
default 0xfffff700 if ARCH_IOP33X
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
@ -1075,6 +1119,12 @@ config DEBUG_UART_VIRT
default 0xf2100000 if DEBUG_PXA_UART1
default 0xf4090000 if ARCH_LPC32XX
default 0xf4200000 if ARCH_GEMINI
default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
@ -1116,7 +1166,7 @@ config DEBUG_UART_VIRT
default 0xff003000 if DEBUG_U300_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"

5
arch/arm/boot/compressed/head.S
View File

@ -60,11 +60,6 @@
add \rb, \rb, #0x00010000 @ Ser1
#endif
.endm
#elif defined(CONFIG_ARCH_S3C24XX)
.macro loadsp, rb, tmp
mov \rb, #0x50000000
add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
.endm
#else
.macro loadsp, rb, tmp
addruart \rb, \tmp

1
arch/arm/boot/dts/atlas6.dtsi
View File

@ -195,6 +195,7 @@
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
clocks = <&clks 11>;
};
nand@b0030000 {

1
arch/arm/boot/dts/prima2.dtsi
View File

@ -201,6 +201,7 @@
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
clocks = <&clks 11>;
};
nand@b0030000 {

13
arch/arm/boot/dts/s3c2416-smdk2416.dts
View File

@ -19,6 +19,19 @@
reg = <0x30000000 0x4000000>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
xti: xti {
compatible = "fixed-clock";
clock-frequency = <12000000>;
clock-output-names = "xti";
#clock-cells = <0>;
};
};
serial@50000000 {
status = "okay";
pinctrl-names = "default";

42
arch/arm/boot/dts/s3c2416.dtsi
View File

@ -8,6 +8,7 @@
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/s3c2443.h>
#include "s3c24xx.dtsi"
#include "s3c2416-pinctrl.dtsi"
@ -28,26 +29,53 @@
compatible = "samsung,s3c2416-irq";
};
clocks: clock-controller@0x4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
};
pinctrl@56000000 {
compatible = "samsung,s3c2416-pinctrl";
};
timer@51000000 {
clocks = <&clocks PCLK_PWM>;
clock-names = "timers";
};
serial@50000000 {
compatible = "samsung,s3c2440-uart";
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
};
serial@50004000 {
compatible = "samsung,s3c2440-uart";
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
<&clocks SCLK_UART>;
};
serial@50008000 {
compatible = "samsung,s3c2440-uart";
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
<&clocks SCLK_UART>;
};
serial@5000C000 {
compatible = "samsung,s3c2440-uart";
reg = <0x5000C000 0x4000>;
interrupts = <1 18 24 4>, <1 18 25 4>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
<&clocks SCLK_UART>;
status = "disabled";
};
@ -55,6 +83,10 @@
compatible = "samsung,s3c6410-sdhci";
reg = <0x4AC00000 0x100>;
interrupts = <0 0 21 3>;
clock-names = "hsmmc", "mmc_busclk.0",
"mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
<&clocks MUX_HSMMC0>;
status = "disabled";
};
@ -62,18 +94,28 @@
compatible = "samsung,s3c6410-sdhci";
reg = <0x4A800000 0x100>;
interrupts = <0 0 20 3>;
clock-names = "hsmmc", "mmc_busclk.0",
"mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
<&clocks MUX_HSMMC1>;
status = "disabled";
};
watchdog@53000000 {
interrupts = <1 9 27 3>;
clocks = <&clocks PCLK_WDT>;
clock-names = "watchdog";
};
rtc@57000000 {
compatible = "samsung,s3c2416-rtc";
clocks = <&clocks PCLK_RTC>;
clock-names = "rtc";
};
i2c@54000000 {
compatible = "samsung,s3c2440-i2c";
clocks = <&clocks PCLK_I2C0>;
clock-names = "i2c";
};
};

76
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
View File

@ -74,8 +74,24 @@
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
v2m_led_gpios: sys_led@08 {
compatible = "arm,vexpress-sysreg,sys_led";
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: sys_mci@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: sys_flash@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
gpio-controller;
#gpio-cells = <2>;
};
};
v2m_sysctl: sysctl@020000 {
@ -113,8 +129,8 @@
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9 10>;
cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>;
cd-gpios = <&v2m_mmc_gpios 0 0>;
wp-gpios = <&v2m_mmc_gpios 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
@ -265,6 +281,58 @@
clock-output-names = "v2m:refclk32khz";
};
leds {
compatible = "gpio-leds";
user@1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
user@2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
user@3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
user@4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
user@5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
user@6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
user@7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
user@8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";
};
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;

76
arch/arm/boot/dts/vexpress-v2m.dtsi
View File

@ -73,8 +73,24 @@
v2m_sysreg: sysreg@00000 {
compatible = "arm,vexpress-sysreg";
reg = <0x00000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
v2m_led_gpios: sys_led@08 {
compatible = "arm,vexpress-sysreg,sys_led";
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: sys_mci@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: sys_flash@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
gpio-controller;
#gpio-cells = <2>;
};
};
v2m_sysctl: sysctl@01000 {
@ -112,8 +128,8 @@
compatible = "arm,pl180", "arm,primecell";
reg = <0x05000 0x1000>;
interrupts = <9 10>;
cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>;
cd-gpios = <&v2m_mmc_gpios 0 0>;
wp-gpios = <&v2m_mmc_gpios 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
@ -264,6 +280,58 @@
clock-output-names = "v2m:refclk32khz";
};
leds {
compatible = "gpio-leds";
user@1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
user@2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
user@3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
user@4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
user@5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
user@6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
user@7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
user@8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";
};
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;

5
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View File

@ -312,6 +312,7 @@
arm,vexpress-sysreg,func = <12 0>;
label = "A15 Pcore";
};
power@1 {
/* Total power for the three A7 cores */
compatible = "arm,vexpress-power";
@ -322,14 +323,14 @@
energy@0 {
/* Total energy for the two A15 cores */
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>;
arm,vexpress-sysreg,func = <13 0>, <13 1>;
label = "A15 Jcore";
};
energy@2 {
/* Total energy for the three A7 cores */
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 2>;
arm,vexpress-sysreg,func = <13 2>, <13 3>;
label = "A7 Jcore";
};
};

2
arch/arm/configs/realview-smp_defconfig
View File

@ -76,8 +76,10 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_VERSATILE=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_PL031=y

2
arch/arm/configs/realview_defconfig
View File

@ -75,8 +75,10 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_VERSATILE=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_PL031=y

3
arch/arm/configs/versatile_defconfig
View File

@ -61,6 +61,9 @@ CONFIG_SND_ARMAACI=m
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_VERSATILE=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_EXT2_FS=y

46
arch/arm/include/debug/s3c24xx.S Normal file
View File

@ -0,0 +1,46 @@
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Copyright (C) 2005 Simtec Electronics
*
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_s3c.h>
#define S3C2410_UART1_OFF (0x4000)
.macro addruart, rp, rv, tmp
ldr \rp, = CONFIG_DEBUG_UART_PHYS
ldr \rv, = CONFIG_DEBUG_UART_VIRT
.endm
.macro fifo_full_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
.macro fifo_level_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2410_UFSTAT_TXMASK
.endm
/* Select the correct implementation depending on the configuration. The
* S3C2440 will get selected by default, as these are the most widely
* used variants of these
*/
#if defined(CONFIG_DEBUG_S3C2410_UART)
#define fifo_full fifo_full_s3c2410
#define fifo_level fifo_level_s3c2410
#endif
/* include the reset of the code which will do the work */
#include <debug/samsung.S>

49
arch/arm/mach-bcm/Kconfig
View File

@ -10,22 +10,51 @@ if ARCH_BCM
menu "Broadcom SoC Selection"
config ARCH_BCM_MOBILE
bool "Broadcom Mobile SoC" if ARCH_MULTI_V7
depends on MMU
bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select GPIO_BCM_KONA
select TICK_ONESHOT
select CACHE_L2X0
select HAVE_ARM_ARCH_TIMER
select PINCTRL
help
This enables support for systems based on Broadcom mobile SoCs.
It currently supports the 'BCM281XX' family, which includes
BCM11130, BCM11140, BCM11351, BCM28145 and
BCM28155 variants.
if ARCH_BCM_MOBILE
menu "Broadcom Mobile SoC Selection"
config ARCH_BCM_281XX
bool "Broadcom BCM281XX SoC family"
default y
help
Enable support for the the BCM281XX family, which includes
BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
variants.
config ARCH_BCM_21664
bool "Broadcom BCM21664 SoC family"
default y
help
Enable support for the the BCM21664 family, which includes
BCM21663 and BCM21664 variants.
config ARCH_BCM_MOBILE_L2_CACHE
bool "Broadcom mobile SoC level 2 cache support"
depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
default y
select CACHE_L2X0
select ARCH_BCM_MOBILE_SMC
config ARCH_BCM_MOBILE_SMC
bool
depends on ARCH_BCM_281XX || ARCH_BCM_21664
endmenu
endif
config ARCH_BCM2835
bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
@ -33,10 +62,7 @@ config ARCH_BCM2835
select ARM_AMBA
select ARM_ERRATA_411920
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select CLKSRC_OF
select CPU_V6
select GENERIC_CLOCKEVENTS
select PINCTRL
select PINCTRL_BCM2835
help
@ -45,17 +71,12 @@ config ARCH_BCM2835
config ARCH_BCM_5301X
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
depends on MMU
select ARM_GIC
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select MIGHT_HAVE_PCI
help
Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.

21
arch/arm/mach-bcm/Makefile
View File

@ -10,10 +10,23 @@
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o board_bcm21664.o \
bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
# BCM281XX
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
# BCM21664
obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
# BCM281XX and BCM21664 L2 cache control
obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
# Support for secure monitor traps
obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec)
CFLAGS_bcm_kona_smc.o += -Wa,-march=armv7-a+sec -DREQUIRES_SEC
endif
# BCM2835
obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
# BCM5301X
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o

136
arch/arm/mach-bcm/bcm_kona_smc.c
View File

@ -21,11 +21,8 @@
#include "bcm_kona_smc.h"
struct secure_bridge_data {
void __iomem *bounce; /* virtual address */
u32 __iomem buffer_addr; /* physical address */
int initialized;
} bridge_data;
static u32 bcm_smc_buffer_phys; /* physical address */
static void __iomem *bcm_smc_buffer; /* virtual address */
struct bcm_kona_smc_data {
unsigned service_id;
@ -33,6 +30,7 @@ struct bcm_kona_smc_data {
unsigned arg1;
unsigned arg2;
unsigned arg3;
unsigned result;
};
static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
@ -41,59 +39,125 @@ static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
{},
};
/* Map in the bounce area */
/* Map in the args buffer area */
int __init bcm_kona_smc_init(void)
{
struct device_node *node;
const __be32 *prop_val;
u64 prop_size = 0;
unsigned long buffer_size;
u32 buffer_phys;
/* Read buffer addr and size from the device tree node */
node = of_find_matching_node(NULL, bcm_kona_smc_ids);
if (!node)
return -ENODEV;
/* Don't care about size or flags of the DT node */
bridge_data.buffer_addr =
be32_to_cpu(*of_get_address(node, 0, NULL, NULL));
BUG_ON(!bridge_data.buffer_addr);
prop_val = of_get_address(node, 0, &prop_size, NULL);
if (!prop_val)
return -EINVAL;
bridge_data.bounce = of_iomap(node, 0);
BUG_ON(!bridge_data.bounce);
/* We assume space for four 32-bit arguments */
if (prop_size < 4 * sizeof(u32) || prop_size > (u64)ULONG_MAX)
return -EINVAL;
buffer_size = (unsigned long)prop_size;
bridge_data.initialized = 1;
buffer_phys = be32_to_cpup(prop_val);
if (!buffer_phys)
return -EINVAL;
bcm_smc_buffer = ioremap(buffer_phys, buffer_size);
if (!bcm_smc_buffer)
return -ENOMEM;
bcm_smc_buffer_phys = buffer_phys;
pr_info("Kona Secure API initialized\n");
return 0;
}
/*
* int bcm_kona_do_smc(u32 service_id, u32 buffer_addr)
*
* Only core 0 can run the secure monitor code. If an "smc" request
* is initiated on a different core it must be redirected to core 0
* for execution. We rely on the caller to handle this.
*
* Each "smc" request supplies a service id and the address of a
* buffer containing parameters related to the service to be
* performed. A flags value defines the behavior of the level 2
* cache and interrupt handling while the secure monitor executes.
*
* Parameters to the "smc" request are passed in r4-r6 as follows:
* r4 service id
* r5 flags (SEC_ROM_*)
* r6 physical address of buffer with other parameters
*
* Execution of an "smc" request produces two distinct results.
*
* First, the secure monitor call itself (regardless of the specific
* service request) can succeed, or can produce an error. When an
* "smc" request completes this value is found in r12; it should
* always be SEC_EXIT_NORMAL.
*
* In addition, the particular service performed produces a result.
* The values that should be expected depend on the service. We
* therefore return this value to the caller, so it can handle the
* request result appropriately. This result value is found in r0
* when the "smc" request completes.
*/
static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys)
{
register u32 ip asm("ip"); /* Also called r12 */
register u32 r0 asm("r0");
register u32 r4 asm("r4");
register u32 r5 asm("r5");
register u32 r6 asm("r6");
r4 = service_id;
r5 = 0x3; /* Keep IRQ and FIQ off in SM */
r6 = buffer_phys;
asm volatile (
/* Make sure we got the registers we want */
__asmeq("%0", "ip")
__asmeq("%1", "r0")
__asmeq("%2", "r4")
__asmeq("%3", "r5")
__asmeq("%4", "r6")
#ifdef REQUIRES_SEC
".arch_extension sec\n"
#endif
" smc #0\n"
: "=r" (ip), "=r" (r0)
: "r" (r4), "r" (r5), "r" (r6)
: "r1", "r2", "r3", "r7", "lr");
BUG_ON(ip != SEC_EXIT_NORMAL);
return r0;
}
/* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
static void __bcm_kona_smc(void *info)
{
struct bcm_kona_smc_data *data = info;
u32 *args = bridge_data.bounce;
int rc = 0;
u32 *args = bcm_smc_buffer;
/* Must run on CPU 0 */
BUG_ON(smp_processor_id() != 0);
BUG_ON(!args);
/* Check map in the bounce area */
BUG_ON(!bridge_data.initialized);
/* Copy one 32 bit word into the bounce area */
args[0] = data->arg0;
args[1] = data->arg1;
args[2] = data->arg2;
args[3] = data->arg3;
/* Copy the four 32 bit argument values into the bounce area */
writel_relaxed(data->arg0, args++);
writel_relaxed(data->arg1, args++);
writel_relaxed(data->arg2, args++);
writel(data->arg3, args);
/* Flush caches for input data passed to Secure Monitor */
if (data->service_id != SSAPI_BRCM_START_VC_CORE)
flush_cache_all();
flush_cache_all();
/* Trap into Secure Monitor */
rc = bcm_kona_smc_asm(data->service_id, bridge_data.buffer_addr);
if (rc != SEC_ROM_RET_OK)
pr_err("Secure Monitor call failed (0x%x)!\n", rc);
/* Trap into Secure Monitor and record the request result */
data->result = bcm_kona_do_smc(data->service_id, bcm_smc_buffer_phys);
}
unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
@ -106,17 +170,13 @@ unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
data.arg1 = arg1;
data.arg2 = arg2;
data.arg3 = arg3;
data.result = 0;
/*
* Due to a limitation of the secure monitor, we must use the SMP
* infrastructure to forward all secure monitor calls to Core 0.
*/
if (get_cpu() != 0)
smp_call_function_single(0, __bcm_kona_smc, (void *)&data, 1);
else
__bcm_kona_smc(&data);
smp_call_function_single(0, __bcm_kona_smc, &data, 1);
put_cpu();
return 0;
return data.result;
}

52
arch/arm/mach-bcm/bcm_kona_smc.h
View File

@ -15,55 +15,12 @@
#define BCM_KONA_SMC_H
#include <linux/types.h>
#define FLAGS (SEC_ROM_ICACHE_ENABLE_MASK | SEC_ROM_DCACHE_ENABLE_MASK | \
SEC_ROM_IRQ_ENABLE_MASK | SEC_ROM_FIQ_ENABLE_MASK)
/*!
* Definitions for IRQ & FIQ Mask for ARM
*/
#define FIQ_IRQ_MASK 0xC0
#define FIQ_MASK 0x40
#define IRQ_MASK 0x80
/*!
* Secure Mode FLAGs
*/
/* When set, enables ICache within the secure mode */
#define SEC_ROM_ICACHE_ENABLE_MASK 0x00000001
/* When set, enables DCache within the secure mode */
#define SEC_ROM_DCACHE_ENABLE_MASK 0x00000002
/* When set, enables IRQ within the secure mode */
#define SEC_ROM_IRQ_ENABLE_MASK 0x00000004
/* When set, enables FIQ within the secure mode */
#define SEC_ROM_FIQ_ENABLE_MASK 0x00000008
/* When set, enables Unified L2 cache within the secure mode */
#define SEC_ROM_UL2_CACHE_ENABLE_MASK 0x00000010
/* Broadcom Secure Service API Service IDs */
#define SSAPI_DORMANT_ENTRY_SERV 0x01000000
#define SSAPI_PUBLIC_OTP_SERV 0x01000001
#define SSAPI_ENABLE_L2_CACHE 0x01000002
#define SSAPI_DISABLE_L2_CACHE 0x01000003
#define SSAPI_WRITE_SCU_STATUS 0x01000004
#define SSAPI_WRITE_PWR_GATE 0x01000005
/* Broadcom Secure Service API Return Codes */
/* Broadcom Secure Service API service IDs, return codes, and exit codes */
#define SSAPI_ENABLE_L2_CACHE 0x01000002
#define SEC_ROM_RET_OK 0x00000001
#define SEC_ROM_RET_FAIL 0x00000009
#define SSAPI_RET_FROM_INT_SERV 0x4
#define SEC_EXIT_NORMAL 0x1
#define SSAPI_ROW_AES 0x0E000006
#define SSAPI_BRCM_START_VC_CORE 0x0E000008
#ifndef __ASSEMBLY__
extern int __init bcm_kona_smc_init(void);
extern unsigned bcm_kona_smc(unsigned service_id,
@ -72,9 +29,4 @@ extern unsigned bcm_kona_smc(unsigned service_id,
unsigned arg2,
unsigned arg3);
extern int bcm_kona_smc_asm(u32 service_id,
u32 buffer_addr);
#endif /* __ASSEMBLY__ */
#endif /* BCM_KONA_SMC_H */

41
arch/arm/mach-bcm/bcm_kona_smc_asm.S
View File

@ -1,41 +0,0 @@
/*
* Copyright (C) 2013 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/linkage.h>
#include "bcm_kona_smc.h"
/*
* int bcm_kona_smc_asm(u32 service_id, u32 buffer_addr)
*/
ENTRY(bcm_kona_smc_asm)
stmfd sp!, {r4-r12, lr}
mov r4, r0 @ service_id
mov r5, #3 @ Keep IRQ and FIQ off in SM
/*
* Since interrupts are disabled in the open mode, we must keep
* interrupts disabled in secure mode by setting R5=0x3. If interrupts
* are enabled in open mode, we can set R5=0x0 to allow interrupts in
* secure mode. If we did this, the secure monitor would return back
* control to the open mode to handle the interrupt prior to completing
* the secure service. If this happened, R12 would not be
* SEC_EXIT_NORMAL and we would need to call SMC again after resetting
* R5 (it gets clobbered by the secure monitor) and setting R4 to
* SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor
* to finish up the previous uncompleted secure service.
*/
mov r6, r1 @ buffer_addr
smc #0
/* Check r12 for SEC_EXIT_NORMAL here if interrupts are enabled */
ldmfd sp!, {r4-r12, pc}
ENDPROC(bcm_kona_smc_asm)

5
arch/arm/mach-bcm/board_bcm21664.c
View File

@ -11,14 +11,13 @@
* GNU General Public License for more details.
*/
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include "bcm_kona_smc.h"
#include "kona.h"
#include "kona_l2_cache.h"
#define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr"

2
arch/arm/mach-bcm/board_bcm281xx.c
View File

@ -17,7 +17,7 @@
#include <asm/mach/arch.h>
#include "kona.h"
#include "kona_l2_cache.h"
#define SECWDOG_OFFSET 0x00000000
#define SECWDOG_RESERVED_MASK 0xe2000000

16
arch/arm/mach-bcm/kona.c → arch/arm/mach-bcm/kona_l2_cache.c
View File

@ -11,19 +11,18 @@
* GNU General Public License for more details.
*/
#include <linux/of_platform.h>
#include <linux/init.h>
#include <linux/printk.h>
#include <asm/hardware/cache-l2x0.h>
#include "bcm_kona_smc.h"
#include "kona.h"
void __init kona_l2_cache_init(void)
{
unsigned int result;
int ret;
if (!IS_ENABLED(CONFIG_CACHE_L2X0))
return;
ret = bcm_kona_smc_init();
if (ret) {
pr_info("Secure API not available (%d). Skipping L2 init.\n",
@ -31,7 +30,12 @@ void __init kona_l2_cache_init(void)
return;
}
bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
result = bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
if (result != SEC_ROM_RET_OK) {
pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n",
result);
return;
}
/*
* The aux_val and aux_mask have no effect since L2 cache is already

6
arch/arm/mach-bcm/kona.h → arch/arm/mach-bcm/kona_l2_cache.h
View File

@ -11,4 +11,8 @@
* GNU General Public License for more details.
*/
void __init kona_l2_cache_init(void);
#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE
void kona_l2_cache_init(void);
#else
#define kona_l2_cache_init() ((void)0)
#endif

1
arch/arm/mach-cns3xxx/Kconfig
View File

@ -1,7 +1,6 @@
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
select ARM_GIC
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.

7
arch/arm/mach-exynos/Makefile
View File

@ -12,20 +12,15 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o
obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-smc.o
obj-$(CONFIG_ARCH_EXYNOS) += firmware.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)

72
arch/arm/mach-exynos/common.h
View File

@ -15,6 +15,75 @@
#include <linux/reboot.h>
#include <linux/of.h>
#define EXYNOS4210_CPU_ID 0x43210000
#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4412_CPU_ID 0xE4412200
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
extern unsigned long samsung_cpu_id;
#define IS_SAMSUNG_CPU(name, id, mask) \
static inline int is_samsung_##name(void) \
{ \
return ((samsung_cpu_id & mask) == (id & mask)); \
}
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
#if defined(CONFIG_CPU_EXYNOS4210)
# define soc_is_exynos4210() is_samsung_exynos4210()
#else
# define soc_is_exynos4210() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4212)
# define soc_is_exynos4212() is_samsung_exynos4212()
#else
# define soc_is_exynos4212() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4412)
# define soc_is_exynos4412() is_samsung_exynos4412()
#else
# define soc_is_exynos4412() 0
#endif
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)
#if defined(CONFIG_SOC_EXYNOS5250)
# define soc_is_exynos5250() is_samsung_exynos5250()
#else
# define soc_is_exynos5250() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
# define soc_is_exynos5420() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5440)
# define soc_is_exynos5440() is_samsung_exynos5440()
#else
# define soc_is_exynos5440() 0
#endif
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
struct map_desc;
@ -63,4 +132,7 @@ struct exynos_pmu_conf {
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

1
arch/arm/mach-exynos/cpuidle.c
View File

@ -24,7 +24,6 @@
#include <asm/unified.h>
#include <asm/cpuidle.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <mach/map.h>

13
arch/arm/mach-exynos/exynos.c
View File

@ -26,8 +26,6 @@
#include <asm/mach/map.h>
#include <asm/memory.h>
#include <plat/cpu.h>
#include "common.h"
#include "mfc.h"
#include "regs-pmu.h"
@ -308,17 +306,6 @@ void __init exynos_init_io(void)
exynos_map_io();
}
struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
static int __init exynos_core_init(void)
{
return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);
static int __init exynos4_l2x0_cache_init(void)
{
int ret;

3
arch/arm/mach-exynos/firmware.c
View File

@ -18,8 +18,7 @@
#include <mach/map.h>
#include <plat/cpu.h>
#include "common.h"
#include "smc.h"
static int exynos_do_idle(void)

65
arch/arm/mach-exynos/hotplug.c
View File

@ -19,61 +19,9 @@
#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include <plat/cpu.h>
#include "common.h"
#include "regs-pmu.h"
static inline void cpu_enter_lowpower_a9(void)
{
unsigned int v;
asm volatile(
" mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
static inline void cpu_enter_lowpower_a15(void)
{
unsigned int v;
asm volatile(
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "Ir" (CR_C)
: "cc");
flush_cache_louis();
asm volatile(
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (0x40)
: "cc");
isb();
dsb();
}
static inline void cpu_leave_lowpower(void)
{
unsigned int v;
@ -132,19 +80,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
void __ref exynos_cpu_die(unsigned int cpu)
{
int spurious = 0;
int primary_part = 0;
/*
* we're ready for shutdown now, so do it.
* Exynos4 is A9 based while Exynos5 is A15; check the CPU part
* number by reading the Main ID register and then perform the
* appropriate sequence for entering low power.
*/
asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
if ((primary_part & 0xfff0) == 0xc0f0)
cpu_enter_lowpower_a15();
else
cpu_enter_lowpower_a9();
v7_exit_coherency_flush(louis);
platform_do_lowpower(cpu, &spurious);

2
arch/arm/mach-exynos/platsmp.c
View File

@ -26,8 +26,6 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
#include <plat/cpu.h>
#include "common.h"
#include "regs-pmu.h"

1
arch/arm/mach-exynos/pm.c
View File

@ -26,7 +26,6 @@
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <plat/cpu.h>
#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>

2
arch/arm/mach-exynos/pmu.c
View File

@ -13,8 +13,6 @@
#include <linux/kernel.h>
#include <linux/bug.h>
#include <plat/cpu.h>
#include "common.h"
#include "regs-pmu.h"

1
arch/arm/mach-imx/Kconfig
View File

@ -796,7 +796,6 @@ config SOC_IMX6Q
select ARM_ERRATA_764369 if SMP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
select PINCTRL_IMX6Q
select SOC_IMX6

7
arch/arm/mach-mvebu/Kconfig
View File

@ -3,15 +3,12 @@ config ARCH_MVEBU
select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select PINCTRL
select PLAT_ORION
select MVEBU_MBUS
select ZONE_DMA if ARM_LPAE
select ARCH_REQUIRE_GPIOLIB
select MIGHT_HAVE_PCI
select PCI_QUIRKS if PCI
select OF_ADDRESS_PCI
if ARCH_MVEBU
@ -38,7 +35,6 @@ config MACH_ARMADA_375
select ARM_ERRATA_753970
select ARM_GIC
select ARMADA_375_CLK
select CPU_V7
select MACH_MVEBU_V7
select PINCTRL_ARMADA_375
help
@ -51,7 +47,6 @@ config MACH_ARMADA_38X
select ARM_ERRATA_753970
select ARM_GIC
select ARMADA_38X_CLK
select CPU_V7
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
help
@ -86,13 +81,11 @@ config MACH_KIRKWOOD
select ARCH_REQUIRE_GPIOLIB
select CPU_FEROCEON
select KIRKWOOD_CLK
select OF_IRQ
select ORION_IRQCHIP
select ORION_TIMER
select PCI
select PCI_QUIRKS
select PINCTRL_KIRKWOOD
select USE_OF
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Kirkwood device tree.

4
arch/arm/mach-omap2/board-flash.c
View File

@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void)
if (!fpga_map_addr)
return -ENOMEM;
if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
/* we dont have an DEBUG FPGA??? */
/* Depend on #defines!! default to strata boot return param */
goto unmap;
/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
/* ES2.0 SDP's onwards 4 dip switches are provided for CS */
if (omap_rev() >= OMAP3430_REV_ES1_0)

2
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View File

@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
if (!dd)
return -EINVAL;
tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
dd->div1_mask);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);

8
arch/arm/mach-omap2/clkt2xxx_osc.c
View File

@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk)
{
u32 pcc;
pcc = __raw_readl(prcm_clksrc_ctrl);
pcc = readl_relaxed(prcm_clksrc_ctrl);
__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
return 0;
}
@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk)
{
u32 pcc;
pcc = __raw_readl(prcm_clksrc_ctrl);
pcc = readl_relaxed(prcm_clksrc_ctrl);
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
}
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,

2
arch/arm/mach-omap2/clkt2xxx_sys.c
View File

@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void)
{
u32 div;
div = __raw_readl(prcm_clksrc_ctrl);
div = readl_relaxed(prcm_clksrc_ctrl);
div &= OMAP_SYSCLKDIV_MASK;
div >>= OMAP_SYSCLKDIV_SHIFT;

3
arch/arm/mach-omap2/clockdomain.h
View File

@ -18,7 +18,6 @@
#include "powerdomain.h"
#include "clock.h"
#include "omap_hwmod.h"
/*
* Clockdomain flags
@ -98,6 +97,8 @@ struct clkdm_dep {
/* Possible flags for struct clockdomain._flags */
#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0)
struct omap_hwmod;
/**
* struct clockdomain - OMAP clockdomain
* @name: clockdomain name

15
arch/arm/mach-omap2/cm2xxx.c
View File

@ -18,9 +18,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "prm2xxx.h"
#include "cm.h"
#include "cm2xxx.h"
@ -390,7 +387,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
OMAP24XX_CLKSEL_DSS2_MASK;
omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
if (cpu_is_omap2430())
if (mdm)
omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
}
@ -405,19 +402,11 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
int __init omap2xxx_cm_init(void)
{
if (!cpu_is_omap24xx())
return 0;
return cm_register(&omap2xxx_cm_ll_data);
}
static void __exit omap2xxx_cm_exit(void)
{
if (!cpu_is_omap24xx())
return;
/* Should never happen */
WARN(cm_unregister(&omap2xxx_cm_ll_data),
"%s: cm_ll_data function pointer mismatch\n", __func__);
cm_unregister(&omap2xxx_cm_ll_data);
}
__exitcall(omap2xxx_cm_exit);

4
arch/arm/mach-omap2/cm2xxx_3xxx.h
View File

@ -52,12 +52,12 @@
static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
{
return __raw_readl(cm_base + module + idx);
return readl_relaxed(cm_base + module + idx);
}
static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__raw_writel(val, cm_base + module + idx);
writel_relaxed(val, cm_base + module + idx);
}
/* Read-modify-write a register in a CM module. Caller must lock */

4
arch/arm/mach-omap2/cm33xx.c
View File

@ -50,13 +50,13 @@
/* Read a register in a CM instance */
static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
{
return __raw_readl(cm_base + inst + idx);
return readl_relaxed(cm_base + inst + idx);
}
/* Write into a register in a CM */
static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
{
__raw_writel(val, cm_base + inst + idx);
writel_relaxed(val, cm_base + inst + idx);
}
/* Read-modify-write a register in CM */

3
arch/arm/mach-omap2/cm33xx.h
View File

@ -17,11 +17,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#include "common.h"
#include "cm.h"
#include "cm-regbits-33xx.h"
#include "iomap.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000

25
arch/arm/mach-omap2/cm3xxx.c
View File

@ -18,9 +18,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "prm2xxx_3xxx.h"
#include "cm.h"
#include "cm3xxx.h"
@ -388,7 +385,8 @@ void omap3_cm_save_context(void)
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
cm_context.iva2_cm_clksel2 =
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
cm_context.cm_sysconfig =
omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
cm_context.sgx_cm_clksel =
omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
cm_context.dss_cm_clksel =
@ -418,7 +416,8 @@ void omap3_cm_save_context(void)
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
cm_context.pll_cm_clken2 =
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
cm_context.cm_polctrl =
omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
cm_context.iva2_cm_fclken =
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
cm_context.iva2_cm_clken_pll =
@ -519,7 +518,8 @@ void omap3_cm_restore_context(void)
CM_CLKSEL1);
omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
CM_CLKSEL2);
__raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
OMAP3430_CM_SYSCONFIG);
omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
CM_CLKSEL);
omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
@ -547,7 +547,8 @@ void omap3_cm_restore_context(void)
OMAP3430ES2_CM_CLKSEL5);
omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
OMAP3430ES2_CM_CLKEN2);
__raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
OMAP3430_CM_POLCTRL);
omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
CM_FCLKEN);
omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
@ -669,19 +670,11 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
int __init omap3xxx_cm_init(void)
{
if (!cpu_is_omap34xx())
return 0;
return cm_register(&omap3xxx_cm_ll_data);
}
static void __exit omap3xxx_cm_exit(void)
{
if (!cpu_is_omap34xx())
return;
/* Should never happen */
WARN(cm_unregister(&omap3xxx_cm_ll_data),
"%s: cm_ll_data function pointer mismatch\n", __func__);
cm_unregister(&omap3xxx_cm_ll_data);
}
__exitcall(omap3xxx_cm_exit);

5
arch/arm/mach-omap2/cm3xxx.h
View File

@ -29,9 +29,8 @@
* These registers appear once per CM module.
*/
#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
#define OMAP3430_CM_SYSCONFIG 0x0010
#define OMAP3430_CM_POLCTRL 0x009c
#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)

11
arch/arm/mach-omap2/cm44xx.c
View File

@ -18,35 +18,32 @@
#include <linux/err.h>
#include <linux/io.h>
#include "iomap.h"
#include "common.h"
#include "cm.h"
#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "cm-regbits-44xx.h"
/* CM1 hardware module low-level functions */
/* Read a register in CM1 */
u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
{
return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
return readl_relaxed(cm_base + inst + reg);
}
/* Write into a register in CM1 */
void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
{
__raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
writel_relaxed(val, cm_base + inst + reg);
}
/* Read a register in CM2 */
u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
{
return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
return readl_relaxed(cm2_base + inst + reg);
}
/* Write into a register in CM2 */
void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
{
__raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
writel_relaxed(val, cm2_base + inst + reg);
}

2
arch/arm/mach-omap2/cm_common.c
View File

@ -14,11 +14,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/bug.h>
#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm44xx.h"
#include "common.h"
/*
* cm_ll_data: function pointers to SoC-specific implementations of

14
arch/arm/mach-omap2/cminst44xx.c
View File

@ -21,8 +21,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "iomap.h"
#include "common.h"
#include "clockdomain.h"
#include "cm.h"
#include "cm1_44xx.h"
@ -30,12 +28,18 @@
#include "cm44xx.h"
#include "cminst44xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prcm_mpu44xx.h"
#include "prcm-common.h"
#define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_MASK (0x3 << 16)
#define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
#define OMAP4430_MODULEMODE_SHIFT 0
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
/*
* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
*
@ -116,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
return __raw_readl(_cm_bases[part] + inst + idx);
return readl_relaxed(_cm_bases[part] + inst + idx);
}
/* Write into a register in a CM instance */
@ -125,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
__raw_writel(val, _cm_bases[part] + inst + idx);
writel_relaxed(val, _cm_bases[part] + inst + idx);
}
/* Read-modify-write a register in CM1. Caller must lock */

20
arch/arm/mach-omap2/control.c
View File

@ -151,32 +151,32 @@ void __iomem *omap_ctrl_base_get(void)
u8 omap_ctrl_readb(u16 offset)
{
return __raw_readb(OMAP_CTRL_REGADDR(offset));
return readb_relaxed(OMAP_CTRL_REGADDR(offset));
}
u16 omap_ctrl_readw(u16 offset)
{
return __raw_readw(OMAP_CTRL_REGADDR(offset));
return readw_relaxed(OMAP_CTRL_REGADDR(offset));
}
u32 omap_ctrl_readl(u16 offset)
{
return __raw_readl(OMAP_CTRL_REGADDR(offset));
return readl_relaxed(OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writeb(u8 val, u16 offset)
{
__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writew(u16 val, u16 offset)
{
__raw_writew(val, OMAP_CTRL_REGADDR(offset));
writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writel(u32 val, u16 offset)
{
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
/*
@ -188,12 +188,12 @@ void omap_ctrl_writel(u32 val, u16 offset)
u32 omap4_ctrl_pad_readl(u16 offset)
{
return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
}
void omap4_ctrl_pad_writel(u32 val, u16 offset)
{
__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
}
#ifdef CONFIG_ARCH_OMAP3
@ -222,7 +222,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
*
* XXX This should use some omap_ctrl_writel()-type function
*/
__raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
}
#endif
@ -285,7 +285,7 @@ void omap3_clear_scratchpad_contents(void)
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
OMAP3430_GLOBAL_COLD_RST_MASK) {
for ( ; offset <= max_offset; offset += 0x4)
__raw_writel(0x0, (v_addr + offset));
writel_relaxed(0x0, (v_addr + offset));
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET);

4
arch/arm/mach-omap2/dma.c
View File

@ -91,7 +91,7 @@ static inline void dma_write(u32 val, int reg, int lch)
addr += reg_map[reg].offset;
addr += reg_map[reg].stride * lch;
__raw_writel(val, addr);
writel_relaxed(val, addr);
}
static inline u32 dma_read(int reg, int lch)
@ -101,7 +101,7 @@ static inline u32 dma_read(int reg, int lch)
addr += reg_map[reg].offset;
addr += reg_map[reg].stride * lch;
return __raw_readl(addr);
return readl_relaxed(addr);
}
static void omap2_clear_dma(int lch)

8
arch/arm/mach-omap2/gpmc.c
View File

@ -170,12 +170,12 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev);
static void gpmc_write_reg(int idx, u32 val)
{
__raw_writel(val, gpmc_base + idx);
writel_relaxed(val, gpmc_base + idx);
}
static u32 gpmc_read_reg(int idx)
{
return __raw_readl(gpmc_base + idx);
return readl_relaxed(gpmc_base + idx);
}
void gpmc_cs_write_reg(int cs, int idx, u32 val)
@ -183,7 +183,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
void __iomem *reg_addr;
reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
__raw_writel(val, reg_addr);
writel_relaxed(val, reg_addr);
}
static u32 gpmc_cs_read_reg(int cs, int idx)
@ -191,7 +191,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx)
void __iomem *reg_addr;
reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
return __raw_readl(reg_addr);
return readl_relaxed(reg_addr);
}
/* TODO: Add support for gpmc_fck to clock framework and use it */

2
arch/arm/mach-omap2/id.c
View File

@ -94,7 +94,7 @@ EXPORT_SYMBOL(omap_type);
#define OMAP_TAP_DIE_ID_44XX_2 0x020c
#define OMAP_TAP_DIE_ID_44XX_3 0x0210
#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
struct omap_id {
u16 hawkeye; /* Silicon type (Hawkeye id) */

4
arch/arm/mach-omap2/irq.c
View File

@ -83,12 +83,12 @@ struct omap3_intc_regs {
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
__raw_writel(val, bank->base_reg + reg);
writel_relaxed(val, bank->base_reg + reg);
}
static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
return __raw_readl(bank->base_reg + reg);
return readl_relaxed(bank->base_reg + reg);
}
/* XXX: FIQ and additional INTC support (only MPU at the moment) */

8
arch/arm/mach-omap2/mux.c
View File

@ -70,18 +70,18 @@ struct omap_mux_partition *omap_mux_get(const char *name)
u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
return __raw_readb(partition->base + reg);
return readb_relaxed(partition->base + reg);
else
return __raw_readw(partition->base + reg);
return readw_relaxed(partition->base + reg);
}
void omap_mux_write(struct omap_mux_partition *partition, u16 val,
u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
__raw_writeb(val, partition->base + reg);
writeb_relaxed(val, partition->base + reg);
else
__raw_writew(val, partition->base + reg);
writew_relaxed(val, partition->base + reg);
}
void omap_mux_write_array(struct omap_mux_partition *partition,

4
arch/arm/mach-omap2/omap-hotplug.c
View File

@ -39,7 +39,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
pr_err("Secure clear status failed\n");
} else {
__raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0);
}
@ -53,7 +53,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
boot_cpu = omap_read_auxcoreboot0();
else
boot_cpu =
__raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5;
if (boot_cpu == smp_processor_id()) {
/*

18
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -116,7 +116,7 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
__raw_writel(addr, pm_info->wkup_sar_addr);
writel_relaxed(addr, pm_info->wkup_sar_addr);
}
/*
@ -141,7 +141,7 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
break;
}
__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
}
/* Helper functions for MPUSS OSWR */
@ -179,7 +179,7 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
__raw_writel(save_state, pm_info->l2x0_sar_addr);
writel_relaxed(save_state, pm_info->l2x0_sar_addr);
}
/*
@ -192,10 +192,10 @@ static void save_l2x0_context(void)
u32 val;
void __iomem *l2x0_base = omap4_get_l2cache_base();
if (l2x0_base) {
val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
writel_relaxed(val, sar_base + L2X0_AUXCTRL_OFFSET);
val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
writel_relaxed(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
}
}
#else
@ -386,9 +386,9 @@ int __init omap4_mpuss_init(void)
/* Save device type on scratchpad for low level code to use */
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
else
__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
save_l2x0_context();

6
arch/arm/mach-omap2/omap-smp.c
View File

@ -99,7 +99,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
if (omap_secure_apis_support())
omap_modify_auxcoreboot0(0x200, 0xfffffdff);
else
__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
if (!cpu1_clkdm && !cpu1_pwrdm) {
cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@ -227,8 +227,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
writel_relaxed(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
}

42
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -60,19 +60,19 @@ static unsigned int omap_secure_apis;
*/
static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
{
return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
(cpu * CPU_ENA_OFFSET) + (idx * 4));
}
static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
{
__raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
(cpu * CPU_ENA_OFFSET) + (idx * 4));
}
static inline void sar_writel(u32 val, u32 offset, u8 idx)
{
__raw_writel(val, sar_base + offset + (idx * 4));
writel_relaxed(val, sar_base + offset + (idx * 4));
}
static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
@ -231,21 +231,21 @@ static inline void omap4_irq_save_context(void)
}
/* Save AuxBoot* registers */
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
/* Save SyncReq generation logic */
val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
/* Set the Backup Bit Mask status */
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
}
@ -264,15 +264,15 @@ static inline void omap5_irq_save_context(void)
}
/* Save AuxBoot* registers */
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
/* Set the Backup Bit Mask status */
val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
}
@ -306,9 +306,9 @@ static void irq_sar_clear(void)
if (soc_is_omap54xx())
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
val = __raw_readl(sar_base + offset);
val = readl_relaxed(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + offset);
writel_relaxed(val, sar_base + offset);
}
/*

18
arch/arm/mach-omap2/omap4-common.c
View File

@ -125,25 +125,25 @@ void __init gic_init_irq(void)
void gic_dist_disable(void)
{
if (gic_dist_base_addr)
__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}
void gic_dist_enable(void)
{
if (gic_dist_base_addr)
__raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
}
bool gic_dist_disabled(void)
{
return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}
void gic_timer_retrigger(void)
{
u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
/*
@ -151,11 +151,11 @@ void gic_timer_retrigger(void)
* disabled. Ack the pending interrupt, and retrigger it.
*/
pr_warn("%s: lost localtimer interrupt\n", __func__);
__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
}
}
}

10
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -72,7 +72,7 @@
* | (../mach-omap2/omap_hwmod*) |
* +-------------------------------+
* | OMAP clock/PRCM/register fns |
* | (__raw_{read,write}l, clk*) |
* | ({read,write}l_relaxed, clk*) |
* +-------------------------------+
*
* Device drivers should not contain any OMAP-specific code or data in
@ -3230,17 +3230,17 @@ static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
{
if (oh->flags & HWMOD_16BIT_REG)
return __raw_readw(oh->_mpu_rt_va + reg_offs);
return readw_relaxed(oh->_mpu_rt_va + reg_offs);
else
return __raw_readl(oh->_mpu_rt_va + reg_offs);
return readl_relaxed(oh->_mpu_rt_va + reg_offs);
}
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
{
if (oh->flags & HWMOD_16BIT_REG)
__raw_writew(v, oh->_mpu_rt_va + reg_offs);
writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
else
__raw_writel(v, oh->_mpu_rt_va + reg_offs);
writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
}
/**

1
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -24,6 +24,7 @@
#include "prm33xx.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "common.h"
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))

6
arch/arm/mach-omap2/omap_phy_internal.c
View File

@ -57,7 +57,7 @@ static int __init omap4430_phy_power_down(void)
}
/* Power down the phy */
__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
iounmap(ctrl_base);
@ -162,7 +162,7 @@ void ti81xx_musb_phy_power(u8 on)
return;
}
usbphycfg = __raw_readl(scm_base + USBCTRL0);
usbphycfg = readl_relaxed(scm_base + USBCTRL0);
if (on) {
if (cpu_is_ti816x()) {
@ -181,7 +181,7 @@ void ti81xx_musb_phy_power(u8 on)
usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
}
__raw_writel(usbphycfg, scm_base + USBCTRL0);
writel_relaxed(usbphycfg, scm_base + USBCTRL0);
iounmap(scm_base);
}

1
arch/arm/mach-omap2/powerdomain-common.c
View File

@ -17,7 +17,6 @@
#include "pm.h"
#include "cm.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-44xx.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"

1
arch/arm/mach-omap2/powerdomain.c
View File

@ -32,6 +32,7 @@
#include "powerdomain.h"
#include "clockdomain.h"
#include "voltage.h"
#include "soc.h"
#include "pm.h"

3
arch/arm/mach-omap2/powerdomain.h
View File

@ -21,8 +21,6 @@
#include <linux/list.h>
#include <linux/spinlock.h>
#include "voltage.h"
/* Powerdomain basic power states */
#define PWRDM_POWER_OFF 0x0
#define PWRDM_POWER_RET 0x1
@ -75,6 +73,7 @@
struct clockdomain;
struct powerdomain;
struct voltagedomain;
/**
* struct powerdomain - OMAP powerdomain

24
arch/arm/mach-omap2/prcm-common.h
View File

@ -428,6 +428,28 @@
#define MAX_IOPAD_LATCH_TIME 100
# ifndef __ASSEMBLER__
#include <linux/delay.h>
/**
* omap_test_timeout - busy-loop, testing a condition
* @cond: condition to test until it evaluates to true
* @timeout: maximum number of microseconds in the timeout
* @index: loop index (integer)
*
* Loop waiting for @cond to become true or until at least @timeout
* microseconds have passed. To use, define some integer @index in the
* calling code. After running, if @index == @timeout, then the loop has
* timed out.
*/
#define omap_test_timeout(cond, timeout, index) \
({ \
for (index = 0; index < timeout; index++) { \
if (cond) \
break; \
udelay(1); \
} \
})
/**
* struct omap_prcm_irq - describes a PRCM interrupt bit
* @name: a short name describing the interrupt type, e.g. "wkup" or "io"
@ -458,6 +480,7 @@ struct omap_prcm_irq {
* @ocp_barrier: fn ptr to force buffered PRM writes to complete
* @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
* @restore_irqen: fn ptr to save and clear IRQENABLE regs
* @reconfigure_io_chain: fn ptr to reconfigure IO chain
* @saved_mask: IRQENABLE regs are saved here during suspend
* @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
* @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
@ -479,6 +502,7 @@ struct omap_prcm_irq_setup {
void (*ocp_barrier)(void);
void (*save_and_clear_irqen)(u32 *saved_mask);
void (*restore_irqen)(u32 *saved_mask);
void (*reconfigure_io_chain)(void);
u32 *saved_mask;
u32 *priority_mask;
int base_irq;

4
arch/arm/mach-omap2/prcm_mpu44xx.c
View File

@ -30,12 +30,12 @@ void __iomem *prcm_mpu_base;
u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
{
return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}
void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
{
__raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}
u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)

1
arch/arm/mach-omap2/prcm_mpu44xx.h
View File

@ -26,7 +26,6 @@
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#include "prcm_mpu_44xx_54xx.h"
#include "common.h"
#define OMAP4430_PRCM_MPU_BASE 0x48243000

10
arch/arm/mach-omap2/prm.h
View File

@ -17,10 +17,18 @@
# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int of_prcm_init(void);
# endif
/*
* prm_features flag values
*
* PRM_HAS_IO_WAKEUP: has IO wakeup capability
* PRM_HAS_VOLTAGE: has voltage domains
*/
#define PRM_HAS_IO_WAKEUP (1 << 0)
/*
* MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@ -118,6 +126,7 @@ struct prm_reset_src_map {
* @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
* @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
* @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
* @late_init: ptr to the late init function
*
* XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
* deprecated.
@ -126,6 +135,7 @@ struct prm_ll_data {
u32 (*read_reset_sources)(void);
bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
int (*late_init)(void);
};
extern int prm_register(struct prm_ll_data *pld);

13
arch/arm/mach-omap2/prm2xxx.c
View File

@ -18,9 +18,6 @@
#include <linux/io.h>
#include <linux/irq.h>
#include "soc.h"
#include "common.h"
#include "vp.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include "prm2xxx.h"
@ -201,19 +198,11 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
int __init omap2xxx_prm_init(void)
{
if (!cpu_is_omap24xx())
return 0;
return prm_register(&omap2xxx_prm_ll_data);
}
static void __exit omap2xxx_prm_exit(void)
{
if (!cpu_is_omap24xx())
return;
/* Should never happen */
WARN(prm_unregister(&omap2xxx_prm_ll_data),
"%s: prm_ll_data function pointer mismatch\n", __func__);
prm_unregister(&omap2xxx_prm_ll_data);
}
__exitcall(omap2xxx_prm_exit);

2
arch/arm/mach-omap2/prm2xxx.h
View File

@ -27,7 +27,7 @@
/*
* OMAP2-specific global PRM registers
* Use __raw_{read,write}l() with these registers.
* Use {read,write}l_relaxed() with these registers.
*
* With a few exceptions, these are the register names beginning with
* PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE

1
arch/arm/mach-omap2/prm2xxx_3xxx.c
View File

@ -16,7 +16,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "common.h"
#include "powerdomain.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"

4
arch/arm/mach-omap2/prm2xxx_3xxx.h
View File

@ -55,12 +55,12 @@
/* Power/reset management domain register get/set */
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
return __raw_readl(prm_base + module + idx);
return readl_relaxed(prm_base + module + idx);
}
static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__raw_writel(val, prm_base + module + idx);
writel_relaxed(val, prm_base + module + idx);
}
/* Read-modify-write a register in a PRM module. Caller must lock */

5
arch/arm/mach-omap2/prm33xx.c
View File

@ -19,7 +19,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "common.h"
#include "powerdomain.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
@ -27,13 +26,13 @@
/* Read a register in a PRM instance */
u32 am33xx_prm_read_reg(s16 inst, u16 idx)
{
return __raw_readl(prm_base + inst + idx);
return readl_relaxed(prm_base + inst + idx);
}
/* Write into a register in a PRM instance */
void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
{
__raw_writel(val, prm_base + inst + idx);
writel_relaxed(val, prm_base + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */

22
arch/arm/mach-omap2/prm3xxx.c
View File

@ -43,6 +43,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
.ocp_barrier = &omap3xxx_prm_ocp_barrier,
.save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
.restore_irqen = &omap3xxx_prm_restore_irqen,
.reconfigure_io_chain = &omap3xxx_prm_reconfigure_io_chain,
};
/*
@ -246,7 +247,7 @@ void omap3xxx_prm_reconfigure_io_chain(void)
*/
static void __init omap3xxx_prm_enable_io_wakeup(void)
{
if (omap3_has_io_wakeup())
if (prm_features & PRM_HAS_IO_WAKEUP)
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
PM_WKEN);
}
@ -400,23 +401,26 @@ struct pwrdm_ops omap3_pwrdm_operations = {
*
*/
static int omap3xxx_prm_late_init(void);
static struct prm_ll_data omap3xxx_prm_ll_data = {
.read_reset_sources = &omap3xxx_prm_read_reset_sources,
.late_init = &omap3xxx_prm_late_init,
};
int __init omap3xxx_prm_init(void)
{
if (!cpu_is_omap34xx())
return 0;
if (omap3_has_io_wakeup())
prm_features |= PRM_HAS_IO_WAKEUP;
return prm_register(&omap3xxx_prm_ll_data);
}
static int __init omap3xxx_prm_late_init(void)
static int omap3xxx_prm_late_init(void)
{
int ret;
if (!cpu_is_omap34xx())
if (!(prm_features & PRM_HAS_IO_WAKEUP))
return 0;
omap3xxx_prm_enable_io_wakeup();
@ -427,15 +431,9 @@ static int __init omap3xxx_prm_late_init(void)
return ret;
}
omap_subsys_initcall(omap3xxx_prm_late_init);
static void __exit omap3xxx_prm_exit(void)
{
if (!cpu_is_omap34xx())
return;
/* Should never happen */
WARN(prm_unregister(&omap3xxx_prm_ll_data),
"%s: prm_ll_data function pointer mismatch\n", __func__);
prm_unregister(&omap3xxx_prm_ll_data);
}
__exitcall(omap3xxx_prm_exit);

2
arch/arm/mach-omap2/prm3xxx.h
View File

@ -26,7 +26,7 @@
/*
* OMAP3-specific global PRM registers
* Use __raw_{read,write}l() with these registers.
* Use {read,write}l_relaxed() with these registers.
*
* With a few exceptions, these are the register names beginning with
* PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE

24
arch/arm/mach-omap2/prm44xx.c
View File

@ -47,6 +47,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
.ocp_barrier = &omap44xx_prm_ocp_barrier,
.save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
.restore_irqen = &omap44xx_prm_restore_irqen,
.reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
};
/*
@ -81,13 +82,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
/* Read a register in a CM/PRM instance in the PRM module */
u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
{
return __raw_readl(prm_base + inst + reg);
return readl_relaxed(prm_base + inst + reg);
}
/* Write into a register in a CM/PRM instance in the PRM module */
void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
{
__raw_writel(val, prm_base + inst + reg);
writel_relaxed(val, prm_base + inst + reg);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
@ -649,6 +650,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_has_voltdm = omap4_check_vcvp,
};
static int omap44xx_prm_late_init(void);
/*
* XXX document
*/
@ -656,34 +659,29 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
.read_reset_sources = &omap44xx_prm_read_reset_sources,
.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
.late_init = &omap44xx_prm_late_init,
};
int __init omap44xx_prm_init(void)
{
if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
return 0;
if (cpu_is_omap44xx())
prm_features |= PRM_HAS_IO_WAKEUP;
return prm_register(&omap44xx_prm_ll_data);
}
static int __init omap44xx_prm_late_init(void)
static int omap44xx_prm_late_init(void)
{
if (!cpu_is_omap44xx())
if (!(prm_features & PRM_HAS_IO_WAKEUP))
return 0;
omap44xx_prm_enable_io_wakeup();
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
}
omap_subsys_initcall(omap44xx_prm_late_init);
static void __exit omap44xx_prm_exit(void)
{
if (!cpu_is_omap44xx())
return;
/* Should never happen */
WARN(prm_unregister(&omap44xx_prm_ll_data),
"%s: prm_ll_data function pointer mismatch\n", __func__);
prm_unregister(&omap44xx_prm_ll_data);
}
__exitcall(omap44xx_prm_exit);

17
arch/arm/mach-omap2/prm_common.c
View File

@ -62,6 +62,8 @@ static struct omap_prcm_irq_setup *prcm_irq_setup;
/* prm_base: base virtual address of the PRM IP block */
void __iomem *prm_base;
u16 prm_features;
/*
* prm_ll_data: function pointers to SoC-specific implementations of
* common PRM functions
@ -330,12 +332,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
if (of_have_populated_dt()) {
int irq = omap_prcm_event_to_irq("io");
if (cpu_is_omap34xx())
omap_pcs_legacy_init(irq,
omap3xxx_prm_reconfigure_io_chain);
else
omap_pcs_legacy_init(irq,
omap44xx_prm_reconfigure_io_chain);
omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
}
return 0;
@ -530,3 +527,11 @@ int __init of_prcm_init(void)
return 0;
}
static int __init prm_late_init(void)
{
if (prm_ll_data->late_init)
return prm_ll_data->late_init();
return 0;
}
subsys_initcall(prm_late_init);

4
arch/arm/mach-omap2/prminst44xx.c
View File

@ -49,7 +49,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]);
return __raw_readl(_prm_bases[part] + inst + idx);
return readl_relaxed(_prm_bases[part] + inst + idx);
}
/* Write into a register in a PRM instance */
@ -58,7 +58,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]);
__raw_writel(val, _prm_bases[part] + inst + idx);
writel_relaxed(val, _prm_bases[part] + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */

8
arch/arm/mach-omap2/sdrc.h
View File

@ -31,24 +31,24 @@ extern void __iomem *omap2_sms_base;
static inline void sdrc_write_reg(u32 val, u16 reg)
{
__raw_writel(val, OMAP_SDRC_REGADDR(reg));
writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
}
static inline u32 sdrc_read_reg(u16 reg)
{
return __raw_readl(OMAP_SDRC_REGADDR(reg));
return readl_relaxed(OMAP_SDRC_REGADDR(reg));
}
/* SMS global register get/set */
static inline void sms_write_reg(u32 val, u16 reg)
{
__raw_writel(val, OMAP_SMS_REGADDR(reg));
writel_relaxed(val, OMAP_SMS_REGADDR(reg));
}
static inline u32 sms_read_reg(u16 reg)
{
return __raw_readl(OMAP_SMS_REGADDR(reg));
return readl_relaxed(OMAP_SMS_REGADDR(reg));
}
extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);

4
arch/arm/mach-omap2/sdrc2xxx.c
View File

@ -103,9 +103,9 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
* prm2xxx.c function
*/
if (cpu_is_omap2420())
__raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
else
__raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
curr_perf_level = level;
local_irq_restore(flags);

2
arch/arm/mach-omap2/sr_device.c
View File

@ -57,7 +57,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
/*
* In OMAP4 the efuse registers are 24 bit aligned.
* A __raw_readl will fail for non-32 bit aligned address
* A readl_relaxed will fail for non-32 bit aligned address
* and hence the 8-bit read and shift.
*/
if (cpu_is_omap44xx()) {

16
arch/arm/mach-omap2/sram.c
View File

@ -70,16 +70,16 @@ static int is_sram_locked(void)
if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
if (cpu_is_omap242x()) {
__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
if (cpu_is_omap34xx()) {
__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
}
return 0;
} else

8
arch/arm/mach-omap2/timer.c
View File

@ -546,15 +546,15 @@ static void __init realtime_counter_init(void)
}
/* Program numerator and denumerator registers */
reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
reg |= num;
__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
reg |= den;
__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
arch_timer_freq = (rate / den) * num;
set_cntfreq();

4
arch/arm/mach-omap2/vc.c
View File

@ -462,7 +462,7 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
OMAP4_DOWNTIME_MASK);
__raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
}
/* OMAP4 specific voltage init functions */
@ -584,7 +584,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
/* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
__raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
/* HSSCLH can always be zero */

8
arch/arm/mach-omap2/wd_timer.c
View File

@ -49,12 +49,12 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
}
/* sequence required to disable watchdog */
__raw_writel(0xAAAA, base + OMAP_WDT_SPR);
while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
cpu_relax();
__raw_writel(0x5555, base + OMAP_WDT_SPR);
while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
writel_relaxed(0x5555, base + OMAP_WDT_SPR);
while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
cpu_relax();
return 0;

34
arch/arm/mach-prima2/rstc.c
View File

@ -36,27 +36,33 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
/*
* Writing 1 to this bit resets corresponding block. Writing 0 to this
* bit de-asserts reset signal of the corresponding block.
* datasheet doesn't require explicit delay between the set and clear
* of reset bit. it could be shorter if tests pass.
* Writing 1 to this bit resets corresponding block.
* Writing 0 to this bit de-asserts reset signal of the
* corresponding block. datasheet doesn't require explicit
* delay between the set and clear of reset bit. it could
* be shorter if tests pass.
*/
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
writel(readl(sirfsoc_rstc_base +
(reset_bit / 32) * 4) | (1 << reset_bit),
sirfsoc_rstc_base + (reset_bit / 32) * 4);
msleep(10);
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
msleep(20);
writel(readl(sirfsoc_rstc_base +
(reset_bit / 32) * 4) & ~(1 << reset_bit),
sirfsoc_rstc_base + (reset_bit / 32) * 4);
} else {
/*
* For MARCO and POLO
* Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
* register de-asserts reset signal of the corresponding block.
* datasheet doesn't require explicit delay between the set and clear
* of reset bit. it could be shorter if tests pass.
* Writing 1 to SET register resets corresponding block.
* Writing 1 to CLEAR register de-asserts reset signal of the
* corresponding block.
* datasheet doesn't require explicit delay between the set and
* clear of reset bit. it could be shorter if tests pass.
*/
writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
msleep(10);
writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
writel(1 << reset_bit,
sirfsoc_rstc_base + (reset_bit / 32) * 8);
msleep(20);
writel(1 << reset_bit,
sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
}
mutex_unlock(&rstc_lock);

2
arch/arm/mach-qcom/Kconfig
View File

@ -3,8 +3,6 @@ config ARCH_QCOM
select ARCH_REQUIRE_GPIOLIB
select ARM_GIC
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
select HAVE_SMP
select QCOM_SCM if SMP
help
Support for Qualcomm's devicetree based systems.

15
arch/arm/mach-realview/core.c
View File

@ -148,6 +148,21 @@ struct platform_device realview_cf_device = {
},
};
static struct resource realview_leds_resources[] = {
{
.start = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET,
.end = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET + 4,
.flags = IORESOURCE_MEM,
},
};
struct platform_device realview_leds_device = {
.name = "versatile-leds",
.id = -1,
.num_resources = ARRAY_SIZE(realview_leds_resources),
.resource = realview_leds_resources,
};
static struct resource realview_i2c_resource = {
.start = REALVIEW_I2C_BASE,
.end = REALVIEW_I2C_BASE + SZ_4K - 1,

1
arch/arm/mach-realview/core.h
View File

@ -37,6 +37,7 @@ struct machine_desc;
extern struct platform_device realview_flash_device;
extern struct platform_device realview_cf_device;
extern struct platform_device realview_leds_device;
extern struct platform_device realview_i2c_device;
extern struct mmci_platform_data realview_mmc0_plat_data;
extern struct mmci_platform_data realview_mmc1_plat_data;

1
arch/arm/mach-realview/realview_eb.c
View File

@ -452,6 +452,7 @@ static void __init realview_eb_init(void)
realview_flash_register(&realview_eb_flash_resource, 1);
platform_device_register(&realview_i2c_device);
platform_device_register(&char_lcd_device);
platform_device_register(&realview_leds_device);
eth_device_register();
realview_usb_register(realview_eb_isp1761_resources);

1
arch/arm/mach-realview/realview_pb1176.c
View File

@ -367,6 +367,7 @@ static void __init realview_pb1176_init(void)
realview_usb_register(realview_pb1176_isp1761_resources);
platform_device_register(&pmu_device);
platform_device_register(&char_lcd_device);
platform_device_register(&realview_leds_device);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];

1
arch/arm/mach-realview/realview_pb11mp.c
View File

@ -347,6 +347,7 @@ static void __init realview_pb11mp_init(void)
realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
platform_device_register(&realview_i2c_device);
platform_device_register(&realview_cf_device);
platform_device_register(&realview_leds_device);
realview_usb_register(realview_pb11mp_isp1761_resources);
platform_device_register(&pmu_device);

1
arch/arm/mach-realview/realview_pba8.c
View File

@ -289,6 +289,7 @@ static void __init realview_pba8_init(void)
realview_eth_register(NULL, realview_pba8_smsc911x_resources);
platform_device_register(&realview_i2c_device);
platform_device_register(&realview_cf_device);
platform_device_register(&realview_leds_device);
realview_usb_register(realview_pba8_isp1761_resources);
platform_device_register(&pmu_device);

Some files were not shown because too many files have changed in this diff Show More