drm/dp: constify DP DPCD helpers
None of the DP DPCD helpers need to modify the DPCD. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -228,12 +228,12 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
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EXPORT_SYMBOL(i2c_dp_aux_add_bus);
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EXPORT_SYMBOL(i2c_dp_aux_add_bus);
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/* Helpers for DP link training */
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/* Helpers for DP link training */
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static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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{
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return link_status[r - DP_LANE0_1_STATUS];
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return link_status[r - DP_LANE0_1_STATUS];
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}
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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int lane)
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{
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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@ -242,7 +242,7 @@ static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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return (l >> s) & 0xf;
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return (l >> s) & 0xf;
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}
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}
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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int lane_count)
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{
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{
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u8 lane_align;
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u8 lane_align;
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@ -262,7 +262,7 @@ bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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}
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}
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EXPORT_SYMBOL(drm_dp_channel_eq_ok);
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EXPORT_SYMBOL(drm_dp_channel_eq_ok);
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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int lane_count)
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{
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{
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int lane;
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int lane;
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@ -277,7 +277,7 @@ bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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}
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}
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EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
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EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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int lane)
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{
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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@ -290,7 +290,7 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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}
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}
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EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
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EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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int lane)
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{
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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@ -303,7 +303,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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}
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}
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EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
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EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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udelay(100);
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udelay(100);
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else
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else
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@ -311,7 +311,7 @@ void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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}
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}
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EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
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EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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udelay(400);
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udelay(400);
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else
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else
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@ -333,20 +333,20 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
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#define DP_LINK_STATUS_SIZE 6
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#define DP_LINK_STATUS_SIZE 6
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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int lane_count);
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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int lane_count);
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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int lane);
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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int lane);
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define EDP_PSR_RECEIVER_CAP_SIZE 2
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#define EDP_PSR_RECEIVER_CAP_SIZE 2
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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u8 drm_dp_link_rate_to_bw_code(int link_rate);
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u8 drm_dp_link_rate_to_bw_code(int link_rate);
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int drm_dp_bw_code_to_link_rate(u8 link_bw);
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int drm_dp_bw_code_to_link_rate(u8 link_bw);
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@ -379,13 +379,13 @@ struct edp_vsc_psr {
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#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
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#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
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static inline int
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static inline int
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drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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{
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return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
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return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
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}
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}
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static inline u8
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static inline u8
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drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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{
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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}
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}
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