Linux 4.16-rc7
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJauCZfAAoJEHm+PkMAQRiGWGUH/2rhdQDkoJpYWnjaQkolECG8 MxpGE7nmIIHxQcbSDdHTGJ8IhVm6Z5wZ7ym/PwCDTT043Y1y341sJrIwL2/nTG6d HVidk8hFvgN6QzlzVAHT3ZZMII/V9Zt+VV5SUYLGnPAVuJNHo/6uzWlTU5g+NTFo IquFDdQUaGBlkKqby+NoAFnkV1UAIkW0g22cfvPnlO5GMer0gusGyVNvVp7TNj3C sqj4Hvt3RMDLMNe9RZ2pFTiOD096n8FWpYftZneUTxFImhRV3Jg5MaaYZm9SI3HW tXrv/LChT/F1mi5Pkx6tkT5Hr8WvcrwDMJ4It1kom10RqWAgjxIR3CMm448ileY= =YKUG -----END PGP SIGNATURE----- Merge tag 'v4.16-rc7' into x86/mm, to fix up conflict Conflicts: arch/x86/mm/init_64.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
commit
0bc91d4ba7
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@ -1,85 +1,94 @@
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What: /sys/class/ata_...
|
||||
Date: August 2008
|
||||
Contact: Gwendal Grignou<gwendal@google.com>
|
||||
Description:
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|
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Provide a place in sysfs for storing the ATA topology of the system. This allows
|
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retrieving various information about ATA objects.
|
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Provide a place in sysfs for storing the ATA topology of the
|
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system. This allows retrieving various information about ATA
|
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objects.
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Files under /sys/class/ata_port
|
||||
-------------------------------
|
||||
|
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For each port, a directory ataX is created where X is the ata_port_id of
|
||||
the port. The device parent is the ata host device.
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For each port, a directory ataX is created where X is the ata_port_id of the
|
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port. The device parent is the ata host device.
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idle_irq (read)
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Number of IRQ received by the port while idle [some ata HBA only].
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What: /sys/class/ata_port/ataX/nr_pmp_links
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What: /sys/class/ata_port/ataX/idle_irq
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Date: May, 2010
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KernelVersion: v2.6.37
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Contact: Gwendal Grignou <gwendal@chromium.org>
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Description:
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nr_pmp_links: (RO) If a SATA Port Multiplier (PM) is
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connected, the number of links behind it.
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nr_pmp_links (read)
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idle_irq: (RO) Number of IRQ received by the port while
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idle [some ata HBA only].
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If a SATA Port Multiplier (PM) is connected, number of link behind it.
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What: /sys/class/ata_port/ataX/port_no
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Date: May, 2013
|
||||
KernelVersion: v3.11
|
||||
Contact: Gwendal Grignou <gwendal@chromium.org>
|
||||
Description:
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(RO) Host local port number. While registering host controller,
|
||||
port numbers are tracked based upon number of ports available on
|
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the controller. This attribute is needed by udev for composing
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persistent links in /dev/disk/by-path.
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Files under /sys/class/ata_link
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-------------------------------
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Behind each port, there is a ata_link. If there is a SATA PM in the
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topology, 15 ata_link objects are created.
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Behind each port, there is a ata_link. If there is a SATA PM in the topology, 15
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ata_link objects are created.
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If a link is behind a port, the directory name is linkX, where X is
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ata_port_id of the port.
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If a link is behind a PM, its name is linkX.Y where X is ata_port_id
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of the parent port and Y the PM port.
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If a link is behind a port, the directory name is linkX, where X is ata_port_id
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of the port. If a link is behind a PM, its name is linkX.Y where X is
|
||||
ata_port_id of the parent port and Y the PM port.
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hw_sata_spd_limit
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|
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Maximum speed supported by the connected SATA device.
|
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What: /sys/class/ata_link/linkX[.Y]/hw_sata_spd_limit
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What: /sys/class/ata_link/linkX[.Y]/sata_spd_limit
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What: /sys/class/ata_link/linkX[.Y]/sata_spd
|
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Date: May, 2010
|
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KernelVersion: v2.6.37
|
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Contact: Gwendal Grignou <gwendal@chromium.org>
|
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Description:
|
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hw_sata_spd_limit: (RO) Maximum speed supported by the
|
||||
connected SATA device.
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sata_spd_limit
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sata_spd_limit: (RO) Maximum speed imposed by libata.
|
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|
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Maximum speed imposed by libata.
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sata_spd: (RO) Current speed of the link
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eg. 1.5, 3 Gbps etc.
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|
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sata_spd
|
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|
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Current speed of the link [1.5, 3Gps,...].
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|
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Files under /sys/class/ata_device
|
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---------------------------------
|
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|
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Behind each link, up to two ata device are created.
|
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The name of the directory is devX[.Y].Z where:
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- X is ata_port_id of the port where the device is connected,
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- Y the port of the PM if any, and
|
||||
- Z the device id: for PATA, there is usually 2 devices [0,1],
|
||||
only 1 for SATA.
|
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Behind each link, up to two ata devices are created.
|
||||
The name of the directory is devX[.Y].Z where:
|
||||
- X is ata_port_id of the port where the device is connected,
|
||||
- Y the port of the PM if any, and
|
||||
- Z the device id: for PATA, there is usually 2 devices [0,1], only 1 for SATA.
|
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|
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class
|
||||
Device class. Can be "ata" for disk, "atapi" for packet device,
|
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"pmp" for PM, or "none" if no device was found behind the link.
|
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|
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dma_mode
|
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What: /sys/class/ata_device/devX[.Y].Z/spdn_cnt
|
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What: /sys/class/ata_device/devX[.Y].Z/gscr
|
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What: /sys/class/ata_device/devX[.Y].Z/ering
|
||||
What: /sys/class/ata_device/devX[.Y].Z/id
|
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What: /sys/class/ata_device/devX[.Y].Z/pio_mode
|
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What: /sys/class/ata_device/devX[.Y].Z/xfer_mode
|
||||
What: /sys/class/ata_device/devX[.Y].Z/dma_mode
|
||||
What: /sys/class/ata_device/devX[.Y].Z/class
|
||||
Date: May, 2010
|
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KernelVersion: v2.6.37
|
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Contact: Gwendal Grignou <gwendal@chromium.org>
|
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Description:
|
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spdn_cnt: (RO) Number of times libata decided to lower the
|
||||
speed of link due to errors.
|
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|
||||
Transfer modes supported by the device when in DMA mode.
|
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Mostly used by PATA device.
|
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gscr: (RO) Cached result of the dump of PM GSCR
|
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register. Valid registers are:
|
||||
|
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pio_mode
|
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|
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Transfer modes supported by the device when in PIO mode.
|
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Mostly used by PATA device.
|
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|
||||
xfer_mode
|
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|
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Current transfer mode.
|
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|
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id
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|
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Cached result of IDENTIFY command, as described in ATA8 7.16 and 7.17.
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Only valid if the device is not a PM.
|
||||
|
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gscr
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Cached result of the dump of PM GSCR register.
|
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Valid registers are:
|
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0: SATA_PMP_GSCR_PROD_ID,
|
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1: SATA_PMP_GSCR_REV,
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2: SATA_PMP_GSCR_PORT_INFO,
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|
@ -88,23 +97,43 @@ gscr
|
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64: SATA_PMP_GSCR_FEAT,
|
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96: SATA_PMP_GSCR_FEAT_EN,
|
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130: SATA_PMP_GSCR_SII_GPIO
|
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|
||||
Only valid if the device is a PM.
|
||||
|
||||
trim
|
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ering: (RO) Formatted output of the error ring of the
|
||||
device.
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|
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Shows the DSM TRIM mode currently used by the device. Valid
|
||||
id: (RO) Cached result of IDENTIFY command, as
|
||||
described in ATA8 7.16 and 7.17. Only valid if
|
||||
the device is not a PM.
|
||||
|
||||
pio_mode: (RO) Transfer modes supported by the device when
|
||||
in PIO mode. Mostly used by PATA device.
|
||||
|
||||
xfer_mode: (RO) Current transfer mode
|
||||
|
||||
dma_mode: (RO) Transfer modes supported by the device when
|
||||
in DMA mode. Mostly used by PATA device.
|
||||
|
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class: (RO) Device class. Can be "ata" for disk,
|
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"atapi" for packet device, "pmp" for PM, or
|
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"none" if no device was found behind the link.
|
||||
|
||||
|
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What: /sys/class/ata_device/devX[.Y].Z/trim
|
||||
Date: May, 2015
|
||||
KernelVersion: v4.10
|
||||
Contact: Gwendal Grignou <gwendal@chromium.org>
|
||||
Description:
|
||||
(RO) Shows the DSM TRIM mode currently used by the device. Valid
|
||||
values are:
|
||||
|
||||
unsupported: Drive does not support DSM TRIM
|
||||
|
||||
unqueued: Drive supports unqueued DSM TRIM only
|
||||
|
||||
queued: Drive supports queued DSM TRIM
|
||||
forced_unqueued: Drive's queued DSM support is known to be
|
||||
buggy and only unqueued TRIM commands
|
||||
|
||||
forced_unqueued: Drive's queued DSM support is known to
|
||||
be buggy and only unqueued TRIM commands
|
||||
are sent
|
||||
|
||||
spdn_cnt
|
||||
|
||||
Number of time libata decided to lower the speed of link due to errors.
|
||||
|
||||
ering
|
||||
|
||||
Formatted output of the error ring of the device.
|
||||
|
|
|
@ -0,0 +1,58 @@
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|||
What: /sys/block/*/device/sw_activity
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Date: Jun, 2008
|
||||
KernelVersion: v2.6.27
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
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(RW) Used by drivers which support software controlled activity
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LEDs.
|
||||
|
||||
It has the following valid values:
|
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0 OFF - the LED is not activated on activity
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1 BLINK_ON - the LED blinks on every 10ms when activity is
|
||||
detected.
|
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2 BLINK_OFF - the LED is on when idle, and blinks off
|
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every 10ms when activity is detected.
|
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|
||||
Note that the user must turn sw_activity OFF it they wish to
|
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control the activity LED via the em_message file.
|
||||
|
||||
|
||||
What: /sys/block/*/device/unload_heads
|
||||
Date: Sep, 2008
|
||||
KernelVersion: v2.6.28
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
(RW) Hard disk shock protection
|
||||
|
||||
Writing an integer value to this file will take the heads of the
|
||||
respective drive off the platter and block all I/O operations
|
||||
for the specified number of milliseconds.
|
||||
|
||||
- If the device does not support the unload heads feature,
|
||||
access is denied with -EOPNOTSUPP.
|
||||
- The maximal value accepted for a timeout is 30000
|
||||
milliseconds.
|
||||
- A previously set timeout can be cancelled and disk can resume
|
||||
normal operation immediately by specifying a timeout of 0.
|
||||
- Some hard drives only comply with an earlier version of the
|
||||
ATA standard, but support the unload feature nonetheless.
|
||||
There is no safe way Linux can detect these devices, so this
|
||||
is not enabled by default. If it is known that your device
|
||||
does support the unload feature, then you can tell the kernel
|
||||
to enable it by writing -1. It can be disabled again by
|
||||
writing -2.
|
||||
- Values below -2 are rejected with -EINVAL
|
||||
|
||||
For more information, see
|
||||
Documentation/laptops/disk-shock-protection.txt
|
||||
|
||||
|
||||
What: /sys/block/*/device/ncq_prio_enable
|
||||
Date: Oct, 2016
|
||||
KernelVersion: v4.10
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
(RW) Write to the file to turn on or off the SATA ncq (native
|
||||
command queueing) support. By default this feature is turned
|
||||
off.
|
|
@ -27,3 +27,92 @@ Description: This file contains the current status of the "SSD Smart Path"
|
|||
the direct i/o path to physical devices. This setting is
|
||||
controller wide, affecting all configured logical drives on the
|
||||
controller. This file is readable and writable.
|
||||
|
||||
What: /sys/class/scsi_host/hostX/link_power_management_policy
|
||||
Date: Oct, 2007
|
||||
KernelVersion: v2.6.24
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
(RW) This parameter allows the user to read and set the link
|
||||
(interface) power management.
|
||||
|
||||
There are four possible options:
|
||||
|
||||
min_power: Tell the controller to try to make the link use the
|
||||
least possible power when possible. This may sacrifice some
|
||||
performance due to increased latency when coming out of lower
|
||||
power states.
|
||||
|
||||
max_performance: Generally, this means no power management.
|
||||
Tell the controller to have performance be a priority over power
|
||||
management.
|
||||
|
||||
medium_power: Tell the controller to enter a lower power state
|
||||
when possible, but do not enter the lowest power state, thus
|
||||
improving latency over min_power setting.
|
||||
|
||||
med_power_with_dipm: Identical to the existing medium_power
|
||||
setting except that it enables dipm (device initiated power
|
||||
management) on top, which makes it match the Windows IRST (Intel
|
||||
Rapid Storage Technology) driver settings. This setting is also
|
||||
close to min_power, except that:
|
||||
a) It does not use host-initiated slumber mode, but it does
|
||||
allow device-initiated slumber
|
||||
b) It does not enable low power device sleep mode (DevSlp).
|
||||
|
||||
What: /sys/class/scsi_host/hostX/em_message
|
||||
What: /sys/class/scsi_host/hostX/em_message_type
|
||||
Date: Jun, 2008
|
||||
KernelVersion: v2.6.27
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
em_message: (RW) Enclosure management support. For the LED
|
||||
protocol, writes and reads correspond to the LED message format
|
||||
as defined in the AHCI spec.
|
||||
|
||||
The user must turn sw_activity (under /sys/block/*/device/) OFF
|
||||
it they wish to control the activity LED via the em_message
|
||||
file.
|
||||
|
||||
em_message_type: (RO) Displays the current enclosure management
|
||||
protocol that is being used by the driver (for eg. LED, SAF-TE,
|
||||
SES-2, SGPIO etc).
|
||||
|
||||
What: /sys/class/scsi_host/hostX/ahci_port_cmd
|
||||
What: /sys/class/scsi_host/hostX/ahci_host_caps
|
||||
What: /sys/class/scsi_host/hostX/ahci_host_cap2
|
||||
Date: Mar, 2010
|
||||
KernelVersion: v2.6.35
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
[to be documented]
|
||||
|
||||
What: /sys/class/scsi_host/hostX/ahci_host_version
|
||||
Date: Mar, 2010
|
||||
KernelVersion: v2.6.35
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
(RO) Display the version of the AHCI spec implemented by the
|
||||
host.
|
||||
|
||||
What: /sys/class/scsi_host/hostX/em_buffer
|
||||
Date: Apr, 2010
|
||||
KernelVersion: v2.6.35
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
(RW) Allows access to AHCI EM (enclosure management) buffer
|
||||
directly if the host supports EM.
|
||||
|
||||
For eg. the AHCI driver supports SGPIO EM messages but the
|
||||
SATA/AHCI specs do not define the SGPIO message format of the EM
|
||||
buffer. Different hardware(HW) vendors may have different
|
||||
definitions. With the em_buffer attribute, this issue can be
|
||||
solved by allowing HW vendors to provide userland drivers and
|
||||
tools for their SGPIO initiators.
|
||||
|
||||
What: /sys/class/scsi_host/hostX/em_message_supported
|
||||
Date: Oct, 2009
|
||||
KernelVersion: v2.6.39
|
||||
Contact: linux-ide@vger.kernel.org
|
||||
Description:
|
||||
(RO) Displays supported enclosure management message types.
|
||||
|
|
|
@ -16,6 +16,7 @@ Required properties:
|
|||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
- #sound-dai-cells: should be 0.
|
||||
|
||||
Required properties for Exynos 4210, 4212, 5420 and 5433:
|
||||
- clocks: list of clock IDs from SoC clock driver.
|
||||
|
|
|
@ -3,11 +3,11 @@ Device-Tree bindings for sigma delta modulator
|
|||
Required properties:
|
||||
- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use
|
||||
as a generic SD modulator if modulator not specified in compatible list.
|
||||
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
|
||||
- #io-channel-cells = <0>: See the IIO bindings section "IIO consumers".
|
||||
|
||||
Example node:
|
||||
|
||||
ads1202: adc@0 {
|
||||
compatible = "sd-modulator";
|
||||
#io-channel-cells = <1>;
|
||||
#io-channel-cells = <0>;
|
||||
};
|
||||
|
|
|
@ -50,7 +50,7 @@ Example:
|
|||
compatible = "marvell,mv88e6085";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -61,6 +61,7 @@ Example:
|
|||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
|
@ -74,7 +75,7 @@ Example:
|
|||
compatible = "marvell,mv88e6390";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -94,3 +95,4 @@ Example:
|
|||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -27,7 +27,11 @@ Required properties:
|
|||
SoC-specific version corresponding to the platform first followed by
|
||||
the generic version.
|
||||
|
||||
- reg: offset and length of (1) the register block and (2) the stream buffer.
|
||||
- reg: Offset and length of (1) the register block and (2) the stream buffer.
|
||||
The region for the register block is mandatory.
|
||||
The region for the stream buffer is optional, as it is only present on
|
||||
R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796),
|
||||
and M3-N (R8A77965).
|
||||
- interrupts: A list of interrupt-specifiers, one for each entry in
|
||||
interrupt-names.
|
||||
If interrupt-names is not present, an interrupt specifier
|
||||
|
|
|
@ -19,7 +19,7 @@ Required properties:
|
|||
configured in FS mode;
|
||||
- "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
|
||||
configured in HS mode;
|
||||
- "st,stm32f7xx-hsotg": The DWC2 USB HS controller instance in STM32F7xx SoCs
|
||||
- "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs
|
||||
configured in HS mode;
|
||||
- reg : Should contain 1 register range (address and length)
|
||||
- interrupts : Should contain 1 interrupt
|
||||
|
|
|
@ -4,6 +4,7 @@ Required properties:
|
|||
- compatible: Must contain one of the following:
|
||||
- "renesas,r8a7795-usb3-peri"
|
||||
- "renesas,r8a7796-usb3-peri"
|
||||
- "renesas,r8a77965-usb3-peri"
|
||||
- "renesas,rcar-gen3-usb3-peri" for a generic R-Car Gen3 compatible
|
||||
device
|
||||
|
||||
|
|
|
@ -12,6 +12,7 @@ Required properties:
|
|||
- "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
|
||||
- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
|
||||
- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
|
||||
- "renesas,usbhs-r8a77965" for r8a77965 (R-Car M3-N) compatible device
|
||||
- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
|
||||
- "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device
|
||||
- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
|
||||
|
|
|
@ -13,6 +13,7 @@ Required properties:
|
|||
- "renesas,xhci-r8a7793" for r8a7793 SoC
|
||||
- "renesas,xhci-r8a7795" for r8a7795 SoC
|
||||
- "renesas,xhci-r8a7796" for r8a7796 SoC
|
||||
- "renesas,xhci-r8a77965" for r8a77965 SoC
|
||||
- "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 or RZ/G1 compatible
|
||||
device
|
||||
- "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device
|
||||
|
|
|
@ -20,8 +20,8 @@ TCP Segmentation Offload
|
|||
|
||||
TCP segmentation allows a device to segment a single frame into multiple
|
||||
frames with a data payload size specified in skb_shinfo()->gso_size.
|
||||
When TCP segmentation requested the bit for either SKB_GSO_TCP or
|
||||
SKB_GSO_TCP6 should be set in skb_shinfo()->gso_type and
|
||||
When TCP segmentation requested the bit for either SKB_GSO_TCPV4 or
|
||||
SKB_GSO_TCPV6 should be set in skb_shinfo()->gso_type and
|
||||
skb_shinfo()->gso_size should be set to a non-zero value.
|
||||
|
||||
TCP segmentation is dependent on support for the use of partial checksum
|
||||
|
@ -153,8 +153,18 @@ To signal this, gso_size is set to the special value GSO_BY_FRAGS.
|
|||
|
||||
Therefore, any code in the core networking stack must be aware of the
|
||||
possibility that gso_size will be GSO_BY_FRAGS and handle that case
|
||||
appropriately. (For size checks, the skb_gso_validate_*_len family of
|
||||
helpers do this automatically.)
|
||||
appropriately.
|
||||
|
||||
There are some helpers to make this easier:
|
||||
|
||||
- skb_is_gso(skb) && skb_is_gso_sctp(skb) is the best way to see if
|
||||
an skb is an SCTP GSO skb.
|
||||
|
||||
- For size checks, the skb_gso_validate_*_len family of helpers correctly
|
||||
considers GSO_BY_FRAGS.
|
||||
|
||||
- For manipulating packets, skb_increase_gso_size and skb_decrease_gso_size
|
||||
will check for GSO_BY_FRAGS and WARN if asked to manipulate these skbs.
|
||||
|
||||
This also affects drivers with the NETIF_F_FRAGLIST & NETIF_F_GSO_SCTP bits
|
||||
set. Note also that NETIF_F_GSO_SCTP is included in NETIF_F_GSO_SOFTWARE.
|
||||
|
|
11
MAINTAINERS
11
MAINTAINERS
|
@ -9925,6 +9925,13 @@ F: Documentation/ABI/stable/sysfs-bus-nvmem
|
|||
F: include/linux/nvmem-consumer.h
|
||||
F: include/linux/nvmem-provider.h
|
||||
|
||||
NXP SGTL5000 DRIVER
|
||||
M: Fabio Estevam <fabio.estevam@nxp.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/sound/sgtl5000.txt
|
||||
F: sound/soc/codecs/sgtl5000*
|
||||
|
||||
NXP TDA998X DRM DRIVER
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Supported
|
||||
|
@ -10327,7 +10334,7 @@ F: drivers/oprofile/
|
|||
F: include/linux/oprofile.h
|
||||
|
||||
ORACLE CLUSTER FILESYSTEM 2 (OCFS2)
|
||||
M: Mark Fasheh <mfasheh@versity.com>
|
||||
M: Mark Fasheh <mark@fasheh.com>
|
||||
M: Joel Becker <jlbec@evilplan.org>
|
||||
L: ocfs2-devel@oss.oracle.com (moderated for non-subscribers)
|
||||
W: http://ocfs2.wiki.kernel.org
|
||||
|
@ -10837,6 +10844,7 @@ F: drivers/platform/x86/peaq-wmi.c
|
|||
PER-CPU MEMORY ALLOCATOR
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
M: Christoph Lameter <cl@linux.com>
|
||||
M: Dennis Zhou <dennisszhou@gmail.com>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu.git
|
||||
S: Maintained
|
||||
F: include/linux/percpu*.h
|
||||
|
@ -12107,6 +12115,7 @@ M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: sound/soc/samsung/
|
||||
F: Documentation/devicetree/bindings/sound/samsung*
|
||||
|
||||
SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
|
11
Makefile
11
Makefile
|
@ -2,7 +2,7 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 16
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Fearless Coyote
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -826,6 +826,15 @@ KBUILD_CFLAGS += $(call cc-disable-warning, pointer-sign)
|
|||
# disable invalid "can't wrap" optimizations for signed / pointers
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow)
|
||||
|
||||
# clang sets -fmerge-all-constants by default as optimization, but this
|
||||
# is non-conforming behavior for C and in fact breaks the kernel, so we
|
||||
# need to disable it here generally.
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-merge-all-constants)
|
||||
|
||||
# for gcc -fno-merge-all-constants disables everything, but it is fine
|
||||
# to have actual conforming behavior enabled.
|
||||
KBUILD_CFLAGS += $(call cc-option,-fmerge-constants)
|
||||
|
||||
# Make sure -fstack-check isn't enabled (like gentoo apparently did)
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-stack-check,)
|
||||
|
||||
|
|
|
@ -363,8 +363,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
|
|||
{
|
||||
int ret = 0;
|
||||
|
||||
vcpu_load(vcpu);
|
||||
|
||||
trace_kvm_set_guest_debug(vcpu, dbg->control);
|
||||
|
||||
if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
|
||||
|
@ -386,7 +384,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
|
|||
}
|
||||
|
||||
out:
|
||||
vcpu_put(vcpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -972,3 +972,13 @@ int pmd_clear_huge(pmd_t *pmdp)
|
|||
pmd_clear(pmdp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int pud_free_pmd_page(pud_t *pud)
|
||||
{
|
||||
return pud_none(*pud);
|
||||
}
|
||||
|
||||
int pmd_free_pte_page(pmd_t *pmd)
|
||||
{
|
||||
return pmd_none(*pmd);
|
||||
}
|
||||
|
|
|
@ -2,7 +2,6 @@
|
|||
#ifndef __H8300_BYTEORDER_H__
|
||||
#define __H8300_BYTEORDER_H__
|
||||
|
||||
#define __BIG_ENDIAN __ORDER_BIG_ENDIAN__
|
||||
#include <linux/byteorder/big_endian.h>
|
||||
|
||||
#endif
|
||||
|
|
|
@ -24,6 +24,7 @@ config MICROBLAZE
|
|||
select HAVE_FTRACE_MCOUNT_RECORD
|
||||
select HAVE_FUNCTION_GRAPH_TRACER
|
||||
select HAVE_FUNCTION_TRACER
|
||||
select NO_BOOTMEM
|
||||
select HAVE_MEMBLOCK
|
||||
select HAVE_MEMBLOCK_NODE_MAP
|
||||
select HAVE_OPROFILE
|
||||
|
|
|
@ -8,7 +8,6 @@ menu "Platform options"
|
|||
|
||||
config OPT_LIB_FUNCTION
|
||||
bool "Optimalized lib function"
|
||||
depends on CPU_LITTLE_ENDIAN
|
||||
default y
|
||||
help
|
||||
Allows turn on optimalized library function (memcpy and memmove).
|
||||
|
@ -21,6 +20,7 @@ config OPT_LIB_FUNCTION
|
|||
config OPT_LIB_ASM
|
||||
bool "Optimalized lib function ASM"
|
||||
depends on OPT_LIB_FUNCTION && (XILINX_MICROBLAZE0_USE_BARREL = 1)
|
||||
depends on CPU_BIG_ENDIAN
|
||||
default n
|
||||
help
|
||||
Allows turn on optimalized library function (memcpy and memmove).
|
||||
|
|
|
@ -44,7 +44,6 @@ void machine_shutdown(void);
|
|||
void machine_halt(void);
|
||||
void machine_power_off(void);
|
||||
|
||||
extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
|
||||
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
|
||||
|
||||
# endif /* __ASSEMBLY__ */
|
||||
|
|
|
@ -29,10 +29,6 @@
|
|||
* between mem locations with size of xfer spec'd in bytes
|
||||
*/
|
||||
|
||||
#ifdef __MICROBLAZEEL__
|
||||
#error Microblaze LE not support ASM optimized lib func. Disable OPT_LIB_ASM.
|
||||
#endif
|
||||
|
||||
#include <linux/linkage.h>
|
||||
.text
|
||||
.globl memcpy
|
||||
|
|
|
@ -32,9 +32,6 @@ int mem_init_done;
|
|||
#ifndef CONFIG_MMU
|
||||
unsigned int __page_offset;
|
||||
EXPORT_SYMBOL(__page_offset);
|
||||
|
||||
#else
|
||||
static int init_bootmem_done;
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
char *klimit = _end;
|
||||
|
@ -117,7 +114,6 @@ static void __init paging_init(void)
|
|||
|
||||
void __init setup_memory(void)
|
||||
{
|
||||
unsigned long map_size;
|
||||
struct memblock_region *reg;
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
|
@ -174,17 +170,6 @@ void __init setup_memory(void)
|
|||
pr_info("%s: max_low_pfn: %#lx\n", __func__, max_low_pfn);
|
||||
pr_info("%s: max_pfn: %#lx\n", __func__, max_pfn);
|
||||
|
||||
/*
|
||||
* Find an area to use for the bootmem bitmap.
|
||||
* We look for the first area which is at least
|
||||
* 128kB in length (128kB is enough for a bitmap
|
||||
* for 4GB of memory, using 4kB pages), plus 1 page
|
||||
* (in case the address isn't page-aligned).
|
||||
*/
|
||||
map_size = init_bootmem_node(NODE_DATA(0),
|
||||
PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
|
||||
memblock_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
|
||||
|
||||
/* Add active regions with valid PFNs */
|
||||
for_each_memblock(memory, reg) {
|
||||
unsigned long start_pfn, end_pfn;
|
||||
|
@ -196,32 +181,9 @@ void __init setup_memory(void)
|
|||
&memblock.memory, 0);
|
||||
}
|
||||
|
||||
/* free bootmem is whole main memory */
|
||||
free_bootmem_with_active_regions(0, max_low_pfn);
|
||||
|
||||
/* reserve allocate blocks */
|
||||
for_each_memblock(reserved, reg) {
|
||||
unsigned long top = reg->base + reg->size - 1;
|
||||
|
||||
pr_debug("reserved - 0x%08x-0x%08x, %lx, %lx\n",
|
||||
(u32) reg->base, (u32) reg->size, top,
|
||||
memory_start + lowmem_size - 1);
|
||||
|
||||
if (top <= (memory_start + lowmem_size - 1)) {
|
||||
reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
|
||||
} else if (reg->base < (memory_start + lowmem_size - 1)) {
|
||||
unsigned long trunc_size = memory_start + lowmem_size -
|
||||
reg->base;
|
||||
reserve_bootmem(reg->base, trunc_size, BOOTMEM_DEFAULT);
|
||||
}
|
||||
}
|
||||
|
||||
/* XXX need to clip this if using highmem? */
|
||||
sparse_memory_present_with_active_regions(0);
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
init_bootmem_done = 1;
|
||||
#endif
|
||||
paging_init();
|
||||
}
|
||||
|
||||
|
@ -398,30 +360,16 @@ asmlinkage void __init mmu_init(void)
|
|||
/* This is only called until mem_init is done. */
|
||||
void __init *early_get_page(void)
|
||||
{
|
||||
void *p;
|
||||
if (init_bootmem_done) {
|
||||
p = alloc_bootmem_pages(PAGE_SIZE);
|
||||
} else {
|
||||
/*
|
||||
* Mem start + kernel_tlb -> here is limit
|
||||
* because of mem mapping from head.S
|
||||
*/
|
||||
p = __va(memblock_alloc_base(PAGE_SIZE, PAGE_SIZE,
|
||||
return __va(memblock_alloc_base(PAGE_SIZE, PAGE_SIZE,
|
||||
memory_start + kernel_tlb));
|
||||
}
|
||||
return p;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
void * __ref alloc_maybe_bootmem(size_t size, gfp_t mask)
|
||||
{
|
||||
if (mem_init_done)
|
||||
return kmalloc(size, mask);
|
||||
else
|
||||
return alloc_bootmem(size);
|
||||
}
|
||||
|
||||
void * __ref zalloc_maybe_bootmem(size_t size, gfp_t mask)
|
||||
{
|
||||
void *p;
|
||||
|
|
|
@ -13,6 +13,8 @@ choice
|
|||
config SOC_AMAZON_SE
|
||||
bool "Amazon SE"
|
||||
select SOC_TYPE_XWAY
|
||||
select MFD_SYSCON
|
||||
select MFD_CORE
|
||||
|
||||
config SOC_XWAY
|
||||
bool "XWAY"
|
||||
|
|
|
@ -549,9 +549,9 @@ void __init ltq_soc_init(void)
|
|||
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
|
||||
ltq_ar9_fpi_hz(), CLOCK_250M);
|
||||
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
|
||||
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
|
||||
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
|
||||
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
|
||||
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
|
||||
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
|
||||
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
|
||||
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
|
@ -560,7 +560,7 @@ void __init ltq_soc_init(void)
|
|||
} else {
|
||||
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
|
||||
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
|
||||
clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
|
||||
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
|
||||
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
|
||||
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
|
|
|
@ -170,6 +170,28 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
|
|||
u32 n1;
|
||||
u32 rev;
|
||||
|
||||
/* Early detection of CMP support */
|
||||
mips_cm_probe();
|
||||
mips_cpc_probe();
|
||||
|
||||
if (mips_cps_numiocu(0)) {
|
||||
/*
|
||||
* mips_cm_probe() wipes out bootloader
|
||||
* config for CM regions and we have to configure them
|
||||
* again. This SoC cannot talk to pamlbus devices
|
||||
* witout proper iocu region set up.
|
||||
*
|
||||
* FIXME: it would be better to do this with values
|
||||
* from DT, but we need this very early because
|
||||
* without this we cannot talk to pretty much anything
|
||||
* including serial.
|
||||
*/
|
||||
write_gcr_reg0_base(MT7621_PALMBUS_BASE);
|
||||
write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
|
||||
CM_GCR_REGn_MASK_CMTGT_IOCU0);
|
||||
__sync();
|
||||
}
|
||||
|
||||
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
|
||||
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
|
||||
|
||||
|
@ -194,26 +216,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
|
|||
|
||||
rt2880_pinmux_data = mt7621_pinmux_data;
|
||||
|
||||
/* Early detection of CMP support */
|
||||
mips_cm_probe();
|
||||
mips_cpc_probe();
|
||||
|
||||
if (mips_cps_numiocu(0)) {
|
||||
/*
|
||||
* mips_cm_probe() wipes out bootloader
|
||||
* config for CM regions and we have to configure them
|
||||
* again. This SoC cannot talk to pamlbus devices
|
||||
* witout proper iocu region set up.
|
||||
*
|
||||
* FIXME: it would be better to do this with values
|
||||
* from DT, but we need this very early because
|
||||
* without this we cannot talk to pretty much anything
|
||||
* including serial.
|
||||
*/
|
||||
write_gcr_reg0_base(MT7621_PALMBUS_BASE);
|
||||
write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
|
||||
CM_GCR_REGn_MASK_CMTGT_IOCU0);
|
||||
}
|
||||
|
||||
if (!register_cps_smp_ops())
|
||||
return;
|
||||
|
|
|
@ -96,16 +96,9 @@ static void ralink_restart(char *command)
|
|||
unreachable();
|
||||
}
|
||||
|
||||
static void ralink_halt(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
unreachable();
|
||||
}
|
||||
|
||||
static int __init mips_reboot_setup(void)
|
||||
{
|
||||
_machine_restart = ralink_restart;
|
||||
_machine_halt = ralink_halt;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -543,6 +543,7 @@ void flush_cache_mm(struct mm_struct *mm)
|
|||
rp3440, etc. So, avoid it if the mm isn't too big. */
|
||||
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
|
||||
mm_total_size(mm) >= parisc_cache_flush_threshold) {
|
||||
if (mm->context)
|
||||
flush_tlb_all();
|
||||
flush_cache_all();
|
||||
return;
|
||||
|
@ -571,6 +572,8 @@ void flush_cache_mm(struct mm_struct *mm)
|
|||
pfn = pte_pfn(*ptep);
|
||||
if (!pfn_valid(pfn))
|
||||
continue;
|
||||
if (unlikely(mm->context))
|
||||
flush_tlb_page(vma, addr);
|
||||
__flush_cache_page(vma, addr, PFN_PHYS(pfn));
|
||||
}
|
||||
}
|
||||
|
@ -579,25 +582,45 @@ void flush_cache_mm(struct mm_struct *mm)
|
|||
void flush_cache_range(struct vm_area_struct *vma,
|
||||
unsigned long start, unsigned long end)
|
||||
{
|
||||
pgd_t *pgd;
|
||||
unsigned long addr;
|
||||
|
||||
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
|
||||
end - start >= parisc_cache_flush_threshold) {
|
||||
if (vma->vm_mm->context)
|
||||
flush_tlb_range(vma, start, end);
|
||||
flush_cache_all();
|
||||
return;
|
||||
}
|
||||
|
||||
if (vma->vm_mm->context == mfsp(3)) {
|
||||
flush_user_dcache_range_asm(start, end);
|
||||
if (vma->vm_flags & VM_EXEC)
|
||||
flush_user_icache_range_asm(start, end);
|
||||
flush_tlb_range(vma, start, end);
|
||||
return;
|
||||
}
|
||||
|
||||
pgd = vma->vm_mm->pgd;
|
||||
for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
|
||||
unsigned long pfn;
|
||||
pte_t *ptep = get_ptep(pgd, addr);
|
||||
if (!ptep)
|
||||
continue;
|
||||
pfn = pte_pfn(*ptep);
|
||||
if (pfn_valid(pfn)) {
|
||||
if (unlikely(vma->vm_mm->context))
|
||||
flush_tlb_page(vma, addr);
|
||||
__flush_cache_page(vma, addr, PFN_PHYS(pfn));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
|
||||
{
|
||||
BUG_ON(!vma->vm_mm->context);
|
||||
|
||||
if (pfn_valid(pfn)) {
|
||||
if (likely(vma->vm_mm->context))
|
||||
flush_tlb_page(vma, vmaddr);
|
||||
__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
|
||||
}
|
||||
|
|
|
@ -320,7 +320,6 @@ kvm_novcpu_exit:
|
|||
stw r12, STACK_SLOT_TRAP(r1)
|
||||
bl kvmhv_commence_exit
|
||||
nop
|
||||
lwz r12, STACK_SLOT_TRAP(r1)
|
||||
b kvmhv_switch_to_host
|
||||
|
||||
/*
|
||||
|
@ -1220,6 +1219,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
|||
|
||||
secondary_too_late:
|
||||
li r12, 0
|
||||
stw r12, STACK_SLOT_TRAP(r1)
|
||||
cmpdi r4, 0
|
||||
beq 11f
|
||||
stw r12, VCPU_TRAP(r4)
|
||||
|
@ -1558,12 +1558,12 @@ mc_cont:
|
|||
3: stw r5,VCPU_SLB_MAX(r9)
|
||||
|
||||
guest_bypass:
|
||||
stw r12, STACK_SLOT_TRAP(r1)
|
||||
mr r3, r12
|
||||
/* Increment exit count, poke other threads to exit */
|
||||
bl kvmhv_commence_exit
|
||||
nop
|
||||
ld r9, HSTATE_KVM_VCPU(r13)
|
||||
lwz r12, VCPU_TRAP(r9)
|
||||
|
||||
/* Stop others sending VCPU interrupts to this physical CPU */
|
||||
li r0, -1
|
||||
|
@ -1898,6 +1898,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
|
|||
* POWER7/POWER8 guest -> host partition switch code.
|
||||
* We don't have to lock against tlbies but we do
|
||||
* have to coordinate the hardware threads.
|
||||
* Here STACK_SLOT_TRAP(r1) contains the trap number.
|
||||
*/
|
||||
kvmhv_switch_to_host:
|
||||
/* Secondary threads wait for primary to do partition switch */
|
||||
|
@ -1950,12 +1951,12 @@ BEGIN_FTR_SECTION
|
|||
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
|
||||
|
||||
/* If HMI, call kvmppc_realmode_hmi_handler() */
|
||||
lwz r12, STACK_SLOT_TRAP(r1)
|
||||
cmpwi r12, BOOK3S_INTERRUPT_HMI
|
||||
bne 27f
|
||||
bl kvmppc_realmode_hmi_handler
|
||||
nop
|
||||
cmpdi r3, 0
|
||||
li r12, BOOK3S_INTERRUPT_HMI
|
||||
/*
|
||||
* At this point kvmppc_realmode_hmi_handler may have resync-ed
|
||||
* the TB, and if it has, we must not subtract the guest timebase
|
||||
|
@ -2008,10 +2009,8 @@ BEGIN_FTR_SECTION
|
|||
lwz r8, KVM_SPLIT_DO_RESTORE(r3)
|
||||
cmpwi r8, 0
|
||||
beq 47f
|
||||
stw r12, STACK_SLOT_TRAP(r1)
|
||||
bl kvmhv_p9_restore_lpcr
|
||||
nop
|
||||
lwz r12, STACK_SLOT_TRAP(r1)
|
||||
b 48f
|
||||
47:
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
||||
|
@ -2049,6 +2048,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
|
|||
li r0, KVM_GUEST_MODE_NONE
|
||||
stb r0, HSTATE_IN_GUEST(r13)
|
||||
|
||||
lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
|
||||
ld r0, SFS+PPC_LR_STKOFF(r1)
|
||||
addi r1, r1, SFS
|
||||
mtlr r0
|
||||
|
|
|
@ -163,13 +163,10 @@ static void tlb_batch_pmd_scan(struct mm_struct *mm, unsigned long vaddr,
|
|||
pte_unmap(pte);
|
||||
}
|
||||
|
||||
void set_pmd_at(struct mm_struct *mm, unsigned long addr,
|
||||
pmd_t *pmdp, pmd_t pmd)
|
||||
|
||||
static void __set_pmd_acct(struct mm_struct *mm, unsigned long addr,
|
||||
pmd_t orig, pmd_t pmd)
|
||||
{
|
||||
pmd_t orig = *pmdp;
|
||||
|
||||
*pmdp = pmd;
|
||||
|
||||
if (mm == &init_mm)
|
||||
return;
|
||||
|
||||
|
@ -219,6 +216,15 @@ void set_pmd_at(struct mm_struct *mm, unsigned long addr,
|
|||
}
|
||||
}
|
||||
|
||||
void set_pmd_at(struct mm_struct *mm, unsigned long addr,
|
||||
pmd_t *pmdp, pmd_t pmd)
|
||||
{
|
||||
pmd_t orig = *pmdp;
|
||||
|
||||
*pmdp = pmd;
|
||||
__set_pmd_acct(mm, addr, orig, pmd);
|
||||
}
|
||||
|
||||
static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
|
||||
unsigned long address, pmd_t *pmdp, pmd_t pmd)
|
||||
{
|
||||
|
@ -227,6 +233,7 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
|
|||
do {
|
||||
old = *pmdp;
|
||||
} while (cmpxchg64(&pmdp->pmd, old.pmd, pmd.pmd) != old.pmd);
|
||||
__set_pmd_acct(vma->vm_mm, address, old, pmd);
|
||||
|
||||
return old;
|
||||
}
|
||||
|
|
|
@ -315,19 +315,6 @@ config X86_L1_CACHE_SHIFT
|
|||
default "4" if MELAN || M486 || MGEODEGX1
|
||||
default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
|
||||
|
||||
config X86_PPRO_FENCE
|
||||
bool "PentiumPro memory ordering errata workaround"
|
||||
depends on M686 || M586MMX || M586TSC || M586 || M486 || MGEODEGX1
|
||||
---help---
|
||||
Old PentiumPro multiprocessor systems had errata that could cause
|
||||
memory operations to violate the x86 ordering standard in rare cases.
|
||||
Enabling this option will attempt to work around some (but not all)
|
||||
occurrences of this problem, at the cost of much heavier spinlock and
|
||||
memory barrier operations.
|
||||
|
||||
If unsure, say n here. Even distro kernels should think twice before
|
||||
enabling this: there are few systems, and an unlikely bug.
|
||||
|
||||
config X86_F00F_BUG
|
||||
def_bool y
|
||||
depends on M586MMX || M586TSC || M586 || M486
|
||||
|
|
|
@ -223,6 +223,15 @@ KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr)
|
|||
|
||||
LDFLAGS := -m elf_$(UTS_MACHINE)
|
||||
|
||||
#
|
||||
# The 64-bit kernel must be aligned to 2MB. Pass -z max-page-size=0x200000 to
|
||||
# the linker to force 2MB page size regardless of the default page size used
|
||||
# by the linker.
|
||||
#
|
||||
ifdef CONFIG_X86_64
|
||||
LDFLAGS += $(call ld-option, -z max-page-size=0x200000)
|
||||
endif
|
||||
|
||||
# Speed up the build
|
||||
KBUILD_CFLAGS += -pipe
|
||||
# Workaround for a gcc prelease that unfortunately was shipped in a suse release
|
||||
|
|
|
@ -300,6 +300,10 @@ static void parse_elf(void *output)
|
|||
|
||||
switch (phdr->p_type) {
|
||||
case PT_LOAD:
|
||||
#ifdef CONFIG_X86_64
|
||||
if ((phdr->p_align % 0x200000) != 0)
|
||||
error("Alignment of LOAD segment isn't multiple of 2MB");
|
||||
#endif
|
||||
#ifdef CONFIG_RELOCATABLE
|
||||
dest = output;
|
||||
dest += (phdr->p_paddr - LOAD_PHYSICAL_ADDR);
|
||||
|
|
|
@ -1143,7 +1143,7 @@ apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
|
|||
#endif /* CONFIG_HYPERV */
|
||||
|
||||
idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
||||
idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
||||
idtentry int3 do_int3 has_error_code=0
|
||||
idtentry stack_segment do_stack_segment has_error_code=1
|
||||
|
||||
#ifdef CONFIG_XEN
|
||||
|
|
|
@ -5,8 +5,6 @@
|
|||
#undef CONFIG_OPTIMIZE_INLINING
|
||||
#endif
|
||||
|
||||
#undef CONFIG_X86_PPRO_FENCE
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
|
||||
/*
|
||||
|
|
|
@ -347,7 +347,7 @@ void __init set_vsyscall_pgtable_user_bits(pgd_t *root)
|
|||
set_pgd(pgd, __pgd(pgd_val(*pgd) | _PAGE_USER));
|
||||
p4d = p4d_offset(pgd, VSYSCALL_ADDR);
|
||||
#if CONFIG_PGTABLE_LEVELS >= 5
|
||||
p4d->p4d |= _PAGE_USER;
|
||||
set_p4d(p4d, __p4d(p4d_val(*p4d) | _PAGE_USER));
|
||||
#endif
|
||||
pud = pud_offset(p4d, VSYSCALL_ADDR);
|
||||
set_pud(pud, __pud(pud_val(*pud) | _PAGE_USER));
|
||||
|
|
|
@ -2118,7 +2118,8 @@ static int x86_pmu_event_init(struct perf_event *event)
|
|||
event->destroy(event);
|
||||
}
|
||||
|
||||
if (READ_ONCE(x86_pmu.attr_rdpmc))
|
||||
if (READ_ONCE(x86_pmu.attr_rdpmc) &&
|
||||
!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
|
||||
event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
|
||||
|
||||
return err;
|
||||
|
|
|
@ -2952,9 +2952,9 @@ static void intel_pebs_aliases_skl(struct perf_event *event)
|
|||
return intel_pebs_aliases_precdist(event);
|
||||
}
|
||||
|
||||
static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
|
||||
static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
|
||||
{
|
||||
unsigned long flags = x86_pmu.free_running_flags;
|
||||
unsigned long flags = x86_pmu.large_pebs_flags;
|
||||
|
||||
if (event->attr.use_clockid)
|
||||
flags &= ~PERF_SAMPLE_TIME;
|
||||
|
@ -2976,8 +2976,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
|
|||
if (!event->attr.freq) {
|
||||
event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
|
||||
if (!(event->attr.sample_type &
|
||||
~intel_pmu_free_running_flags(event)))
|
||||
event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
|
||||
~intel_pmu_large_pebs_flags(event)))
|
||||
event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
|
||||
}
|
||||
if (x86_pmu.pebs_aliases)
|
||||
x86_pmu.pebs_aliases(event);
|
||||
|
@ -3194,7 +3194,7 @@ static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
|
|||
X86_CONFIG(.event=0xc0, .umask=0x01)) {
|
||||
if (left < 128)
|
||||
left = 128;
|
||||
left &= ~0x3fu;
|
||||
left &= ~0x3fULL;
|
||||
}
|
||||
return left;
|
||||
}
|
||||
|
@ -3460,7 +3460,7 @@ static __initconst const struct x86_pmu core_pmu = {
|
|||
.event_map = intel_pmu_event_map,
|
||||
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
|
||||
.apic = 1,
|
||||
.free_running_flags = PEBS_FREERUNNING_FLAGS,
|
||||
.large_pebs_flags = LARGE_PEBS_FLAGS,
|
||||
|
||||
/*
|
||||
* Intel PMCs cannot be accessed sanely above 32-bit width,
|
||||
|
@ -3502,7 +3502,7 @@ static __initconst const struct x86_pmu intel_pmu = {
|
|||
.event_map = intel_pmu_event_map,
|
||||
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
|
||||
.apic = 1,
|
||||
.free_running_flags = PEBS_FREERUNNING_FLAGS,
|
||||
.large_pebs_flags = LARGE_PEBS_FLAGS,
|
||||
/*
|
||||
* Intel PMCs cannot be accessed sanely above 32 bit width,
|
||||
* so we install an artificial 1<<31 period regardless of
|
||||
|
|
|
@ -935,7 +935,7 @@ void intel_pmu_pebs_add(struct perf_event *event)
|
|||
bool needed_cb = pebs_needs_sched_cb(cpuc);
|
||||
|
||||
cpuc->n_pebs++;
|
||||
if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
|
||||
if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
|
||||
cpuc->n_large_pebs++;
|
||||
|
||||
pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
|
||||
|
@ -975,7 +975,7 @@ void intel_pmu_pebs_del(struct perf_event *event)
|
|||
bool needed_cb = pebs_needs_sched_cb(cpuc);
|
||||
|
||||
cpuc->n_pebs--;
|
||||
if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
|
||||
if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
|
||||
cpuc->n_large_pebs--;
|
||||
|
||||
pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
|
||||
|
@ -1530,7 +1530,7 @@ void __init intel_ds_init(void)
|
|||
x86_pmu.pebs_record_size =
|
||||
sizeof(struct pebs_record_skl);
|
||||
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
|
||||
x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
|
||||
x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
@ -3343,6 +3343,7 @@ static struct extra_reg skx_uncore_cha_extra_regs[] = {
|
|||
SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4),
|
||||
SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8),
|
||||
SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8),
|
||||
SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3),
|
||||
EVENT_EXTRA_END
|
||||
};
|
||||
|
||||
|
@ -3562,24 +3563,27 @@ static struct intel_uncore_type *skx_msr_uncores[] = {
|
|||
NULL,
|
||||
};
|
||||
|
||||
/*
|
||||
* To determine the number of CHAs, it should read bits 27:0 in the CAPID6
|
||||
* register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.
|
||||
*/
|
||||
#define SKX_CAPID6 0x9c
|
||||
#define SKX_CHA_BIT_MASK GENMASK(27, 0)
|
||||
|
||||
static int skx_count_chabox(void)
|
||||
{
|
||||
struct pci_dev *chabox_dev = NULL;
|
||||
int bus, count = 0;
|
||||
struct pci_dev *dev = NULL;
|
||||
u32 val = 0;
|
||||
|
||||
while (1) {
|
||||
chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev);
|
||||
if (!chabox_dev)
|
||||
break;
|
||||
if (count == 0)
|
||||
bus = chabox_dev->bus->number;
|
||||
if (bus != chabox_dev->bus->number)
|
||||
break;
|
||||
count++;
|
||||
}
|
||||
dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev);
|
||||
if (!dev)
|
||||
goto out;
|
||||
|
||||
pci_dev_put(chabox_dev);
|
||||
return count;
|
||||
pci_read_config_dword(dev, SKX_CAPID6, &val);
|
||||
val &= SKX_CHA_BIT_MASK;
|
||||
out:
|
||||
pci_dev_put(dev);
|
||||
return hweight32(val);
|
||||
}
|
||||
|
||||
void skx_uncore_cpu_init(void)
|
||||
|
|
|
@ -69,7 +69,7 @@ struct event_constraint {
|
|||
#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
|
||||
#define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
|
||||
#define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
|
||||
#define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */
|
||||
#define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */
|
||||
|
||||
|
||||
struct amd_nb {
|
||||
|
@ -88,7 +88,7 @@ struct amd_nb {
|
|||
* REGS_USER can be handled for events limited to ring 3.
|
||||
*
|
||||
*/
|
||||
#define PEBS_FREERUNNING_FLAGS \
|
||||
#define LARGE_PEBS_FLAGS \
|
||||
(PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
|
||||
PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
|
||||
PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
|
||||
|
@ -608,7 +608,7 @@ struct x86_pmu {
|
|||
struct event_constraint *pebs_constraints;
|
||||
void (*pebs_aliases)(struct perf_event *event);
|
||||
int max_pebs_events;
|
||||
unsigned long free_running_flags;
|
||||
unsigned long large_pebs_flags;
|
||||
|
||||
/*
|
||||
* Intel LBR
|
||||
|
|
|
@ -52,11 +52,7 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
|
|||
#define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
|
||||
"lfence", X86_FEATURE_LFENCE_RDTSC)
|
||||
|
||||
#ifdef CONFIG_X86_PPRO_FENCE
|
||||
#define dma_rmb() rmb()
|
||||
#else
|
||||
#define dma_rmb() barrier()
|
||||
#endif
|
||||
#define dma_wmb() barrier()
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
|
@ -68,30 +64,6 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
|
|||
#define __smp_wmb() barrier()
|
||||
#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
|
||||
|
||||
#if defined(CONFIG_X86_PPRO_FENCE)
|
||||
|
||||
/*
|
||||
* For this option x86 doesn't have a strong TSO memory
|
||||
* model and we should fall back to full barriers.
|
||||
*/
|
||||
|
||||
#define __smp_store_release(p, v) \
|
||||
do { \
|
||||
compiletime_assert_atomic_type(*p); \
|
||||
__smp_mb(); \
|
||||
WRITE_ONCE(*p, v); \
|
||||
} while (0)
|
||||
|
||||
#define __smp_load_acquire(p) \
|
||||
({ \
|
||||
typeof(*p) ___p1 = READ_ONCE(*p); \
|
||||
compiletime_assert_atomic_type(*p); \
|
||||
__smp_mb(); \
|
||||
___p1; \
|
||||
})
|
||||
|
||||
#else /* regular x86 TSO memory ordering */
|
||||
|
||||
#define __smp_store_release(p, v) \
|
||||
do { \
|
||||
compiletime_assert_atomic_type(*p); \
|
||||
|
@ -107,8 +79,6 @@ do { \
|
|||
___p1; \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
/* Atomic operations are already serializing on x86 */
|
||||
#define __smp_mb__before_atomic() barrier()
|
||||
#define __smp_mb__after_atomic() barrier()
|
||||
|
|
|
@ -232,21 +232,6 @@ extern void set_iounmap_nonlazy(void);
|
|||
*/
|
||||
#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
|
||||
|
||||
/*
|
||||
* Cache management
|
||||
*
|
||||
* This needed for two cases
|
||||
* 1. Out of order aware processors
|
||||
* 2. Accidentally out of order processors (PPro errata #51)
|
||||
*/
|
||||
|
||||
static inline void flush_write_buffers(void)
|
||||
{
|
||||
#if defined(CONFIG_X86_PPRO_FENCE)
|
||||
asm volatile("lock; addl $0,0(%%esp)": : :"memory");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
extern void native_io_delay(void);
|
||||
|
|
|
@ -39,6 +39,7 @@ struct device;
|
|||
|
||||
enum ucode_state {
|
||||
UCODE_OK = 0,
|
||||
UCODE_NEW,
|
||||
UCODE_UPDATED,
|
||||
UCODE_NFOUND,
|
||||
UCODE_ERROR,
|
||||
|
|
|
@ -183,7 +183,10 @@
|
|||
* otherwise we'll run out of registers. We don't care about CET
|
||||
* here, anyway.
|
||||
*/
|
||||
# define CALL_NOSPEC ALTERNATIVE("call *%[thunk_target]\n", \
|
||||
# define CALL_NOSPEC \
|
||||
ALTERNATIVE( \
|
||||
ANNOTATE_RETPOLINE_SAFE \
|
||||
"call *%[thunk_target]\n", \
|
||||
" jmp 904f;\n" \
|
||||
" .align 16\n" \
|
||||
"901: call 903f;\n" \
|
||||
|
|
|
@ -352,6 +352,7 @@ enum vmcs_field {
|
|||
#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
|
||||
#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
|
||||
#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
|
||||
#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
|
||||
#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
|
||||
|
||||
/* GUEST_INTERRUPTIBILITY_INFO flags. */
|
||||
|
|
|
@ -105,7 +105,7 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
|
|||
/*
|
||||
* Early microcode releases for the Spectre v2 mitigation were broken.
|
||||
* Information taken from;
|
||||
* - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf
|
||||
* - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
|
||||
* - https://kb.vmware.com/s/article/52345
|
||||
* - Microcode revisions observed in the wild
|
||||
* - Release note from 20180108 microcode release
|
||||
|
@ -123,7 +123,6 @@ static const struct sku_microcode spectre_bad_microcodes[] = {
|
|||
{ INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
|
||||
{ INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
|
||||
{ INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
|
||||
{ INTEL_FAM6_SKYLAKE_DESKTOP, 0x03, 0xc2 },
|
||||
{ INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
|
||||
{ INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
|
||||
{ INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
|
||||
|
|
|
@ -339,7 +339,7 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
|
|||
return -EINVAL;
|
||||
|
||||
ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);
|
||||
if (ret != UCODE_OK)
|
||||
if (ret > UCODE_UPDATED)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
|
@ -683,27 +683,35 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
|
|||
static enum ucode_state
|
||||
load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
|
||||
{
|
||||
struct ucode_patch *p;
|
||||
enum ucode_state ret;
|
||||
|
||||
/* free old equiv table */
|
||||
free_equiv_cpu_table();
|
||||
|
||||
ret = __load_microcode_amd(family, data, size);
|
||||
|
||||
if (ret != UCODE_OK)
|
||||
if (ret != UCODE_OK) {
|
||||
cleanup();
|
||||
return ret;
|
||||
}
|
||||
|
||||
p = find_patch(0);
|
||||
if (!p) {
|
||||
return ret;
|
||||
} else {
|
||||
if (boot_cpu_data.microcode == p->patch_id)
|
||||
return ret;
|
||||
|
||||
ret = UCODE_NEW;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
/* save BSP's matching patch for early load */
|
||||
if (save) {
|
||||
struct ucode_patch *p = find_patch(0);
|
||||
if (p) {
|
||||
if (!save)
|
||||
return ret;
|
||||
|
||||
memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
|
||||
memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
|
||||
PATCH_MAX_SIZE));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -517,7 +517,29 @@ static int check_online_cpus(void)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static atomic_t late_cpus;
|
||||
static atomic_t late_cpus_in;
|
||||
static atomic_t late_cpus_out;
|
||||
|
||||
static int __wait_for_cpus(atomic_t *t, long long timeout)
|
||||
{
|
||||
int all_cpus = num_online_cpus();
|
||||
|
||||
atomic_inc(t);
|
||||
|
||||
while (atomic_read(t) < all_cpus) {
|
||||
if (timeout < SPINUNIT) {
|
||||
pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n",
|
||||
all_cpus - atomic_read(t));
|
||||
return 1;
|
||||
}
|
||||
|
||||
ndelay(SPINUNIT);
|
||||
timeout -= SPINUNIT;
|
||||
|
||||
touch_nmi_watchdog();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns:
|
||||
|
@ -527,30 +549,16 @@ static atomic_t late_cpus;
|
|||
*/
|
||||
static int __reload_late(void *info)
|
||||
{
|
||||
unsigned int timeout = NSEC_PER_SEC;
|
||||
int all_cpus = num_online_cpus();
|
||||
int cpu = smp_processor_id();
|
||||
enum ucode_state err;
|
||||
int ret = 0;
|
||||
|
||||
atomic_dec(&late_cpus);
|
||||
|
||||
/*
|
||||
* Wait for all CPUs to arrive. A load will not be attempted unless all
|
||||
* CPUs show up.
|
||||
* */
|
||||
while (atomic_read(&late_cpus)) {
|
||||
if (timeout < SPINUNIT) {
|
||||
pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n",
|
||||
atomic_read(&late_cpus));
|
||||
if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC))
|
||||
return -1;
|
||||
}
|
||||
|
||||
ndelay(SPINUNIT);
|
||||
timeout -= SPINUNIT;
|
||||
|
||||
touch_nmi_watchdog();
|
||||
}
|
||||
|
||||
spin_lock(&update_lock);
|
||||
apply_microcode_local(&err);
|
||||
|
@ -558,15 +566,22 @@ static int __reload_late(void *info)
|
|||
|
||||
if (err > UCODE_NFOUND) {
|
||||
pr_warn("Error reloading microcode on CPU %d\n", cpu);
|
||||
ret = -1;
|
||||
} else if (err == UCODE_UPDATED) {
|
||||
return -1;
|
||||
/* siblings return UCODE_OK because their engine got updated already */
|
||||
} else if (err == UCODE_UPDATED || err == UCODE_OK) {
|
||||
ret = 1;
|
||||
} else {
|
||||
return ret;
|
||||
}
|
||||
|
||||
atomic_inc(&late_cpus);
|
||||
|
||||
while (atomic_read(&late_cpus) != all_cpus)
|
||||
cpu_relax();
|
||||
/*
|
||||
* Increase the wait timeout to a safe value here since we're
|
||||
* serializing the microcode update and that could take a while on a
|
||||
* large number of CPUs. And that is fine as the *actual* timeout will
|
||||
* be determined by the last CPU finished updating and thus cut short.
|
||||
*/
|
||||
if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC * num_online_cpus()))
|
||||
panic("Timeout during microcode update!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -579,12 +594,11 @@ static int microcode_reload_late(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
atomic_set(&late_cpus, num_online_cpus());
|
||||
atomic_set(&late_cpus_in, 0);
|
||||
atomic_set(&late_cpus_out, 0);
|
||||
|
||||
ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
else if (ret > 0)
|
||||
if (ret > 0)
|
||||
microcode_check();
|
||||
|
||||
return ret;
|
||||
|
@ -607,7 +621,7 @@ static ssize_t reload_store(struct device *dev,
|
|||
return size;
|
||||
|
||||
tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true);
|
||||
if (tmp_ret != UCODE_OK)
|
||||
if (tmp_ret != UCODE_NEW)
|
||||
return size;
|
||||
|
||||
get_online_cpus();
|
||||
|
@ -691,10 +705,8 @@ static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw)
|
|||
if (system_state != SYSTEM_RUNNING)
|
||||
return UCODE_NFOUND;
|
||||
|
||||
ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev,
|
||||
refresh_fw);
|
||||
|
||||
if (ustate == UCODE_OK) {
|
||||
ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, refresh_fw);
|
||||
if (ustate == UCODE_NEW) {
|
||||
pr_debug("CPU%d updated upon init\n", cpu);
|
||||
apply_microcode_on_target(cpu);
|
||||
}
|
||||
|
|
|
@ -862,6 +862,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
|
|||
unsigned int leftover = size;
|
||||
unsigned int curr_mc_size = 0, new_mc_size = 0;
|
||||
unsigned int csig, cpf;
|
||||
enum ucode_state ret = UCODE_OK;
|
||||
|
||||
while (leftover) {
|
||||
struct microcode_header_intel mc_header;
|
||||
|
@ -903,6 +904,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
|
|||
new_mc = mc;
|
||||
new_mc_size = mc_size;
|
||||
mc = NULL; /* trigger new vmalloc */
|
||||
ret = UCODE_NEW;
|
||||
}
|
||||
|
||||
ucode_ptr += mc_size;
|
||||
|
@ -932,7 +934,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
|
|||
pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
|
||||
cpu, new_rev, uci->cpu_sig.rev);
|
||||
|
||||
return UCODE_OK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_ucode_fw(void *to, const void *from, size_t n)
|
||||
|
|
|
@ -160,7 +160,6 @@ static const __initconst struct idt_data early_pf_idts[] = {
|
|||
*/
|
||||
static const __initconst struct idt_data dbg_idts[] = {
|
||||
INTG(X86_TRAP_DB, debug),
|
||||
INTG(X86_TRAP_BP, int3),
|
||||
};
|
||||
#endif
|
||||
|
||||
|
@ -183,7 +182,6 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
|
|||
static const __initconst struct idt_data ist_idts[] = {
|
||||
ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
|
||||
ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
|
||||
SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
|
||||
ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
|
||||
#ifdef CONFIG_X86_MCE
|
||||
ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
|
||||
|
|
|
@ -37,7 +37,6 @@ static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
|
|||
WARN_ON(size == 0);
|
||||
if (!check_addr("map_single", dev, bus, size))
|
||||
return NOMMU_MAPPING_ERROR;
|
||||
flush_write_buffers();
|
||||
return bus;
|
||||
}
|
||||
|
||||
|
@ -72,25 +71,9 @@ static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
|
|||
return 0;
|
||||
s->dma_length = s->length;
|
||||
}
|
||||
flush_write_buffers();
|
||||
return nents;
|
||||
}
|
||||
|
||||
static void nommu_sync_single_for_device(struct device *dev,
|
||||
dma_addr_t addr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
flush_write_buffers();
|
||||
}
|
||||
|
||||
|
||||
static void nommu_sync_sg_for_device(struct device *dev,
|
||||
struct scatterlist *sg, int nelems,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
flush_write_buffers();
|
||||
}
|
||||
|
||||
static int nommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
||||
{
|
||||
return dma_addr == NOMMU_MAPPING_ERROR;
|
||||
|
@ -101,8 +84,6 @@ const struct dma_map_ops nommu_dma_ops = {
|
|||
.free = dma_generic_free_coherent,
|
||||
.map_sg = nommu_map_sg,
|
||||
.map_page = nommu_map_page,
|
||||
.sync_single_for_device = nommu_sync_single_for_device,
|
||||
.sync_sg_for_device = nommu_sync_sg_for_device,
|
||||
.is_phys = 1,
|
||||
.mapping_error = nommu_mapping_error,
|
||||
.dma_supported = x86_dma_supported,
|
||||
|
|
|
@ -577,7 +577,6 @@ do_general_protection(struct pt_regs *regs, long error_code)
|
|||
}
|
||||
NOKPROBE_SYMBOL(do_general_protection);
|
||||
|
||||
/* May run on IST stack. */
|
||||
dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
|
@ -592,6 +591,13 @@ dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
|
|||
if (poke_int3_handler(regs))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Use ist_enter despite the fact that we don't use an IST stack.
|
||||
* We can be called from a kprobe in non-CONTEXT_KERNEL kernel
|
||||
* mode or even during context tracking state changes.
|
||||
*
|
||||
* This means that we can't schedule. That's okay.
|
||||
*/
|
||||
ist_enter(regs);
|
||||
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
|
||||
#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
|
||||
|
@ -609,15 +615,10 @@ dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
|
|||
SIGTRAP) == NOTIFY_STOP)
|
||||
goto exit;
|
||||
|
||||
/*
|
||||
* Let others (NMI) know that the debug stack is in use
|
||||
* as we may switch to the interrupt stack.
|
||||
*/
|
||||
debug_stack_usage_inc();
|
||||
cond_local_irq_enable(regs);
|
||||
do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
|
||||
cond_local_irq_disable(regs);
|
||||
debug_stack_usage_dec();
|
||||
|
||||
exit:
|
||||
ist_exit(regs);
|
||||
}
|
||||
|
|
|
@ -727,7 +727,8 @@ void handle_vm86_fault(struct kernel_vm86_regs *regs, long error_code)
|
|||
return;
|
||||
|
||||
check_vip:
|
||||
if (VEFLAGS & X86_EFLAGS_VIP) {
|
||||
if ((VEFLAGS & (X86_EFLAGS_VIP | X86_EFLAGS_VIF)) ==
|
||||
(X86_EFLAGS_VIP | X86_EFLAGS_VIF)) {
|
||||
save_v86_state(regs, VM86_STI);
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -2770,9 +2770,11 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
|
|||
else
|
||||
pte_access &= ~ACC_WRITE_MASK;
|
||||
|
||||
spte |= (u64)pfn << PAGE_SHIFT;
|
||||
if (!kvm_is_mmio_pfn(pfn))
|
||||
spte |= shadow_me_mask;
|
||||
|
||||
spte |= (u64)pfn << PAGE_SHIFT;
|
||||
|
||||
if (pte_access & ACC_WRITE_MASK) {
|
||||
|
||||
/*
|
||||
|
|
|
@ -1045,6 +1045,13 @@ static inline bool is_machine_check(u32 intr_info)
|
|||
(INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
|
||||
}
|
||||
|
||||
/* Undocumented: icebp/int1 */
|
||||
static inline bool is_icebp(u32 intr_info)
|
||||
{
|
||||
return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
|
||||
== (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
|
||||
}
|
||||
|
||||
static inline bool cpu_has_vmx_msr_bitmap(void)
|
||||
{
|
||||
return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
|
||||
|
@ -6179,7 +6186,7 @@ static int handle_exception(struct kvm_vcpu *vcpu)
|
|||
(KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
|
||||
vcpu->arch.dr6 &= ~15;
|
||||
vcpu->arch.dr6 |= dr6 | DR6_RTM;
|
||||
if (!(dr6 & ~DR6_RESERVED)) /* icebp */
|
||||
if (is_icebp(intr_info))
|
||||
skip_emulated_instruction(vcpu);
|
||||
|
||||
kvm_queue_exception(vcpu, DB_VECTOR);
|
||||
|
|
|
@ -806,17 +806,11 @@ int arch_add_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap,
|
|||
|
||||
#define PAGE_INUSE 0xFD
|
||||
|
||||
static void __meminit free_pagetable(struct page *page, int order,
|
||||
struct vmem_altmap *altmap)
|
||||
static void __meminit free_pagetable(struct page *page, int order)
|
||||
{
|
||||
unsigned long magic;
|
||||
unsigned int nr_pages = 1 << order;
|
||||
|
||||
if (altmap) {
|
||||
vmem_altmap_free(altmap, nr_pages);
|
||||
return;
|
||||
}
|
||||
|
||||
/* bootmem page has reserved flag */
|
||||
if (PageReserved(page)) {
|
||||
__ClearPageReserved(page);
|
||||
|
@ -832,8 +826,16 @@ static void __meminit free_pagetable(struct page *page, int order,
|
|||
free_pages((unsigned long)page_address(page), order);
|
||||
}
|
||||
|
||||
static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd,
|
||||
static void __meminit free_hugepage_table(struct page *page,
|
||||
struct vmem_altmap *altmap)
|
||||
{
|
||||
if (altmap)
|
||||
vmem_altmap_free(altmap, PMD_SIZE / PAGE_SIZE);
|
||||
else
|
||||
free_pagetable(page, get_order(PMD_SIZE));
|
||||
}
|
||||
|
||||
static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd)
|
||||
{
|
||||
pte_t *pte;
|
||||
int i;
|
||||
|
@ -845,14 +847,13 @@ static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd,
|
|||
}
|
||||
|
||||
/* free a pte talbe */
|
||||
free_pagetable(pmd_page(*pmd), 0, altmap);
|
||||
free_pagetable(pmd_page(*pmd), 0);
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
pmd_clear(pmd);
|
||||
spin_unlock(&init_mm.page_table_lock);
|
||||
}
|
||||
|
||||
static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud,
|
||||
struct vmem_altmap *altmap)
|
||||
static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud)
|
||||
{
|
||||
pmd_t *pmd;
|
||||
int i;
|
||||
|
@ -864,14 +865,13 @@ static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud,
|
|||
}
|
||||
|
||||
/* free a pmd talbe */
|
||||
free_pagetable(pud_page(*pud), 0, altmap);
|
||||
free_pagetable(pud_page(*pud), 0);
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
pud_clear(pud);
|
||||
spin_unlock(&init_mm.page_table_lock);
|
||||
}
|
||||
|
||||
static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
|
||||
struct vmem_altmap *altmap)
|
||||
static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d)
|
||||
{
|
||||
pud_t *pud;
|
||||
int i;
|
||||
|
@ -883,7 +883,7 @@ static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
|
|||
}
|
||||
|
||||
/* free a pud talbe */
|
||||
free_pagetable(p4d_page(*p4d), 0, altmap);
|
||||
free_pagetable(p4d_page(*p4d), 0);
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
p4d_clear(p4d);
|
||||
spin_unlock(&init_mm.page_table_lock);
|
||||
|
@ -891,7 +891,7 @@ static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
|
|||
|
||||
static void __meminit
|
||||
remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
|
||||
struct vmem_altmap *altmap, bool direct)
|
||||
bool direct)
|
||||
{
|
||||
unsigned long next, pages = 0;
|
||||
pte_t *pte;
|
||||
|
@ -922,7 +922,7 @@ remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
|
|||
* freed when offlining, or simplely not in use.
|
||||
*/
|
||||
if (!direct)
|
||||
free_pagetable(pte_page(*pte), 0, altmap);
|
||||
free_pagetable(pte_page(*pte), 0);
|
||||
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
pte_clear(&init_mm, addr, pte);
|
||||
|
@ -945,7 +945,7 @@ remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
|
|||
|
||||
page_addr = page_address(pte_page(*pte));
|
||||
if (!memchr_inv(page_addr, PAGE_INUSE, PAGE_SIZE)) {
|
||||
free_pagetable(pte_page(*pte), 0, altmap);
|
||||
free_pagetable(pte_page(*pte), 0);
|
||||
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
pte_clear(&init_mm, addr, pte);
|
||||
|
@ -980,8 +980,7 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
|
|||
if (IS_ALIGNED(addr, PMD_SIZE) &&
|
||||
IS_ALIGNED(next, PMD_SIZE)) {
|
||||
if (!direct)
|
||||
free_pagetable(pmd_page(*pmd),
|
||||
get_order(PMD_SIZE),
|
||||
free_hugepage_table(pmd_page(*pmd),
|
||||
altmap);
|
||||
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
|
@ -995,8 +994,7 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
|
|||
page_addr = page_address(pmd_page(*pmd));
|
||||
if (!memchr_inv(page_addr, PAGE_INUSE,
|
||||
PMD_SIZE)) {
|
||||
free_pagetable(pmd_page(*pmd),
|
||||
get_order(PMD_SIZE),
|
||||
free_hugepage_table(pmd_page(*pmd),
|
||||
altmap);
|
||||
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
|
@ -1009,8 +1007,8 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
|
|||
}
|
||||
|
||||
pte_base = (pte_t *)pmd_page_vaddr(*pmd);
|
||||
remove_pte_table(pte_base, addr, next, altmap, direct);
|
||||
free_pte_table(pte_base, pmd, altmap);
|
||||
remove_pte_table(pte_base, addr, next, direct);
|
||||
free_pte_table(pte_base, pmd);
|
||||
}
|
||||
|
||||
/* Call free_pmd_table() in remove_pud_table(). */
|
||||
|
@ -1039,8 +1037,7 @@ remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
|
|||
IS_ALIGNED(next, PUD_SIZE)) {
|
||||
if (!direct)
|
||||
free_pagetable(pud_page(*pud),
|
||||
get_order(PUD_SIZE),
|
||||
altmap);
|
||||
get_order(PUD_SIZE));
|
||||
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
pud_clear(pud);
|
||||
|
@ -1054,8 +1051,7 @@ remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
|
|||
if (!memchr_inv(page_addr, PAGE_INUSE,
|
||||
PUD_SIZE)) {
|
||||
free_pagetable(pud_page(*pud),
|
||||
get_order(PUD_SIZE),
|
||||
altmap);
|
||||
get_order(PUD_SIZE));
|
||||
|
||||
spin_lock(&init_mm.page_table_lock);
|
||||
pud_clear(pud);
|
||||
|
@ -1068,7 +1064,7 @@ remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
|
|||
|
||||
pmd_base = pmd_offset(pud, 0);
|
||||
remove_pmd_table(pmd_base, addr, next, direct, altmap);
|
||||
free_pmd_table(pmd_base, pud, altmap);
|
||||
free_pmd_table(pmd_base, pud);
|
||||
}
|
||||
|
||||
if (direct)
|
||||
|
@ -1100,7 +1096,7 @@ remove_p4d_table(p4d_t *p4d_start, unsigned long addr, unsigned long end,
|
|||
* to adapt for boot-time switching between 4 and 5 level page tables.
|
||||
*/
|
||||
if (pgtable_l5_enabled)
|
||||
free_pud_table(pud_base, p4d, altmap);
|
||||
free_pud_table(pud_base, p4d);
|
||||
}
|
||||
|
||||
if (direct)
|
||||
|
|
|
@ -702,4 +702,52 @@ int pmd_clear_huge(pmd_t *pmd)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pud_free_pmd_page - Clear pud entry and free pmd page.
|
||||
* @pud: Pointer to a PUD.
|
||||
*
|
||||
* Context: The pud range has been unmaped and TLB purged.
|
||||
* Return: 1 if clearing the entry succeeded. 0 otherwise.
|
||||
*/
|
||||
int pud_free_pmd_page(pud_t *pud)
|
||||
{
|
||||
pmd_t *pmd;
|
||||
int i;
|
||||
|
||||
if (pud_none(*pud))
|
||||
return 1;
|
||||
|
||||
pmd = (pmd_t *)pud_page_vaddr(*pud);
|
||||
|
||||
for (i = 0; i < PTRS_PER_PMD; i++)
|
||||
if (!pmd_free_pte_page(&pmd[i]))
|
||||
return 0;
|
||||
|
||||
pud_clear(pud);
|
||||
free_page((unsigned long)pmd);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* pmd_free_pte_page - Clear pmd entry and free pte page.
|
||||
* @pmd: Pointer to a PMD.
|
||||
*
|
||||
* Context: The pmd range has been unmaped and TLB purged.
|
||||
* Return: 1 if clearing the entry succeeded. 0 otherwise.
|
||||
*/
|
||||
int pmd_free_pte_page(pmd_t *pmd)
|
||||
{
|
||||
pte_t *pte;
|
||||
|
||||
if (pmd_none(*pmd))
|
||||
return 1;
|
||||
|
||||
pte = (pte_t *)pmd_page_vaddr(*pmd);
|
||||
pmd_clear(pmd);
|
||||
free_page((unsigned long)pte);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
|
||||
|
|
|
@ -1188,7 +1188,7 @@ skip_init_addrs:
|
|||
* may converge on the last pass. In such case do one more
|
||||
* pass to emit the final image
|
||||
*/
|
||||
for (pass = 0; pass < 10 || image; pass++) {
|
||||
for (pass = 0; pass < 20 || image; pass++) {
|
||||
proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
|
||||
if (proglen <= 0) {
|
||||
image = NULL;
|
||||
|
@ -1215,6 +1215,7 @@ skip_init_addrs:
|
|||
}
|
||||
}
|
||||
oldproglen = proglen;
|
||||
cond_resched();
|
||||
}
|
||||
|
||||
if (bpf_jit_enable > 1)
|
||||
|
|
|
@ -229,7 +229,7 @@ int __init efi_alloc_page_tables(void)
|
|||
if (!pud) {
|
||||
if (pgtable_l5_enabled)
|
||||
free_page((unsigned long) pgd_page_vaddr(*pgd));
|
||||
free_page((unsigned long)efi_pgd);
|
||||
free_pages((unsigned long)efi_pgd, PGD_ALLOCATION_ORDER);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
|
|
@ -30,11 +30,7 @@
|
|||
|
||||
#endif /* CONFIG_X86_32 */
|
||||
|
||||
#ifdef CONFIG_X86_PPRO_FENCE
|
||||
#define dma_rmb() rmb()
|
||||
#else /* CONFIG_X86_PPRO_FENCE */
|
||||
#define dma_rmb() barrier()
|
||||
#endif /* CONFIG_X86_PPRO_FENCE */
|
||||
#define dma_wmb() barrier()
|
||||
|
||||
#include <asm-generic/barrier.h>
|
||||
|
|
|
@ -74,10 +74,10 @@ void __init acpi_watchdog_init(void)
|
|||
res.start = gas->address;
|
||||
if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
|
||||
res.flags = IORESOURCE_MEM;
|
||||
res.end = res.start + ALIGN(gas->access_width, 4);
|
||||
res.end = res.start + ALIGN(gas->access_width, 4) - 1;
|
||||
} else if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
|
||||
res.flags = IORESOURCE_IO;
|
||||
res.end = res.start + gas->access_width;
|
||||
res.end = res.start + gas->access_width - 1;
|
||||
} else {
|
||||
pr_warn("Unsupported address space: %u\n",
|
||||
gas->space_id);
|
||||
|
|
|
@ -70,7 +70,6 @@ static async_cookie_t async_cookie;
|
|||
static bool battery_driver_registered;
|
||||
static int battery_bix_broken_package;
|
||||
static int battery_notification_delay_ms;
|
||||
static int battery_full_discharging;
|
||||
static unsigned int cache_time = 1000;
|
||||
module_param(cache_time, uint, 0644);
|
||||
MODULE_PARM_DESC(cache_time, "cache time in milliseconds");
|
||||
|
@ -215,12 +214,9 @@ static int acpi_battery_get_property(struct power_supply *psy,
|
|||
return -ENODEV;
|
||||
switch (psp) {
|
||||
case POWER_SUPPLY_PROP_STATUS:
|
||||
if (battery->state & ACPI_BATTERY_STATE_DISCHARGING) {
|
||||
if (battery_full_discharging && battery->rate_now == 0)
|
||||
val->intval = POWER_SUPPLY_STATUS_FULL;
|
||||
else
|
||||
if (battery->state & ACPI_BATTERY_STATE_DISCHARGING)
|
||||
val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
|
||||
} else if (battery->state & ACPI_BATTERY_STATE_CHARGING)
|
||||
else if (battery->state & ACPI_BATTERY_STATE_CHARGING)
|
||||
val->intval = POWER_SUPPLY_STATUS_CHARGING;
|
||||
else if (acpi_battery_is_charged(battery))
|
||||
val->intval = POWER_SUPPLY_STATUS_FULL;
|
||||
|
@ -1170,12 +1166,6 @@ battery_notification_delay_quirk(const struct dmi_system_id *d)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int __init battery_full_discharging_quirk(const struct dmi_system_id *d)
|
||||
{
|
||||
battery_full_discharging = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dmi_system_id bat_dmi_table[] __initconst = {
|
||||
{
|
||||
.callback = battery_bix_broken_package_quirk,
|
||||
|
@ -1193,38 +1183,6 @@ static const struct dmi_system_id bat_dmi_table[] __initconst = {
|
|||
DMI_MATCH(DMI_PRODUCT_NAME, "Aspire V5-573G"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = battery_full_discharging_quirk,
|
||||
.ident = "ASUS GL502VSK",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "GL502VSK"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = battery_full_discharging_quirk,
|
||||
.ident = "ASUS UX305LA",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "UX305LA"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = battery_full_discharging_quirk,
|
||||
.ident = "ASUS UX360UA",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "UX360UA"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = battery_full_discharging_quirk,
|
||||
.ident = "ASUS UX410UAK",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "UX410UAK"),
|
||||
},
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -2675,10 +2675,14 @@ static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
|
|||
else
|
||||
ndr_desc->numa_node = NUMA_NO_NODE;
|
||||
|
||||
if(acpi_desc->platform_cap & ACPI_NFIT_CAPABILITY_CACHE_FLUSH)
|
||||
/*
|
||||
* Persistence domain bits are hierarchical, if
|
||||
* ACPI_NFIT_CAPABILITY_CACHE_FLUSH is set then
|
||||
* ACPI_NFIT_CAPABILITY_MEM_FLUSH is implied.
|
||||
*/
|
||||
if (acpi_desc->platform_cap & ACPI_NFIT_CAPABILITY_CACHE_FLUSH)
|
||||
set_bit(ND_REGION_PERSIST_CACHE, &ndr_desc->flags);
|
||||
|
||||
if (acpi_desc->platform_cap & ACPI_NFIT_CAPABILITY_MEM_FLUSH)
|
||||
else if (acpi_desc->platform_cap & ACPI_NFIT_CAPABILITY_MEM_FLUSH)
|
||||
set_bit(ND_REGION_PERSIST_MEMCTRL, &ndr_desc->flags);
|
||||
|
||||
list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
|
||||
|
|
|
@ -103,25 +103,27 @@ int acpi_map_pxm_to_node(int pxm)
|
|||
*/
|
||||
int acpi_map_pxm_to_online_node(int pxm)
|
||||
{
|
||||
int node, n, dist, min_dist;
|
||||
int node, min_node;
|
||||
|
||||
node = acpi_map_pxm_to_node(pxm);
|
||||
|
||||
if (node == NUMA_NO_NODE)
|
||||
node = 0;
|
||||
|
||||
min_node = node;
|
||||
if (!node_online(node)) {
|
||||
min_dist = INT_MAX;
|
||||
int min_dist = INT_MAX, dist, n;
|
||||
|
||||
for_each_online_node(n) {
|
||||
dist = node_distance(node, n);
|
||||
if (dist < min_dist) {
|
||||
min_dist = dist;
|
||||
node = n;
|
||||
min_node = n;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return node;
|
||||
return min_node;
|
||||
}
|
||||
EXPORT_SYMBOL(acpi_map_pxm_to_online_node);
|
||||
|
||||
|
|
|
@ -550,7 +550,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
|
|||
.driver_data = board_ahci_yes_fbs },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
|
||||
.driver_data = board_ahci_yes_fbs },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
|
||||
.driver_data = board_ahci_yes_fbs },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
|
||||
.driver_data = board_ahci_yes_fbs },
|
||||
|
||||
/* Promise */
|
||||
|
|
|
@ -665,6 +665,16 @@ int ahci_stop_engine(struct ata_port *ap)
|
|||
if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Don't try to issue commands but return with ENODEV if the
|
||||
* AHCI controller not available anymore (e.g. due to PCIe hot
|
||||
* unplugging). Otherwise a 500ms delay for each port is added.
|
||||
*/
|
||||
if (tmp == 0xffffffff) {
|
||||
dev_err(ap->host->dev, "AHCI controller unavailable!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* setting HBA to idle */
|
||||
tmp &= ~PORT_CMD_START;
|
||||
writel(tmp, port_mmio + PORT_CMD);
|
||||
|
|
|
@ -4530,6 +4530,25 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
|||
{ "PIONEER DVD-RW DVR-212D", NULL, ATA_HORKAGE_NOSETXFER },
|
||||
{ "PIONEER DVD-RW DVR-216D", NULL, ATA_HORKAGE_NOSETXFER },
|
||||
|
||||
/* Crucial BX100 SSD 500GB has broken LPM support */
|
||||
{ "CT500BX100SSD1", NULL, ATA_HORKAGE_NOLPM },
|
||||
|
||||
/* 512GB MX100 with MU01 firmware has both queued TRIM and LPM issues */
|
||||
{ "Crucial_CT512MX100*", "MU01", ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM |
|
||||
ATA_HORKAGE_NOLPM, },
|
||||
/* 512GB MX100 with newer firmware has only LPM issues */
|
||||
{ "Crucial_CT512MX100*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM |
|
||||
ATA_HORKAGE_NOLPM, },
|
||||
|
||||
/* 480GB+ M500 SSDs have both queued TRIM and LPM issues */
|
||||
{ "Crucial_CT480M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM |
|
||||
ATA_HORKAGE_NOLPM, },
|
||||
{ "Crucial_CT960M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM |
|
||||
ATA_HORKAGE_NOLPM, },
|
||||
|
||||
/* devices that don't properly handle queued TRIM commands */
|
||||
{ "Micron_M500_*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
|
@ -4541,7 +4560,9 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
|||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
{ "Crucial_CT*MX100*", "MU01", ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
{ "Samsung SSD 8*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
{ "Samsung SSD 840*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
{ "Samsung SSD 850*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
{ "FCCT*M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
|
@ -5401,8 +5422,7 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
|
|||
* We guarantee to LLDs that they will have at least one
|
||||
* non-zero sg if the command is a data command.
|
||||
*/
|
||||
if (WARN_ON_ONCE(ata_is_data(prot) &&
|
||||
(!qc->sg || !qc->n_elem || !qc->nbytes)))
|
||||
if (ata_is_data(prot) && (!qc->sg || !qc->n_elem || !qc->nbytes))
|
||||
goto sys_err;
|
||||
|
||||
if (ata_is_dma(prot) || (ata_is_pio(prot) &&
|
||||
|
|
|
@ -815,7 +815,8 @@ void ata_scsi_port_error_handler(struct Scsi_Host *host, struct ata_port *ap)
|
|||
|
||||
if (ap->pflags & ATA_PFLAG_LOADING)
|
||||
ap->pflags &= ~ATA_PFLAG_LOADING;
|
||||
else if (ap->pflags & ATA_PFLAG_SCSI_HOTPLUG)
|
||||
else if ((ap->pflags & ATA_PFLAG_SCSI_HOTPLUG) &&
|
||||
!(ap->flags & ATA_FLAG_SAS_HOST))
|
||||
schedule_delayed_work(&ap->hotplug_task, 0);
|
||||
|
||||
if (ap->pflags & ATA_PFLAG_RECOVERED)
|
||||
|
|
|
@ -3316,6 +3316,12 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
|
|||
goto invalid_fld;
|
||||
}
|
||||
|
||||
/* We may not issue NCQ commands to devices not supporting NCQ */
|
||||
if (ata_is_ncq(tf->protocol) && !ata_ncq_enabled(dev)) {
|
||||
fp = 1;
|
||||
goto invalid_fld;
|
||||
}
|
||||
|
||||
/* sanity check for pio multi commands */
|
||||
if ((cdb[1] & 0xe0) && !is_multi_taskfile(tf)) {
|
||||
fp = 1;
|
||||
|
@ -4282,7 +4288,7 @@ static inline void ata_scsi_dump_cdb(struct ata_port *ap,
|
|||
#ifdef ATA_DEBUG
|
||||
struct scsi_device *scsidev = cmd->device;
|
||||
|
||||
DPRINTK("CDB (%u:%d,%d,%d) %9ph\n",
|
||||
DPRINTK("CDB (%u:%d,%d,%lld) %9ph\n",
|
||||
ap->print_id,
|
||||
scsidev->channel, scsidev->id, scsidev->lun,
|
||||
cmd->cmnd);
|
||||
|
@ -4309,7 +4315,9 @@ static inline int __ata_scsi_queuecmd(struct scsi_cmnd *scmd,
|
|||
if (likely((scsi_op != ATA_16) || !atapi_passthru16)) {
|
||||
/* relay SCSI command to ATAPI device */
|
||||
int len = COMMAND_SIZE(scsi_op);
|
||||
if (unlikely(len > scmd->cmd_len || len > dev->cdb_len))
|
||||
if (unlikely(len > scmd->cmd_len ||
|
||||
len > dev->cdb_len ||
|
||||
scmd->cmd_len > ATAPI_CDB_LEN))
|
||||
goto bad_cdb_len;
|
||||
|
||||
xlat_func = atapi_xlat;
|
||||
|
|
|
@ -146,6 +146,7 @@
|
|||
enum sata_rcar_type {
|
||||
RCAR_GEN1_SATA,
|
||||
RCAR_GEN2_SATA,
|
||||
RCAR_GEN3_SATA,
|
||||
RCAR_R8A7790_ES1_SATA,
|
||||
};
|
||||
|
||||
|
@ -784,26 +785,11 @@ static void sata_rcar_setup_port(struct ata_host *host)
|
|||
ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
|
||||
}
|
||||
|
||||
static void sata_rcar_init_controller(struct ata_host *host)
|
||||
static void sata_rcar_init_module(struct sata_rcar_priv *priv)
|
||||
{
|
||||
struct sata_rcar_priv *priv = host->private_data;
|
||||
void __iomem *base = priv->base;
|
||||
u32 val;
|
||||
|
||||
/* reset and setup phy */
|
||||
switch (priv->type) {
|
||||
case RCAR_GEN1_SATA:
|
||||
sata_rcar_gen1_phy_init(priv);
|
||||
break;
|
||||
case RCAR_GEN2_SATA:
|
||||
case RCAR_R8A7790_ES1_SATA:
|
||||
sata_rcar_gen2_phy_init(priv);
|
||||
break;
|
||||
default:
|
||||
dev_warn(host->dev, "SATA phy is not initialized\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* SATA-IP reset state */
|
||||
val = ioread32(base + ATAPI_CONTROL1_REG);
|
||||
val |= ATAPI_CONTROL1_RESET;
|
||||
|
@ -824,10 +810,33 @@ static void sata_rcar_init_controller(struct ata_host *host)
|
|||
/* ack and mask */
|
||||
iowrite32(0, base + SATAINTSTAT_REG);
|
||||
iowrite32(0x7ff, base + SATAINTMASK_REG);
|
||||
|
||||
/* enable interrupts */
|
||||
iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
|
||||
}
|
||||
|
||||
static void sata_rcar_init_controller(struct ata_host *host)
|
||||
{
|
||||
struct sata_rcar_priv *priv = host->private_data;
|
||||
|
||||
/* reset and setup phy */
|
||||
switch (priv->type) {
|
||||
case RCAR_GEN1_SATA:
|
||||
sata_rcar_gen1_phy_init(priv);
|
||||
break;
|
||||
case RCAR_GEN2_SATA:
|
||||
case RCAR_GEN3_SATA:
|
||||
case RCAR_R8A7790_ES1_SATA:
|
||||
sata_rcar_gen2_phy_init(priv);
|
||||
break;
|
||||
default:
|
||||
dev_warn(host->dev, "SATA phy is not initialized\n");
|
||||
break;
|
||||
}
|
||||
|
||||
sata_rcar_init_module(priv);
|
||||
}
|
||||
|
||||
static const struct of_device_id sata_rcar_match[] = {
|
||||
{
|
||||
/* Deprecated by "renesas,sata-r8a7779" */
|
||||
|
@ -856,7 +865,7 @@ static const struct of_device_id sata_rcar_match[] = {
|
|||
},
|
||||
{
|
||||
.compatible = "renesas,sata-r8a7795",
|
||||
.data = (void *)RCAR_GEN2_SATA
|
||||
.data = (void *)RCAR_GEN3_SATA
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,rcar-gen2-sata",
|
||||
|
@ -864,7 +873,7 @@ static const struct of_device_id sata_rcar_match[] = {
|
|||
},
|
||||
{
|
||||
.compatible = "renesas,rcar-gen3-sata",
|
||||
.data = (void *)RCAR_GEN2_SATA
|
||||
.data = (void *)RCAR_GEN3_SATA
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
@ -982,11 +991,18 @@ static int sata_rcar_resume(struct device *dev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (priv->type == RCAR_GEN3_SATA) {
|
||||
sata_rcar_gen2_phy_init(priv);
|
||||
sata_rcar_init_module(priv);
|
||||
} else {
|
||||
/* ack and mask */
|
||||
iowrite32(0, base + SATAINTSTAT_REG);
|
||||
iowrite32(0x7ff, base + SATAINTMASK_REG);
|
||||
|
||||
/* enable interrupts */
|
||||
iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
|
||||
iowrite32(ATAPI_INT_ENABLE_SATAINT,
|
||||
base + ATAPI_INT_ENABLE_REG);
|
||||
}
|
||||
|
||||
ata_host_resume(host);
|
||||
|
||||
|
|
|
@ -97,7 +97,7 @@ static struct img_ascii_lcd_config boston_config = {
|
|||
static void malta_update(struct img_ascii_lcd_ctx *ctx)
|
||||
{
|
||||
unsigned int i;
|
||||
int err;
|
||||
int err = 0;
|
||||
|
||||
for (i = 0; i < ctx->cfg->num_chars; i++) {
|
||||
err = regmap_write(ctx->regmap,
|
||||
|
@ -180,7 +180,7 @@ static int sead3_wait_lcd_idle(struct img_ascii_lcd_ctx *ctx)
|
|||
static void sead3_update(struct img_ascii_lcd_ctx *ctx)
|
||||
{
|
||||
unsigned int i;
|
||||
int err;
|
||||
int err = 0;
|
||||
|
||||
for (i = 0; i < ctx->cfg->num_chars; i++) {
|
||||
err = sead3_wait_lcd_idle(ctx);
|
||||
|
@ -224,7 +224,7 @@ MODULE_DEVICE_TABLE(of, img_ascii_lcd_matches);
|
|||
|
||||
/**
|
||||
* img_ascii_lcd_scroll() - scroll the display by a character
|
||||
* @arg: really a pointer to the private data structure
|
||||
* @t: really a pointer to the private data structure
|
||||
*
|
||||
* Scroll the current message along the LCD by one character, rearming the
|
||||
* timer if required.
|
||||
|
|
|
@ -1372,7 +1372,7 @@ static void panel_process_inputs(void)
|
|||
break;
|
||||
input->rise_timer = 0;
|
||||
input->state = INPUT_ST_RISING;
|
||||
/* no break here, fall through */
|
||||
/* fall through */
|
||||
case INPUT_ST_RISING:
|
||||
if ((phys_curr & input->mask) != input->value) {
|
||||
input->state = INPUT_ST_LOW;
|
||||
|
@ -1385,11 +1385,11 @@ static void panel_process_inputs(void)
|
|||
}
|
||||
input->high_timer = 0;
|
||||
input->state = INPUT_ST_HIGH;
|
||||
/* no break here, fall through */
|
||||
/* fall through */
|
||||
case INPUT_ST_HIGH:
|
||||
if (input_state_high(input))
|
||||
break;
|
||||
/* no break here, fall through */
|
||||
/* fall through */
|
||||
case INPUT_ST_FALLING:
|
||||
input_state_falling(input);
|
||||
}
|
||||
|
|
|
@ -231,7 +231,6 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
{ USB_DEVICE(0x0930, 0x0227), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0b05, 0x17d0), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x0036), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x3004), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x3008), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x311d), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x311e), .driver_info = BTUSB_ATH3012 },
|
||||
|
@ -264,6 +263,7 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
{ USB_DEVICE(0x0489, 0xe03c), .driver_info = BTUSB_ATH3012 },
|
||||
|
||||
/* QCA ROME chipset */
|
||||
{ USB_DEVICE(0x0cf3, 0x3004), .driver_info = BTUSB_QCA_ROME },
|
||||
{ USB_DEVICE(0x0cf3, 0xe007), .driver_info = BTUSB_QCA_ROME },
|
||||
{ USB_DEVICE(0x0cf3, 0xe009), .driver_info = BTUSB_QCA_ROME },
|
||||
{ USB_DEVICE(0x0cf3, 0xe010), .driver_info = BTUSB_QCA_ROME },
|
||||
|
@ -386,10 +386,10 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
*/
|
||||
static const struct dmi_system_id btusb_needs_reset_resume_table[] = {
|
||||
{
|
||||
/* Lenovo Yoga 920 (QCA Rome device 0cf3:e300) */
|
||||
/* Dell OptiPlex 3060 (QCA ROME device 0cf3:e007) */
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
|
||||
DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA 920"),
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 3060"),
|
||||
},
|
||||
},
|
||||
{}
|
||||
|
|
|
@ -244,7 +244,9 @@ static irqreturn_t bcm_host_wake(int irq, void *data)
|
|||
|
||||
bt_dev_dbg(bdev, "Host wake IRQ");
|
||||
|
||||
pm_request_resume(bdev->dev);
|
||||
pm_runtime_get(bdev->dev);
|
||||
pm_runtime_mark_last_busy(bdev->dev);
|
||||
pm_runtime_put_autosuspend(bdev->dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
@ -301,7 +303,7 @@ static const struct bcm_set_sleep_mode default_sleep_params = {
|
|||
.usb_auto_sleep = 0,
|
||||
.usb_resume_timeout = 0,
|
||||
.break_to_host = 0,
|
||||
.pulsed_host_wake = 0,
|
||||
.pulsed_host_wake = 1,
|
||||
};
|
||||
|
||||
static int bcm_setup_sleep(struct hci_uart *hu)
|
||||
|
@ -586,8 +588,11 @@ static int bcm_recv(struct hci_uart *hu, const void *data, int count)
|
|||
} else if (!bcm->rx_skb) {
|
||||
/* Delay auto-suspend when receiving completed packet */
|
||||
mutex_lock(&bcm_device_lock);
|
||||
if (bcm->dev && bcm_device_exists(bcm->dev))
|
||||
pm_request_resume(bcm->dev->dev);
|
||||
if (bcm->dev && bcm_device_exists(bcm->dev)) {
|
||||
pm_runtime_get(bcm->dev->dev);
|
||||
pm_runtime_mark_last_busy(bcm->dev->dev);
|
||||
pm_runtime_put_autosuspend(bcm->dev->dev);
|
||||
}
|
||||
mutex_unlock(&bcm_device_lock);
|
||||
}
|
||||
|
||||
|
|
|
@ -449,17 +449,17 @@ struct bcm2835_pll_ana_bits {
|
|||
static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
|
||||
.mask0 = 0,
|
||||
.set0 = 0,
|
||||
.mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK),
|
||||
.mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
|
||||
.set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
|
||||
.mask3 = (u32)~A2W_PLL_KA_MASK,
|
||||
.mask3 = A2W_PLL_KA_MASK,
|
||||
.set3 = (2 << A2W_PLL_KA_SHIFT),
|
||||
.fb_prediv_mask = BIT(14),
|
||||
};
|
||||
|
||||
static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
|
||||
.mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK),
|
||||
.mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
|
||||
.set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
|
||||
.mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK),
|
||||
.mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
|
||||
.set1 = (6 << A2W_PLLH_KP_SHIFT),
|
||||
.mask3 = 0,
|
||||
.set3 = 0,
|
||||
|
@ -623,8 +623,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
|
|||
~A2W_PLL_CTRL_PWRDN);
|
||||
|
||||
/* Take the PLL out of reset. */
|
||||
spin_lock(&cprman->regs_lock);
|
||||
cprman_write(cprman, data->cm_ctrl_reg,
|
||||
cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
|
||||
spin_unlock(&cprman->regs_lock);
|
||||
|
||||
/* Wait for the PLL to lock. */
|
||||
timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
|
||||
|
@ -701,9 +703,11 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
|
|||
}
|
||||
|
||||
/* Unmask the reference clock from the oscillator. */
|
||||
spin_lock(&cprman->regs_lock);
|
||||
cprman_write(cprman, A2W_XOSC_CTRL,
|
||||
cprman_read(cprman, A2W_XOSC_CTRL) |
|
||||
data->reference_enable_mask);
|
||||
spin_unlock(&cprman->regs_lock);
|
||||
|
||||
if (do_ana_setup_first)
|
||||
bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
|
||||
|
|
|
@ -205,6 +205,18 @@ static const struct aspeed_clk_soc_data ast2400_data = {
|
|||
.calc_pll = aspeed_ast2400_calc_pll,
|
||||
};
|
||||
|
||||
static int aspeed_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
|
||||
u32 clk = BIT(gate->clock_idx);
|
||||
u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
|
||||
u32 reg;
|
||||
|
||||
regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
|
||||
|
||||
return ((reg & clk) == enval) ? 1 : 0;
|
||||
}
|
||||
|
||||
static int aspeed_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
|
||||
|
@ -215,6 +227,11 @@ static int aspeed_clk_enable(struct clk_hw *hw)
|
|||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
if (aspeed_clk_is_enabled(hw)) {
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gate->reset_idx >= 0) {
|
||||
/* Put IP in reset */
|
||||
regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
|
||||
|
@ -255,17 +272,6 @@ static void aspeed_clk_disable(struct clk_hw *hw)
|
|||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
static int aspeed_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
|
||||
u32 clk = BIT(gate->clock_idx);
|
||||
u32 reg;
|
||||
|
||||
regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
|
||||
|
||||
return (reg & clk) ? 0 : 1;
|
||||
}
|
||||
|
||||
static const struct clk_ops aspeed_clk_gate_ops = {
|
||||
.enable = aspeed_clk_enable,
|
||||
.disable = aspeed_clk_disable,
|
||||
|
|
|
@ -1125,8 +1125,10 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
|
|||
{
|
||||
lockdep_assert_held(&prepare_lock);
|
||||
|
||||
if (!core)
|
||||
if (!core) {
|
||||
req->rate = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_core_init_rate_req(core, req);
|
||||
|
||||
|
@ -2309,8 +2311,11 @@ static int clk_core_set_phase_nolock(struct clk_core *core, int degrees)
|
|||
|
||||
trace_clk_set_phase(core, degrees);
|
||||
|
||||
if (core->ops->set_phase)
|
||||
if (core->ops->set_phase) {
|
||||
ret = core->ops->set_phase(core->hw, degrees);
|
||||
if (!ret)
|
||||
core->phase = degrees;
|
||||
}
|
||||
|
||||
trace_clk_set_phase_complete(core, degrees);
|
||||
|
||||
|
@ -2967,23 +2972,38 @@ static int __clk_core_init(struct clk_core *core)
|
|||
rate = 0;
|
||||
core->rate = core->req_rate = rate;
|
||||
|
||||
/*
|
||||
* Enable CLK_IS_CRITICAL clocks so newly added critical clocks
|
||||
* don't get accidentally disabled when walking the orphan tree and
|
||||
* reparenting clocks
|
||||
*/
|
||||
if (core->flags & CLK_IS_CRITICAL) {
|
||||
unsigned long flags;
|
||||
|
||||
clk_core_prepare(core);
|
||||
|
||||
flags = clk_enable_lock();
|
||||
clk_core_enable(core);
|
||||
clk_enable_unlock(flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* walk the list of orphan clocks and reparent any that newly finds a
|
||||
* parent.
|
||||
*/
|
||||
hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
|
||||
struct clk_core *parent = __clk_init_parent(orphan);
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* we could call __clk_set_parent, but that would result in a
|
||||
* redundant call to the .set_rate op, if it exists
|
||||
* We need to use __clk_set_parent_before() and _after() to
|
||||
* to properly migrate any prepare/enable count of the orphan
|
||||
* clock. This is important for CLK_IS_CRITICAL clocks, which
|
||||
* are enabled during init but might not have a parent yet.
|
||||
*/
|
||||
if (parent) {
|
||||
/* update the clk tree topology */
|
||||
flags = clk_enable_lock();
|
||||
clk_reparent(orphan, parent);
|
||||
clk_enable_unlock(flags);
|
||||
__clk_set_parent_before(orphan, parent);
|
||||
__clk_set_parent_after(orphan, parent, NULL);
|
||||
__clk_recalc_accuracies(orphan);
|
||||
__clk_recalc_rates(orphan, 0);
|
||||
}
|
||||
|
@ -3000,16 +3020,6 @@ static int __clk_core_init(struct clk_core *core)
|
|||
if (core->ops->init)
|
||||
core->ops->init(core->hw);
|
||||
|
||||
if (core->flags & CLK_IS_CRITICAL) {
|
||||
unsigned long flags;
|
||||
|
||||
clk_core_prepare(core);
|
||||
|
||||
flags = clk_enable_lock();
|
||||
clk_core_enable(core);
|
||||
clk_enable_unlock(flags);
|
||||
}
|
||||
|
||||
kref_init(&core->ref);
|
||||
out:
|
||||
clk_pm_runtime_put(core);
|
||||
|
|
|
@ -149,6 +149,8 @@ static int hi3660_stub_clk_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(stub_clk_chan.mbox);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
freq_reg = devm_ioremap(dev, res->start, resource_size(res));
|
||||
if (!freq_reg)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -131,7 +131,17 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_
|
|||
static struct clk *clk[IMX5_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
static struct clk ** const uart_clks_mx51[] __initconst = {
|
||||
&clk[IMX5_CLK_UART1_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART1_PER_GATE],
|
||||
&clk[IMX5_CLK_UART2_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART2_PER_GATE],
|
||||
&clk[IMX5_CLK_UART3_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART3_PER_GATE],
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
|
||||
&clk[IMX5_CLK_UART1_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART1_PER_GATE],
|
||||
&clk[IMX5_CLK_UART2_IPG_GATE],
|
||||
|
@ -321,8 +331,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
|||
clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
|
||||
static void __init mx50_clocks_init(struct device_node *np)
|
||||
|
@ -388,6 +396,8 @@ static void __init mx50_clocks_init(struct device_node *np)
|
|||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
imx_register_uart_clocks(uart_clks_mx50_mx53);
|
||||
}
|
||||
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
|
||||
|
||||
|
@ -477,6 +487,8 @@ static void __init mx51_clocks_init(struct device_node *np)
|
|||
val = readl(MXC_CCM_CLPCR);
|
||||
val |= 1 << 23;
|
||||
writel(val, MXC_CCM_CLPCR);
|
||||
|
||||
imx_register_uart_clocks(uart_clks_mx51);
|
||||
}
|
||||
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
|
||||
|
||||
|
@ -606,5 +618,7 @@ static void __init mx53_clocks_init(struct device_node *np)
|
|||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
imx_register_uart_clocks(uart_clks_mx50_mx53);
|
||||
}
|
||||
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
|
||||
|
|
|
@ -49,11 +49,10 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
|
|||
struct clk_regmap_mux_div *a53cc;
|
||||
struct regmap *regmap;
|
||||
struct clk_init_data init = { };
|
||||
int ret;
|
||||
int ret = -ENODEV;
|
||||
|
||||
regmap = dev_get_regmap(parent, NULL);
|
||||
if (IS_ERR(regmap)) {
|
||||
ret = PTR_ERR(regmap);
|
||||
if (!regmap) {
|
||||
dev_err(dev, "failed to get regmap: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -762,7 +762,7 @@ static struct ccu_mp out_a_clk = {
|
|||
.features = CCU_FEATURE_FIXED_PREDIV,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("out-a",
|
||||
clk_out_parents,
|
||||
&ccu_div_ops,
|
||||
&ccu_mp_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
@ -783,7 +783,7 @@ static struct ccu_mp out_b_clk = {
|
|||
.features = CCU_FEATURE_FIXED_PREDIV,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("out-b",
|
||||
clk_out_parents,
|
||||
&ccu_div_ops,
|
||||
&ccu_mp_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
@ -804,7 +804,7 @@ static struct ccu_mp out_c_clk = {
|
|||
.features = CCU_FEATURE_FIXED_PREDIV,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("out-c",
|
||||
clk_out_parents,
|
||||
&ccu_div_ops,
|
||||
&ccu_mp_ops,
|
||||
0),
|
||||
},
|
||||
};
|
||||
|
|
|
@ -45,7 +45,7 @@ static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
|
|||
|
||||
static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
|
||||
{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
|
||||
{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" },
|
||||
{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
|
||||
{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
|
||||
{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
|
||||
{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
|
||||
|
|
|
@ -187,7 +187,7 @@ static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst
|
|||
{ AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
|
||||
{ AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
|
||||
{ AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
|
||||
{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "disp_clk", "dss_clkdm" },
|
||||
{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
|
||||
{ AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
|
||||
{ 0 },
|
||||
};
|
||||
|
|
|
@ -537,6 +537,8 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
|
|||
init.parent_names = ®_data->parent;
|
||||
init.num_parents = 1;
|
||||
init.flags = 0;
|
||||
if (reg_data->flags & CLKF_SET_RATE_PARENT)
|
||||
init.flags |= CLK_SET_RATE_PARENT;
|
||||
init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
|
||||
node->parent->name, node->name,
|
||||
reg_data->offset, 0);
|
||||
|
|
|
@ -118,14 +118,15 @@ static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
|
|||
spin_lock_irqsave(&dmamux->lock, flags);
|
||||
mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
|
||||
dmamux->dma_requests);
|
||||
set_bit(mux->chan_id, dmamux->dma_inuse);
|
||||
spin_unlock_irqrestore(&dmamux->lock, flags);
|
||||
|
||||
if (mux->chan_id == dmamux->dma_requests) {
|
||||
spin_unlock_irqrestore(&dmamux->lock, flags);
|
||||
dev_err(&pdev->dev, "Run out of free DMA requests\n");
|
||||
ret = -ENOMEM;
|
||||
goto error;
|
||||
goto error_chan_id;
|
||||
}
|
||||
set_bit(mux->chan_id, dmamux->dma_inuse);
|
||||
spin_unlock_irqrestore(&dmamux->lock, flags);
|
||||
|
||||
/* Look for DMA Master */
|
||||
for (i = 1, min = 0, max = dmamux->dma_reqs[i];
|
||||
|
@ -173,6 +174,8 @@ static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
|
|||
|
||||
error:
|
||||
clear_bit(mux->chan_id, dmamux->dma_inuse);
|
||||
|
||||
error_chan_id:
|
||||
kfree(mux);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
|
|
@ -639,7 +639,7 @@ static void __exit dcdbas_exit(void)
|
|||
platform_driver_unregister(&dcdbas_driver);
|
||||
}
|
||||
|
||||
module_init(dcdbas_init);
|
||||
subsys_initcall_sync(dcdbas_init);
|
||||
module_exit(dcdbas_exit);
|
||||
|
||||
MODULE_DESCRIPTION(DRIVER_DESCRIPTION " (version " DRIVER_VERSION ")");
|
||||
|
|
|
@ -68,11 +68,11 @@ void efi_retrieve_tpm2_eventlog_1_2(efi_system_table_t *sys_table_arg)
|
|||
efi_guid_t linux_eventlog_guid = LINUX_EFI_TPM_EVENT_LOG_GUID;
|
||||
efi_status_t status;
|
||||
efi_physical_addr_t log_location, log_last_entry;
|
||||
struct linux_efi_tpm_eventlog *log_tbl;
|
||||
struct linux_efi_tpm_eventlog *log_tbl = NULL;
|
||||
unsigned long first_entry_addr, last_entry_addr;
|
||||
size_t log_size, last_entry_size;
|
||||
efi_bool_t truncated;
|
||||
void *tcg2_protocol;
|
||||
void *tcg2_protocol = NULL;
|
||||
|
||||
status = efi_call_early(locate_protocol, &tcg2_guid, NULL,
|
||||
&tcg2_protocol);
|
||||
|
|
|
@ -69,26 +69,19 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
|
|||
/* don't do anything if sink is not display port, i.e.,
|
||||
* passive dp->(dvi|hdmi) adaptor
|
||||
*/
|
||||
if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
|
||||
int saved_dpms = connector->dpms;
|
||||
/* Only turn off the display if it's physically disconnected */
|
||||
if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
|
||||
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
||||
} else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
|
||||
/* Don't try to start link training before we
|
||||
* have the dpcd */
|
||||
if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
|
||||
amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
|
||||
amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
|
||||
/* Don't start link training before we have the DPCD */
|
||||
if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
|
||||
return;
|
||||
|
||||
/* set it to OFF so that drm_helper_connector_dpms()
|
||||
* won't return immediately since the current state
|
||||
* is ON at this point.
|
||||
/* Turn the connector off and back on immediately, which
|
||||
* will trigger link training
|
||||
*/
|
||||
connector->dpms = DRM_MODE_DPMS_OFF;
|
||||
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
||||
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
|
||||
}
|
||||
connector->dpms = saved_dpms;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -2063,9 +2063,12 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
|
|||
|
||||
DRM_INFO("amdgpu: finishing device.\n");
|
||||
adev->shutdown = true;
|
||||
if (adev->mode_info.mode_config_initialized)
|
||||
if (adev->mode_info.mode_config_initialized){
|
||||
if (!amdgpu_device_has_dc_support(adev))
|
||||
drm_crtc_force_disable_all(adev->ddev);
|
||||
|
||||
else
|
||||
drm_atomic_helper_shutdown(adev->ddev);
|
||||
}
|
||||
amdgpu_ib_pool_fini(adev);
|
||||
amdgpu_fence_driver_fini(adev);
|
||||
amdgpu_fbdev_fini(adev);
|
||||
|
|
|
@ -36,8 +36,6 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj)
|
|||
struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
|
||||
|
||||
if (robj) {
|
||||
if (robj->gem_base.import_attach)
|
||||
drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
|
||||
amdgpu_mn_unregister(robj);
|
||||
amdgpu_bo_unref(&robj);
|
||||
}
|
||||
|
|
|
@ -352,6 +352,7 @@ struct amdgpu_mode_info {
|
|||
u16 firmware_flags;
|
||||
/* pointer to backlight encoder */
|
||||
struct amdgpu_encoder *bl_encoder;
|
||||
u8 bl_level; /* saved backlight level */
|
||||
struct amdgpu_audio audio; /* audio stuff */
|
||||
int num_crtc; /* number of crtcs */
|
||||
int num_hpd; /* number of hpd pins */
|
||||
|
|
|
@ -56,6 +56,8 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
|
|||
|
||||
amdgpu_bo_kunmap(bo);
|
||||
|
||||
if (bo->gem_base.import_attach)
|
||||
drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
|
||||
drm_gem_object_release(&bo->gem_base);
|
||||
amdgpu_bo_unref(&bo->parent);
|
||||
if (!list_empty(&bo->shadow_list)) {
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#include <linux/backlight.h>
|
||||
#include "bif/bif_4_1_d.h"
|
||||
|
||||
static u8
|
||||
u8
|
||||
amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
|
||||
{
|
||||
u8 backlight_level;
|
||||
|
@ -48,7 +48,7 @@ amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
|
|||
return backlight_level;
|
||||
}
|
||||
|
||||
static void
|
||||
void
|
||||
amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
|
||||
u8 backlight_level)
|
||||
{
|
||||
|
|
|
@ -24,6 +24,11 @@
|
|||
#ifndef __ATOMBIOS_ENCODER_H__
|
||||
#define __ATOMBIOS_ENCODER_H__
|
||||
|
||||
u8
|
||||
amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev);
|
||||
void
|
||||
amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
|
||||
u8 backlight_level);
|
||||
u8
|
||||
amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder);
|
||||
void
|
||||
|
|
|
@ -2921,6 +2921,11 @@ static int dce_v10_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v10_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
adev->mode_info.bl_level =
|
||||
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
|
||||
|
||||
return dce_v10_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -2929,6 +2934,9 @@ static int dce_v10_0_resume(void *handle)
|
|||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret;
|
||||
|
||||
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
|
||||
adev->mode_info.bl_level);
|
||||
|
||||
ret = dce_v10_0_hw_init(handle);
|
||||
|
||||
/* turn on the BL */
|
||||
|
|
|
@ -3047,6 +3047,11 @@ static int dce_v11_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v11_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
adev->mode_info.bl_level =
|
||||
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
|
||||
|
||||
return dce_v11_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -3055,6 +3060,9 @@ static int dce_v11_0_resume(void *handle)
|
|||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret;
|
||||
|
||||
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
|
||||
adev->mode_info.bl_level);
|
||||
|
||||
ret = dce_v11_0_hw_init(handle);
|
||||
|
||||
/* turn on the BL */
|
||||
|
|
|
@ -2787,6 +2787,11 @@ static int dce_v6_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v6_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
adev->mode_info.bl_level =
|
||||
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
|
||||
|
||||
return dce_v6_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -2795,6 +2800,9 @@ static int dce_v6_0_resume(void *handle)
|
|||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret;
|
||||
|
||||
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
|
||||
adev->mode_info.bl_level);
|
||||
|
||||
ret = dce_v6_0_hw_init(handle);
|
||||
|
||||
/* turn on the BL */
|
||||
|
|
|
@ -2819,6 +2819,11 @@ static int dce_v8_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v8_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
adev->mode_info.bl_level =
|
||||
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
|
||||
|
||||
return dce_v8_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -2827,6 +2832,9 @@ static int dce_v8_0_resume(void *handle)
|
|||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret;
|
||||
|
||||
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
|
||||
adev->mode_info.bl_level);
|
||||
|
||||
ret = dce_v8_0_hw_init(handle);
|
||||
|
||||
/* turn on the BL */
|
||||
|
|
|
@ -3134,8 +3134,6 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
|
|||
|
||||
switch (aplane->base.type) {
|
||||
case DRM_PLANE_TYPE_PRIMARY:
|
||||
aplane->base.format_default = true;
|
||||
|
||||
res = drm_universal_plane_init(
|
||||
dm->adev->ddev,
|
||||
&aplane->base,
|
||||
|
@ -4794,6 +4792,9 @@ static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
|
|||
return -EDEADLK;
|
||||
|
||||
crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
|
||||
if (IS_ERR(crtc_state))
|
||||
return PTR_ERR(crtc_state);
|
||||
|
||||
if (crtc->primary == plane && crtc_state->active) {
|
||||
if (!plane_state->fb)
|
||||
return -EINVAL;
|
||||
|
|
|
@ -109,7 +109,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
|
|||
struct cea_sad *sad = &sads[i];
|
||||
|
||||
edid_caps->audio_modes[i].format_code = sad->format;
|
||||
edid_caps->audio_modes[i].channel_count = sad->channels;
|
||||
edid_caps->audio_modes[i].channel_count = sad->channels + 1;
|
||||
edid_caps->audio_modes[i].sample_rate = sad->freq;
|
||||
edid_caps->audio_modes[i].sample_size = sad->byte2;
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue