ASoC: DaVinci: Fixes to McASP configuration
McASP register settings are not correct for DSP mode of operation. There is a channel swap initally. This patch provides fixes to the register values for proper working. Tested on DA830/OMAP-L137 EVM, DM6467 EVM. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -512,34 +512,49 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
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int channel_size)
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{
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u32 fmt = 0;
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u32 mask, rotate;
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switch (channel_size) {
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case DAVINCI_AUDIO_WORD_8:
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fmt = 0x03;
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rotate = 6;
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mask = 0x000000ff;
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break;
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case DAVINCI_AUDIO_WORD_12:
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fmt = 0x05;
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rotate = 5;
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mask = 0x00000fff;
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break;
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case DAVINCI_AUDIO_WORD_16:
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fmt = 0x07;
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rotate = 4;
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mask = 0x0000ffff;
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break;
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case DAVINCI_AUDIO_WORD_20:
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fmt = 0x09;
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rotate = 3;
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mask = 0x000fffff;
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break;
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case DAVINCI_AUDIO_WORD_24:
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fmt = 0x0B;
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rotate = 2;
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mask = 0x00ffffff;
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break;
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case DAVINCI_AUDIO_WORD_28:
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fmt = 0x0D;
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rotate = 1;
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mask = 0x0fffffff;
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break;
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case DAVINCI_AUDIO_WORD_32:
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fmt = 0x0F;
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rotate = 0;
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mask = 0xffffffff;
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break;
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default:
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@ -550,6 +565,13 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
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RXSSZ(fmt), RXSSZ(0x0F));
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
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TXSSZ(fmt), TXSSZ(0x0F));
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
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TXROT(7));
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mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
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RXROT(7));
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
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return 0;
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}
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@ -638,7 +660,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
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printk(KERN_ERR "playback tdm slot %d not supported\n",
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dev->tdm_slots);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF);
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mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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} else {
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/* bit stream is MSB first with no delay */
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@ -655,7 +676,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
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printk(KERN_ERR "capture tdm slot %d not supported\n",
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dev->tdm_slots);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF);
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mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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}
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}
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