Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: tcrypt - do not attempt to write to readonly variable random: update interface comments to reflect reality crypto: picoxcell - add support for the picoxcell crypto engines crypto: sha1 - Add test vector to test partial block processing hwrng: omap - Convert release_resource to release_region/release_mem_region crypto: aesni-intel - Fix remaining leak in rfc4106_set_hash_key crypto: omap-sham - don't treat NULL clk as an error crypto: omap-aes - don't treat NULL clk as an error crypto: testmgr - mark ghash as fips_allowed crypto: testmgr - mark xts(aes) as fips_allowed crypto: skcipher - remove redundant NULL check hwrng: pixocell - add support for picoxcell TRNG crypto: aesni-intel - Don't leak memory in rfc4106_set_hash_subkey
This commit is contained in:
Linus Torvalds
commit
0d2ecee2bd
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@ -873,22 +873,18 @@ rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len)
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crypto_ablkcipher_clear_flags(ctr_tfm, ~0);
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ret = crypto_ablkcipher_setkey(ctr_tfm, key, key_len);
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if (ret) {
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crypto_free_ablkcipher(ctr_tfm);
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return ret;
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}
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if (ret)
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goto out_free_ablkcipher;
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ret = -ENOMEM;
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req = ablkcipher_request_alloc(ctr_tfm, GFP_KERNEL);
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if (!req) {
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crypto_free_ablkcipher(ctr_tfm);
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return -EINVAL;
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}
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if (!req)
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goto out_free_ablkcipher;
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req_data = kmalloc(sizeof(*req_data), GFP_KERNEL);
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if (!req_data) {
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crypto_free_ablkcipher(ctr_tfm);
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return -ENOMEM;
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}
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if (!req_data)
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goto out_free_request;
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memset(req_data->iv, 0, sizeof(req_data->iv));
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/* Clear the data in the hash sub key container to zero.*/
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@ -913,8 +909,10 @@ rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len)
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if (!ret)
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ret = req_data->result.err;
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}
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ablkcipher_request_free(req);
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kfree(req_data);
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out_free_request:
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ablkcipher_request_free(req);
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out_free_ablkcipher:
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crypto_free_ablkcipher(ctr_tfm);
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return ret;
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}
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@ -141,8 +141,7 @@ err:
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if (walk->iv != req->info)
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memcpy(req->info, walk->iv, tfm->crt_ablkcipher.ivsize);
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if (walk->iv_buffer)
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kfree(walk->iv_buffer);
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kfree(walk->iv_buffer);
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return err;
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}
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@ -146,7 +146,8 @@ static void test_cipher_speed(const char *algo, int enc, unsigned int sec,
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unsigned int tcount, u8 *keysize)
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{
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unsigned int ret, i, j, iv_len;
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const char *key, iv[128];
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const char *key;
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char iv[128];
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struct crypto_blkcipher *tfm;
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struct blkcipher_desc desc;
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const char *e;
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@ -2077,6 +2077,7 @@ static const struct alg_test_desc alg_test_descs[] = {
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}, {
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.alg = "ghash",
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.test = alg_test_hash,
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.fips_allowed = 1,
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.suite = {
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.hash = {
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.vecs = ghash_tv_template,
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@ -2453,6 +2454,7 @@ static const struct alg_test_desc alg_test_descs[] = {
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}, {
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.alg = "xts(aes)",
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.test = alg_test_skcipher,
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.fips_allowed = 1,
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.suite = {
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.cipher = {
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.enc = {
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@ -451,8 +451,9 @@ static struct hash_testvec rmd320_tv_template[] = {
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/*
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* SHA1 test vectors from from FIPS PUB 180-1
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* Long vector from CAVS 5.0
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*/
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#define SHA1_TEST_VECTORS 2
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#define SHA1_TEST_VECTORS 3
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static struct hash_testvec sha1_tv_template[] = {
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{
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@ -467,6 +468,33 @@ static struct hash_testvec sha1_tv_template[] = {
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"\x4a\xa1\xf9\x51\x29\xe5\xe5\x46\x70\xf1",
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.np = 2,
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.tap = { 28, 28 }
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}, {
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.plaintext = "\xec\x29\x56\x12\x44\xed\xe7\x06"
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"\xb6\xeb\x30\xa1\xc3\x71\xd7\x44"
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"\x50\xa1\x05\xc3\xf9\x73\x5f\x7f"
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"\xa9\xfe\x38\xcf\x67\xf3\x04\xa5"
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"\x73\x6a\x10\x6e\x92\xe1\x71\x39"
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"\xa6\x81\x3b\x1c\x81\xa4\xf3\xd3"
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"\xfb\x95\x46\xab\x42\x96\xfa\x9f"
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"\x72\x28\x26\xc0\x66\x86\x9e\xda"
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"\xcd\x73\xb2\x54\x80\x35\x18\x58"
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"\x13\xe2\x26\x34\xa9\xda\x44\x00"
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"\x0d\x95\xa2\x81\xff\x9f\x26\x4e"
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"\xcc\xe0\xa9\x31\x22\x21\x62\xd0"
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"\x21\xcc\xa2\x8d\xb5\xf3\xc2\xaa"
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"\x24\x94\x5a\xb1\xe3\x1c\xb4\x13"
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"\xae\x29\x81\x0f\xd7\x94\xca\xd5"
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"\xdf\xaf\x29\xec\x43\xcb\x38\xd1"
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"\x98\xfe\x4a\xe1\xda\x23\x59\x78"
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"\x02\x21\x40\x5b\xd6\x71\x2a\x53"
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"\x05\xda\x4b\x1b\x73\x7f\xce\x7c"
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"\xd2\x1c\x0e\xb7\x72\x8d\x08\x23"
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"\x5a\x90\x11",
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.psize = 163,
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.digest = "\x97\x01\x11\xc4\xe7\x7b\xcc\x88\xcc\x20"
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"\x45\x9c\x02\xb6\x9b\x4a\xa8\xf5\x82\x17",
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.np = 4,
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.tap = { 63, 64, 31, 5 }
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}
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};
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|
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@ -198,3 +198,15 @@ config HW_RANDOM_NOMADIK
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module will be called nomadik-rng.
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If unsure, say Y.
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config HW_RANDOM_PICOXCELL
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tristate "Picochip picoXcell true random number generator support"
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depends on HW_RANDOM && ARCH_PICOXCELL && PICOXCELL_PC3X3
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---help---
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This driver provides kernel-side support for the Random Number
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Generator hardware found on Picochip PC3x3 and later devices.
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To compile this driver as a module, choose M here: the
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module will be called picoxcell-rng.
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If unsure, say Y.
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|
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@ -19,3 +19,4 @@ obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
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obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
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obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
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obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
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obj-$(CONFIG_HW_RANDOM_PICOXCELL) += picoxcell-rng.o
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@ -91,7 +91,7 @@ static struct hwrng omap_rng_ops = {
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static int __devinit omap_rng_probe(struct platform_device *pdev)
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{
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struct resource *res, *mem;
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struct resource *res;
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int ret;
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/*
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@ -116,14 +116,12 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
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if (!res)
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return -ENOENT;
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mem = request_mem_region(res->start, resource_size(res),
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pdev->name);
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if (mem == NULL) {
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if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
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ret = -EBUSY;
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goto err_region;
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}
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dev_set_drvdata(&pdev->dev, mem);
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dev_set_drvdata(&pdev->dev, res);
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rng_base = ioremap(res->start, resource_size(res));
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if (!rng_base) {
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ret = -ENOMEM;
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@ -146,7 +144,7 @@ err_register:
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iounmap(rng_base);
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rng_base = NULL;
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err_ioremap:
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release_resource(mem);
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release_mem_region(res->start, resource_size(res));
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err_region:
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if (cpu_is_omap24xx()) {
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clk_disable(rng_ick);
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@ -157,7 +155,7 @@ err_region:
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|||
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static int __exit omap_rng_remove(struct platform_device *pdev)
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{
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struct resource *mem = dev_get_drvdata(&pdev->dev);
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struct resource *res = dev_get_drvdata(&pdev->dev);
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hwrng_unregister(&omap_rng_ops);
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@ -170,7 +168,7 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
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clk_put(rng_ick);
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}
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release_resource(mem);
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release_mem_region(res->start, resource_size(res));
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rng_base = NULL;
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return 0;
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|
|
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|
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@ -0,0 +1,208 @@
|
|||
/*
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||||
* Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* All enquiries to support@picochip.com
|
||||
*/
|
||||
#include <linux/clk.h>
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#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
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#include <linux/hw_random.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define DATA_REG_OFFSET 0x0200
|
||||
#define CSR_REG_OFFSET 0x0278
|
||||
#define CSR_OUT_EMPTY_MASK (1 << 24)
|
||||
#define CSR_FAULT_MASK (1 << 1)
|
||||
#define TRNG_BLOCK_RESET_MASK (1 << 0)
|
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#define TAI_REG_OFFSET 0x0380
|
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|
||||
/*
|
||||
* The maximum amount of time in microseconds to spend waiting for data if the
|
||||
* core wants us to wait. The TRNG should generate 32 bits every 320ns so a
|
||||
* timeout of 20us seems reasonable. The TRNG does builtin tests of the data
|
||||
* for randomness so we can't always assume there is data present.
|
||||
*/
|
||||
#define PICO_TRNG_TIMEOUT 20
|
||||
|
||||
static void __iomem *rng_base;
|
||||
static struct clk *rng_clk;
|
||||
struct device *rng_dev;
|
||||
|
||||
static inline u32 picoxcell_trng_read_csr(void)
|
||||
{
|
||||
return __raw_readl(rng_base + CSR_REG_OFFSET);
|
||||
}
|
||||
|
||||
static inline bool picoxcell_trng_is_empty(void)
|
||||
{
|
||||
return picoxcell_trng_read_csr() & CSR_OUT_EMPTY_MASK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Take the random number generator out of reset and make sure the interrupts
|
||||
* are masked. We shouldn't need to get large amounts of random bytes so just
|
||||
* poll the status register. The hardware generates 32 bits every 320ns so we
|
||||
* shouldn't have to wait long enough to warrant waiting for an IRQ.
|
||||
*/
|
||||
static void picoxcell_trng_start(void)
|
||||
{
|
||||
__raw_writel(0, rng_base + TAI_REG_OFFSET);
|
||||
__raw_writel(0, rng_base + CSR_REG_OFFSET);
|
||||
}
|
||||
|
||||
static void picoxcell_trng_reset(void)
|
||||
{
|
||||
__raw_writel(TRNG_BLOCK_RESET_MASK, rng_base + CSR_REG_OFFSET);
|
||||
__raw_writel(TRNG_BLOCK_RESET_MASK, rng_base + TAI_REG_OFFSET);
|
||||
picoxcell_trng_start();
|
||||
}
|
||||
|
||||
/*
|
||||
* Get some random data from the random number generator. The hw_random core
|
||||
* layer provides us with locking.
|
||||
*/
|
||||
static int picoxcell_trng_read(struct hwrng *rng, void *buf, size_t max,
|
||||
bool wait)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Wait for some data to become available. */
|
||||
for (i = 0; i < PICO_TRNG_TIMEOUT && picoxcell_trng_is_empty(); ++i) {
|
||||
if (!wait)
|
||||
return 0;
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (picoxcell_trng_read_csr() & CSR_FAULT_MASK) {
|
||||
dev_err(rng_dev, "fault detected, resetting TRNG\n");
|
||||
picoxcell_trng_reset();
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (i == PICO_TRNG_TIMEOUT)
|
||||
return 0;
|
||||
|
||||
*(u32 *)buf = __raw_readl(rng_base + DATA_REG_OFFSET);
|
||||
return sizeof(u32);
|
||||
}
|
||||
|
||||
static struct hwrng picoxcell_trng = {
|
||||
.name = "picoxcell",
|
||||
.read = picoxcell_trng_read,
|
||||
};
|
||||
|
||||
static int picoxcell_trng_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
if (!mem) {
|
||||
dev_warn(&pdev->dev, "no memory resource\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
|
||||
"picoxcell_trng")) {
|
||||
dev_warn(&pdev->dev, "unable to request io mem\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
rng_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
||||
if (!rng_base) {
|
||||
dev_warn(&pdev->dev, "unable to remap io mem\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
rng_clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(rng_clk)) {
|
||||
dev_warn(&pdev->dev, "no clk\n");
|
||||
return PTR_ERR(rng_clk);
|
||||
}
|
||||
|
||||
ret = clk_enable(rng_clk);
|
||||
if (ret) {
|
||||
dev_warn(&pdev->dev, "unable to enable clk\n");
|
||||
goto err_enable;
|
||||
}
|
||||
|
||||
picoxcell_trng_start();
|
||||
ret = hwrng_register(&picoxcell_trng);
|
||||
if (ret)
|
||||
goto err_register;
|
||||
|
||||
rng_dev = &pdev->dev;
|
||||
dev_info(&pdev->dev, "pixoxcell random number generator active\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_register:
|
||||
clk_disable(rng_clk);
|
||||
err_enable:
|
||||
clk_put(rng_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit picoxcell_trng_remove(struct platform_device *pdev)
|
||||
{
|
||||
hwrng_unregister(&picoxcell_trng);
|
||||
clk_disable(rng_clk);
|
||||
clk_put(rng_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int picoxcell_trng_suspend(struct device *dev)
|
||||
{
|
||||
clk_disable(rng_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int picoxcell_trng_resume(struct device *dev)
|
||||
{
|
||||
return clk_enable(rng_clk);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops picoxcell_trng_pm_ops = {
|
||||
.suspend = picoxcell_trng_suspend,
|
||||
.resume = picoxcell_trng_resume,
|
||||
};
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static struct platform_driver picoxcell_trng_driver = {
|
||||
.probe = picoxcell_trng_probe,
|
||||
.remove = __devexit_p(picoxcell_trng_remove),
|
||||
.driver = {
|
||||
.name = "picoxcell-trng",
|
||||
.owner = THIS_MODULE,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &picoxcell_trng_pm_ops,
|
||||
#endif /* CONFIG_PM */
|
||||
},
|
||||
};
|
||||
|
||||
static int __init picoxcell_trng_init(void)
|
||||
{
|
||||
return platform_driver_register(&picoxcell_trng_driver);
|
||||
}
|
||||
module_init(picoxcell_trng_init);
|
||||
|
||||
static void __exit picoxcell_trng_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&picoxcell_trng_driver);
|
||||
}
|
||||
module_exit(picoxcell_trng_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Jamie Iles");
|
||||
MODULE_DESCRIPTION("Picochip picoXcell TRNG driver");
|
||||
|
|
@ -128,6 +128,7 @@
|
|||
* void add_input_randomness(unsigned int type, unsigned int code,
|
||||
* unsigned int value);
|
||||
* void add_interrupt_randomness(int irq);
|
||||
* void add_disk_randomness(struct gendisk *disk);
|
||||
*
|
||||
* add_input_randomness() uses the input layer interrupt timing, as well as
|
||||
* the event type information from the hardware.
|
||||
|
|
@ -136,9 +137,15 @@
|
|||
* inputs to the entropy pool. Note that not all interrupts are good
|
||||
* sources of randomness! For example, the timer interrupts is not a
|
||||
* good choice, because the periodicity of the interrupts is too
|
||||
* regular, and hence predictable to an attacker. Disk interrupts are
|
||||
* a better measure, since the timing of the disk interrupts are more
|
||||
* unpredictable.
|
||||
* regular, and hence predictable to an attacker. Network Interface
|
||||
* Controller interrupts are a better measure, since the timing of the
|
||||
* NIC interrupts are more unpredictable.
|
||||
*
|
||||
* add_disk_randomness() uses what amounts to the seek time of block
|
||||
* layer request events, on a per-disk_devt basis, as input to the
|
||||
* entropy pool. Note that high-speed solid state drives with very low
|
||||
* seek times do not make for good sources of entropy, as their seek
|
||||
* times are usually fairly consistent.
|
||||
*
|
||||
* All of these routines try to estimate how many bits of randomness a
|
||||
* particular randomness source. They do this by keeping track of the
|
||||
|
|
|
|||
|
|
@ -252,4 +252,21 @@ config CRYPTO_DEV_OMAP_AES
|
|||
OMAP processors have AES module accelerator. Select this if you
|
||||
want to use the OMAP module for AES algorithms.
|
||||
|
||||
config CRYPTO_DEV_PICOXCELL
|
||||
tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
|
||||
depends on ARCH_PICOXCELL
|
||||
select CRYPTO_AES
|
||||
select CRYPTO_AUTHENC
|
||||
select CRYPTO_ALGAPI
|
||||
select CRYPTO_DES
|
||||
select CRYPTO_CBC
|
||||
select CRYPTO_ECB
|
||||
select CRYPTO_SEQIV
|
||||
help
|
||||
This option enables support for the hardware offload engines in the
|
||||
Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
|
||||
and for 3gpp Layer 2 ciphering support.
|
||||
|
||||
Saying m here will build a module named pipcoxcell_crypto.
|
||||
|
||||
endif # CRYPTO_HW
|
||||
|
|
|
|||
|
|
@ -10,4 +10,4 @@ obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
|
|||
obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
|
||||
obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
|
||||
obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
|
||||
|
||||
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
|
||||
|
|
|
|||
|
|
@ -839,9 +839,9 @@ static int omap_aes_probe(struct platform_device *pdev)
|
|||
|
||||
/* Initializing the clock */
|
||||
dd->iclk = clk_get(dev, "ick");
|
||||
if (!dd->iclk) {
|
||||
if (IS_ERR(dd->iclk)) {
|
||||
dev_err(dev, "clock intialization failed.\n");
|
||||
err = -ENODEV;
|
||||
err = PTR_ERR(dd->iclk);
|
||||
goto err_res;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1206,9 +1206,9 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
|
|||
|
||||
/* Initializing the clock */
|
||||
dd->iclk = clk_get(dev, "ick");
|
||||
if (!dd->iclk) {
|
||||
if (IS_ERR(dd->iclk)) {
|
||||
dev_err(dev, "clock intialization failed.\n");
|
||||
err = -ENODEV;
|
||||
err = PTR_ERR(dd->iclk);
|
||||
goto clk_err;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Picochip Ltd., Jamie Iles
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __PICOXCELL_CRYPTO_REGS_H__
|
||||
#define __PICOXCELL_CRYPTO_REGS_H__
|
||||
|
||||
#define SPA_STATUS_OK 0
|
||||
#define SPA_STATUS_ICV_FAIL 1
|
||||
#define SPA_STATUS_MEMORY_ERROR 2
|
||||
#define SPA_STATUS_BLOCK_ERROR 3
|
||||
|
||||
#define SPA_IRQ_CTRL_STAT_CNT_OFFSET 16
|
||||
#define SPA_IRQ_STAT_STAT_MASK (1 << 4)
|
||||
#define SPA_FIFO_STAT_STAT_OFFSET 16
|
||||
#define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
|
||||
#define SPA_STATUS_RES_CODE_OFFSET 24
|
||||
#define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET)
|
||||
#define SPA_KEY_SZ_CTX_INDEX_OFFSET 8
|
||||
#define SPA_KEY_SZ_CIPHER_OFFSET 31
|
||||
|
||||
#define SPA_IRQ_EN_REG_OFFSET 0x00000000
|
||||
#define SPA_IRQ_STAT_REG_OFFSET 0x00000004
|
||||
#define SPA_IRQ_CTRL_REG_OFFSET 0x00000008
|
||||
#define SPA_FIFO_STAT_REG_OFFSET 0x0000000C
|
||||
#define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010
|
||||
#define SPA_SRC_PTR_REG_OFFSET 0x00000020
|
||||
#define SPA_DST_PTR_REG_OFFSET 0x00000024
|
||||
#define SPA_OFFSET_REG_OFFSET 0x00000028
|
||||
#define SPA_AAD_LEN_REG_OFFSET 0x0000002C
|
||||
#define SPA_PROC_LEN_REG_OFFSET 0x00000030
|
||||
#define SPA_ICV_LEN_REG_OFFSET 0x00000034
|
||||
#define SPA_ICV_OFFSET_REG_OFFSET 0x00000038
|
||||
#define SPA_SW_CTRL_REG_OFFSET 0x0000003C
|
||||
#define SPA_CTRL_REG_OFFSET 0x00000040
|
||||
#define SPA_AUX_INFO_REG_OFFSET 0x0000004C
|
||||
#define SPA_STAT_POP_REG_OFFSET 0x00000050
|
||||
#define SPA_STATUS_REG_OFFSET 0x00000054
|
||||
#define SPA_KEY_SZ_REG_OFFSET 0x00000100
|
||||
#define SPA_CIPH_KEY_BASE_REG_OFFSET 0x00004000
|
||||
#define SPA_HASH_KEY_BASE_REG_OFFSET 0x00008000
|
||||
#define SPA_RC4_CTX_BASE_REG_OFFSET 0x00020000
|
||||
|
||||
#define SPA_IRQ_EN_REG_RESET 0x00000000
|
||||
#define SPA_IRQ_CTRL_REG_RESET 0x00000000
|
||||
#define SPA_FIFO_STAT_REG_RESET 0x00000000
|
||||
#define SPA_SDMA_BRST_SZ_REG_RESET 0x00000000
|
||||
#define SPA_SRC_PTR_REG_RESET 0x00000000
|
||||
#define SPA_DST_PTR_REG_RESET 0x00000000
|
||||
#define SPA_OFFSET_REG_RESET 0x00000000
|
||||
#define SPA_AAD_LEN_REG_RESET 0x00000000
|
||||
#define SPA_PROC_LEN_REG_RESET 0x00000000
|
||||
#define SPA_ICV_LEN_REG_RESET 0x00000000
|
||||
#define SPA_ICV_OFFSET_REG_RESET 0x00000000
|
||||
#define SPA_SW_CTRL_REG_RESET 0x00000000
|
||||
#define SPA_CTRL_REG_RESET 0x00000000
|
||||
#define SPA_AUX_INFO_REG_RESET 0x00000000
|
||||
#define SPA_STAT_POP_REG_RESET 0x00000000
|
||||
#define SPA_STATUS_REG_RESET 0x00000000
|
||||
#define SPA_KEY_SZ_REG_RESET 0x00000000
|
||||
|
||||
#define SPA_CTRL_HASH_ALG_IDX 4
|
||||
#define SPA_CTRL_CIPH_MODE_IDX 8
|
||||
#define SPA_CTRL_HASH_MODE_IDX 12
|
||||
#define SPA_CTRL_CTX_IDX 16
|
||||
#define SPA_CTRL_ENCRYPT_IDX 24
|
||||
#define SPA_CTRL_AAD_COPY 25
|
||||
#define SPA_CTRL_ICV_PT 26
|
||||
#define SPA_CTRL_ICV_ENC 27
|
||||
#define SPA_CTRL_ICV_APPEND 28
|
||||
#define SPA_CTRL_KEY_EXP 29
|
||||
|
||||
#define SPA_KEY_SZ_CXT_IDX 8
|
||||
#define SPA_KEY_SZ_CIPHER_IDX 31
|
||||
|
||||
#define SPA_IRQ_EN_CMD0_EN (1 << 0)
|
||||
#define SPA_IRQ_EN_STAT_EN (1 << 4)
|
||||
#define SPA_IRQ_EN_GLBL_EN (1 << 31)
|
||||
|
||||
#define SPA_CTRL_CIPH_ALG_NULL 0x00
|
||||
#define SPA_CTRL_CIPH_ALG_DES 0x01
|
||||
#define SPA_CTRL_CIPH_ALG_AES 0x02
|
||||
#define SPA_CTRL_CIPH_ALG_RC4 0x03
|
||||
#define SPA_CTRL_CIPH_ALG_MULTI2 0x04
|
||||
#define SPA_CTRL_CIPH_ALG_KASUMI 0x05
|
||||
|
||||
#define SPA_CTRL_HASH_ALG_NULL (0x00 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_MD5 (0x01 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_SHA (0x02 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_SHA224 (0x03 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_SHA256 (0x04 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_SHA384 (0x05 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_SHA512 (0x06 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_AESMAC (0x07 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_AESCMAC (0x08 << SPA_CTRL_HASH_ALG_IDX)
|
||||
#define SPA_CTRL_HASH_ALG_KASF9 (0x09 << SPA_CTRL_HASH_ALG_IDX)
|
||||
|
||||
#define SPA_CTRL_CIPH_MODE_NULL (0x00 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_ECB (0x00 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_CBC (0x01 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_CTR (0x02 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_CCM (0x03 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_GCM (0x05 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_OFB (0x07 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_CFB (0x08 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
#define SPA_CTRL_CIPH_MODE_F8 (0x09 << SPA_CTRL_CIPH_MODE_IDX)
|
||||
|
||||
#define SPA_CTRL_HASH_MODE_RAW (0x00 << SPA_CTRL_HASH_MODE_IDX)
|
||||
#define SPA_CTRL_HASH_MODE_SSLMAC (0x01 << SPA_CTRL_HASH_MODE_IDX)
|
||||
#define SPA_CTRL_HASH_MODE_HMAC (0x02 << SPA_CTRL_HASH_MODE_IDX)
|
||||
|
||||
#define SPA_FIFO_STAT_EMPTY (1 << 31)
|
||||
#define SPA_FIFO_CMD_FULL (1 << 7)
|
||||
|
||||
#endif /* __PICOXCELL_CRYPTO_REGS_H__ */
|
||||
Loading…
Reference in New Issue