sh: intc - add support for sh7619
This patch converts the cpu specific interrupt setup code for sh7619 from ipr to intc. New vectors are also added to match the information provided by the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -12,6 +12,61 @@
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#include <linux/serial.h>
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#include <asm/sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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WDT, EDMAC, CMT0, CMT1,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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HIF_HIFI, HIF_HIFBI,
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DMAC0, DMAC1, DMAC2, DMAC3,
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SIOF,
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/* interrupt groups */
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SCIF0, SCIF1, SCIF2,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
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INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
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INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
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INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
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INTC_IRQ(SCIF0_ERI, 88), INTC_IRQ(SCIF0_RXI, 89),
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INTC_IRQ(SCIF0_BRI, 90), INTC_IRQ(SCIF0_TXI, 91),
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INTC_IRQ(SCIF1_ERI, 92), INTC_IRQ(SCIF1_RXI, 93),
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INTC_IRQ(SCIF1_BRI, 94), INTC_IRQ(SCIF1_TXI, 95),
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INTC_IRQ(SCIF2_ERI, 96), INTC_IRQ(SCIF2_RXI, 97),
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INTC_IRQ(SCIF2_BRI, 98), INTC_IRQ(SCIF2_TXI, 99),
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INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
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INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
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INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
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INTC_IRQ(SIOF, 108),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
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{ 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
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{ 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
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{ 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, groups,
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NULL, NULL, prio_registers, NULL);
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xf8400000,
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@ -52,43 +107,7 @@ static int __init sh7619_devices_setup(void)
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}
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__initcall(sh7619_devices_setup);
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static struct ipr_data ipr_irq_table[] = {
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{ 86, 0, 4, 2 }, /* CMI0 */
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{ 88, 1, 12, 3 }, /* SCIF0_ERI */
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{ 89, 1, 12, 3 }, /* SCIF0_RXI */
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{ 90, 1, 12, 3 }, /* SCIF0_BRI */
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{ 91, 1, 12, 3 }, /* SCIF0_TXI */
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{ 92, 1, 8, 3 }, /* SCIF1_ERI */
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{ 93, 1, 8, 3 }, /* SCIF1_RXI */
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{ 94, 1, 8, 3 }, /* SCIF1_BRI */
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{ 95, 1, 8, 3 }, /* SCIF1_TXI */
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{ 96, 1, 4, 3 }, /* SCIF2_ERI */
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{ 97, 1, 4, 3 }, /* SCIF2_RXI */
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{ 98, 1, 4, 3 }, /* SCIF2_BRI */
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{ 99, 1, 4, 3 }, /* SCIF2_TXI */
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};
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static unsigned long ipr_offsets[] = {
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0xf8080000, /* IPRC */
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0xf8080002, /* IPRD */
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0xf8080004, /* IPRE */
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0xf8080006, /* IPRF */
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0xf8080008, /* IPRG */
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-sh7619",
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},
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};
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void __init plat_irq_setup(void)
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{
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register_ipr_controller(&ipr_irq_desc);
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register_intc_controller(&intc_desc);
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}
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@ -50,7 +50,7 @@ choice
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config CPU_SUBTYPE_SH7619
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bool "Support SH7619 processor"
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select CPU_SH2
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_INTC_IRQ
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# SH-2A Processor Support
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