[ARM] 3971/1: xsc3: get rid of L_PTE_COHERENT
Merge L_PTE_COHERENT with L_PTE_SHARED and free up a L_PTE_* bit. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -265,7 +265,7 @@ static void __init build_mem_type_table(void)
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if (arch_is_coherent()) {
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if (cpu_is_xsc3()) {
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
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mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
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}
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}
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@ -371,8 +371,10 @@ ENTRY(cpu_xsc3_switch_mm)
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ENTRY(cpu_xsc3_set_pte)
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str r1, [r0], #-2048 @ linux version
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bic r2, r1, #0xdf0 @ Keep C, B, coherency bits
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bic r2, r1, #0xff0 @ Keep C, B bits
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orr r2, r2, #PTE_TYPE_EXT @ extended page
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tst r1, #L_PTE_SHARED @ Shared?
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orrne r2, r2, #0x200
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
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#define L_PTE_WRITE (1 << 5)
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#define L_PTE_EXEC (1 << 6)
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#define L_PTE_DIRTY (1 << 7)
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#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */
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#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */
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#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
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#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */
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#ifndef __ASSEMBLY__
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