ARM: SMP: use more sane register allocation for __fixup_smp_on_up
Use r0,r3-r6 rather than r0,r3,r4,r6,r7, which makes it easier to understand which registers can be modified. Also document which registers hold values which must be preserved. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -89,6 +89,11 @@ ENTRY(stext)
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bl __lookup_machine_type @ r5=machinfo
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movs r8, r5 @ invalid machine (r5=0)?
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beq __error_a @ yes, error 'a'
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/*
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* r1 = machine no, r2 = atags,
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* r8 = machinfo, r9 = cpuid, r10 = procinfo
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*/
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bl __vet_atags
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#ifdef CONFIG_SMP_ON_UP
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bl __fixup_smp
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@ -381,19 +386,19 @@ ENDPROC(__turn_mmu_on)
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#ifdef CONFIG_SMP_ON_UP
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__fixup_smp:
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mov r7, #0x00070000
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orr r6, r7, #0xff000000 @ mask 0xff070000
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orr r7, r7, #0x41000000 @ val 0x41070000
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and r0, r9, r6
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teq r0, r7 @ ARM CPU and ARMv6/v7?
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mov r4, #0x00070000
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orr r3, r4, #0xff000000 @ mask 0xff070000
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orr r4, r4, #0x41000000 @ val 0x41070000
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and r0, r9, r3
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teq r0, r4 @ ARM CPU and ARMv6/v7?
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bne __fixup_smp_on_up @ no, assume UP
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orr r6, r6, #0x0000ff00
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orr r6, r6, #0x000000f0 @ mask 0xff07fff0
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orr r7, r7, #0x0000b000
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orr r7, r7, #0x00000020 @ val 0x4107b020
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and r0, r9, r6
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teq r0, r7 @ ARM 11MPCore?
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orr r3, r3, #0x0000ff00
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orr r3, r3, #0x000000f0 @ mask 0xff07fff0
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orr r4, r4, #0x0000b000
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orr r4, r4, #0x00000020 @ val 0x4107b020
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and r0, r9, r3
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teq r0, r4 @ ARM 11MPCore?
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moveq pc, lr @ yes, assume SMP
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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@ -402,13 +407,13 @@ __fixup_smp:
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__fixup_smp_on_up:
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adr r0, 1f
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ldmia r0, {r3, r6, r7}
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ldmia r0, {r3 - r5}
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sub r3, r0, r3
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add r6, r6, r3
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add r7, r7, r3
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2: cmp r6, r7
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ldmia r6!, {r0, r4}
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strlo r4, [r0, r3]
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add r4, r4, r3
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add r5, r5, r3
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2: cmp r4, r5
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ldmia r4!, {r0, r6}
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strlo r6, [r0, r3]
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blo 2b
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mov pc, lr
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ENDPROC(__fixup_smp)
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