perf/x86/intel: Update Intel models
The model number descriptions got a bit messy, clean them up. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/n/tip-oo3xclxdoy8s7ubssn929vaj@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
parent
1a91eac68b
commit
0f7c29ce90
|
@ -2367,15 +2367,15 @@ __init int intel_pmu_init(void)
|
|||
* Install the hw-cache-events table:
|
||||
*/
|
||||
switch (boot_cpu_data.x86_model) {
|
||||
case 14: /* 65 nm core solo/duo, "Yonah" */
|
||||
case 14: /* 65nm Core "Yonah" */
|
||||
pr_cont("Core events, ");
|
||||
break;
|
||||
|
||||
case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
|
||||
case 15: /* 65nm Core2 "Merom" */
|
||||
x86_add_quirk(intel_clovertown_quirk);
|
||||
case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
|
||||
case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
|
||||
case 29: /* six-core 45 nm xeon "Dunnington" */
|
||||
case 22: /* 65nm Core2 "Merom-L" */
|
||||
case 23: /* 45nm Core2 "Penryn" */
|
||||
case 29: /* 45nm Core2 "Dunnington (MP) */
|
||||
memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
|
||||
|
@ -2386,9 +2386,9 @@ __init int intel_pmu_init(void)
|
|||
pr_cont("Core2 events, ");
|
||||
break;
|
||||
|
||||
case 26: /* 45 nm nehalem, "Bloomfield" */
|
||||
case 30: /* 45 nm nehalem, "Lynnfield" */
|
||||
case 46: /* 45 nm nehalem-ex, "Beckton" */
|
||||
case 30: /* 45nm Nehalem */
|
||||
case 26: /* 45nm Nehalem-EP */
|
||||
case 46: /* 45nm Nehalem-EX */
|
||||
memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
|
||||
|
@ -2415,11 +2415,11 @@ __init int intel_pmu_init(void)
|
|||
pr_cont("Nehalem events, ");
|
||||
break;
|
||||
|
||||
case 28: /* Atom */
|
||||
case 38: /* Lincroft */
|
||||
case 39: /* Penwell */
|
||||
case 53: /* Cloverview */
|
||||
case 54: /* Cedarview */
|
||||
case 28: /* 45nm Atom "Pineview" */
|
||||
case 38: /* 45nm Atom "Lincroft" */
|
||||
case 39: /* 32nm Atom "Penwell" */
|
||||
case 53: /* 32nm Atom "Cloverview" */
|
||||
case 54: /* 32nm Atom "Cedarview" */
|
||||
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
|
||||
|
@ -2430,8 +2430,8 @@ __init int intel_pmu_init(void)
|
|||
pr_cont("Atom events, ");
|
||||
break;
|
||||
|
||||
case 55: /* Atom 22nm "Silvermont" */
|
||||
case 77: /* Avoton "Silvermont" */
|
||||
case 55: /* 22nm Atom "Silvermont" */
|
||||
case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
|
||||
memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
|
||||
|
@ -2446,9 +2446,9 @@ __init int intel_pmu_init(void)
|
|||
pr_cont("Silvermont events, ");
|
||||
break;
|
||||
|
||||
case 37: /* 32 nm nehalem, "Clarkdale" */
|
||||
case 44: /* 32 nm nehalem, "Gulftown" */
|
||||
case 47: /* 32 nm Xeon E7 */
|
||||
case 37: /* 32nm Westmere */
|
||||
case 44: /* 32nm Westmere-EP */
|
||||
case 47: /* 32nm Westmere-EX */
|
||||
memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
|
||||
|
@ -2474,8 +2474,8 @@ __init int intel_pmu_init(void)
|
|||
pr_cont("Westmere events, ");
|
||||
break;
|
||||
|
||||
case 42: /* SandyBridge */
|
||||
case 45: /* SandyBridge, "Romely-EP" */
|
||||
case 42: /* 32nm SandyBridge */
|
||||
case 45: /* 32nm SandyBridge-E/EN/EP */
|
||||
x86_add_quirk(intel_sandybridge_quirk);
|
||||
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
|
@ -2506,8 +2506,9 @@ __init int intel_pmu_init(void)
|
|||
|
||||
pr_cont("SandyBridge events, ");
|
||||
break;
|
||||
case 58: /* IvyBridge */
|
||||
case 62: /* IvyBridge EP */
|
||||
|
||||
case 58: /* 22nm IvyBridge */
|
||||
case 62: /* 22nm IvyBridge-EP/EX */
|
||||
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
/* dTLB-load-misses on IVB is different than SNB */
|
||||
|
@ -2539,11 +2540,11 @@ __init int intel_pmu_init(void)
|
|||
break;
|
||||
|
||||
|
||||
case 60: /* Haswell Client */
|
||||
case 70:
|
||||
case 71:
|
||||
case 60: /* 22nm Haswell */
|
||||
case 63:
|
||||
case 69:
|
||||
case 70:
|
||||
case 71:
|
||||
x86_pmu.late_ack = true;
|
||||
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
||||
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
|
||||
|
|
Loading…
Reference in New Issue