[TG3]: add 5780 basic jumbo frame support
Add basic jumbo frames support for 5780. This chip supports jumbo frames on the standard receive ring without the jumbo ring. The TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to indicate using the jumbo ring on 5704 and older chips. A new TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support with or without the jumbo ring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
4cf78e4fb6
commit
0f893dc6ec
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@ -90,7 +90,7 @@
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/* hardware minimum and maximum for a single frame's data payload */
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#define TG3_MIN_MTU 60
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#define TG3_MAX_MTU(tp) \
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(!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
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((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
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/* These numbers seem to be hard coded in the NIC firmware somehow.
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* You can't change the ring sizes, but you can change where you place
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@ -914,7 +914,7 @@ out:
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if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
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/* Cannot do read-modify-write on 5401 */
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
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} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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} else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
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u32 phy_reg;
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/* Set bit 14 with read-modify-write to preserve other bits */
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@ -926,7 +926,7 @@ out:
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/* Set phy register 0x10 bit 0 to high fifo elasticity to support
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* jumbo frames transmission.
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*/
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
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u32 phy_reg;
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if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
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@ -3444,9 +3444,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
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dev->mtu = new_mtu;
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if (new_mtu > ETH_DATA_LEN)
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tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
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tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
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else
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tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
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tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
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}
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static int tg3_change_mtu(struct net_device *dev, int new_mtu)
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@ -3588,7 +3588,7 @@ static void tg3_init_rings(struct tg3 *tp)
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(i << RXD_OPAQUE_INDEX_SHIFT));
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}
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if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
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if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
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for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
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struct tg3_rx_buffer_desc *rxd;
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@ -3609,7 +3609,7 @@ static void tg3_init_rings(struct tg3 *tp)
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break;
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}
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if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
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if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
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for (i = 0; i < tp->rx_jumbo_pending; i++) {
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if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
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-1, i) < 0)
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@ -5277,7 +5277,7 @@ static int tg3_reset_hw(struct tg3 *tp)
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}
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#endif
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if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
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if (tp->dev->mtu <= ETH_DATA_LEN) {
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tw32(BUFMGR_MB_RDMA_LOW_WATER,
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tp->bufmgr_config.mbuf_read_dma_low_water);
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tw32(BUFMGR_MB_MACRX_LOW_WATER,
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@ -5352,7 +5352,7 @@ static int tg3_reset_hw(struct tg3 *tp)
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/* Setup replenish threshold. */
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tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
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if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
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if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
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tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
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((u64) tp->rx_jumbo_mapping >> 32));
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tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
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@ -5413,7 +5413,7 @@ static int tg3_reset_hw(struct tg3 *tp)
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tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
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tp->rx_std_ptr);
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tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
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tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
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tp->rx_jumbo_pending : 0;
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tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
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tp->rx_jumbo_ptr);
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@ -8991,6 +8991,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
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tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
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if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
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@ -9117,8 +9122,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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/* Derive initial jumbo mode from MTU assigned in
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* ether_setup() via the alloc_etherdev() call
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*/
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if (tp->dev->mtu > ETH_DATA_LEN)
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tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
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if (tp->dev->mtu > ETH_DATA_LEN &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
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tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
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/* Determine WakeOnLan speed to use. */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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@ -2125,7 +2125,7 @@ struct tg3 {
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#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
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#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
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#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
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#define TG3_FLAG_JUMBO_ENABLE 0x00800000
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#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
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#define TG3_FLAG_10_100_ONLY 0x01000000
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#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
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#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
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@ -2155,6 +2155,7 @@ struct tg3 {
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#define TG3_FLG2_5750_PLUS 0x00080000
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#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
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#define TG3_FLG2_USING_MSI 0x00200000
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#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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