powerpc/perf: Avoid spurious PMU interrupts after idle
POWER9 DD2 can see spurious PMU interrupts after state-loss idle in some conditions. A solution is to save and reload MMCR0 over state-loss idle. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Tested-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -30,6 +30,7 @@
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* Use unused space in the interrupt stack to save and restore
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* Use unused space in the interrupt stack to save and restore
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* registers for winkle support.
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* registers for winkle support.
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*/
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*/
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#define _MMCR0 GPR0
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#define _SDR1 GPR3
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#define _SDR1 GPR3
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#define _PTCR GPR3
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#define _PTCR GPR3
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#define _RPR GPR4
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#define _RPR GPR4
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@ -272,6 +273,14 @@ power_enter_stop:
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b pnv_wakeup_noloss
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b pnv_wakeup_noloss
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.Lhandle_esl_ec_set:
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.Lhandle_esl_ec_set:
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/*
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* POWER9 DD2 can incorrectly set PMAO when waking up after a
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* state-loss idle. Saving and restoring MMCR0 over idle is a
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* workaround.
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*/
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mfspr r4,SPRN_MMCR0
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std r4,_MMCR0(r1)
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/*
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/*
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* Check if the requested state is a deep idle state.
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* Check if the requested state is a deep idle state.
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*/
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*/
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@ -450,10 +459,14 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
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pnv_restore_hyp_resource_arch300:
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pnv_restore_hyp_resource_arch300:
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/*
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/*
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* Workaround for POWER9, if we lost resources, the ERAT
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* Workaround for POWER9, if we lost resources, the ERAT
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* might have been mixed up and needs flushing.
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* might have been mixed up and needs flushing. We also need
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* to reload MMCR0 (see comment above).
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*/
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*/
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blt cr3,1f
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blt cr3,1f
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PPC_INVALIDATE_ERAT
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PPC_INVALIDATE_ERAT
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ld r1,PACAR1(r13)
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ld r4,_MMCR0(r1)
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mtspr SPRN_MMCR0,r4
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1:
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1:
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/*
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/*
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* POWER ISA 3. Use PSSCR to determine if we
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* POWER ISA 3. Use PSSCR to determine if we
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