arm64 KVM fix: set the correct MDCR_EL2 register value on the first run
of a vCPU. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAl4xTDUACgkQa9axLQDI XvFVwxAAgaUudyEZrxpKJeueM4g0NcJ73Ahu+BrIft81ScKLsyaBE33Afnb6C8BG wkvUMYJCold7v741UE82oQ9y2R6P4lrr3MnvUhCwa6iR+HmakWJ1hes5M20rLAh6 u/GSXJxwhJaOLWAVjDNrCRP4HNyYVsXTxo+mCeYuz30+k/tfMzrKhbOBEfYp2zVS mpxoA2MccANl/sOvATXSkOh7z4bBct7FHj72PiAb0WFM2nuBP9h+8Jd6C3WwgW7B VWuoF/qKFGl1IK3IQ+RQCcvlAEVpX4dz8RqxWX+mseoQpVEI0RjAykdypJOCJ/W6 2E0BTwV5bNJzEU23fuM08YsGn0scQjjiEByyAbi+zEb4lZdlFjaHQHxlj4BNtzzK eCHK0LSy+DNWzVgEr2Bm4eGAM753zJ8LH04oOqhn01yKJ15CDGD4vNgUy03PXyTX iHpbMnUSUbgGVsaqpFb9jSq6dIToy8zGv5xwHOSa77UM1bSyn01n1aMAdC3MjWWI SKW0bh34hmdhbaeZV3V2tchiYHiv8CyLsBdxy4IpcZeOSpzw5mRo3HdkVrPbFwYB YSWUyQHXj5Xo6yAvs+MOMl1zS1aG0zgk5b5cCeewSHVHeiaxJBvcqSEXO29a/mwz x2ObZy6NMXKcOVuuOiTGCUW8CWPLkg/4ANFi68F0lUG4vVZyEes= =eAJt -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 KVM fix from Catalin Marinas: "Set the correct MDCR_EL2 register value on the first run of a vCPU" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: KVM: arm64: Write arch.mdcr_el2 changes since last vcpu_load on VHE
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@ -101,7 +101,7 @@ void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu)
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void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
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{
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bool trap_debug = !(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY);
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unsigned long mdscr;
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unsigned long mdscr, orig_mdcr_el2 = vcpu->arch.mdcr_el2;
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trace_kvm_arm_setup_debug(vcpu, vcpu->guest_debug);
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@ -197,6 +197,10 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
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if (vcpu_read_sys_reg(vcpu, MDSCR_EL1) & (DBG_MDSCR_KDE | DBG_MDSCR_MDE))
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vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
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/* Write mdcr_el2 changes since vcpu_load on VHE systems */
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if (has_vhe() && orig_mdcr_el2 != vcpu->arch.mdcr_el2)
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write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
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trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2);
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trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_read_sys_reg(vcpu, MDSCR_EL1));
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}
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