ARM: davinci: add support for multiple power domains
On a new SoC based on DaVinci, there are multiple power domains similar to that in C6670 (c6x). Currently the clock module assumes that there are only two power domains (0 and 1). This patch removes this restriction to allow porting on to the new SoC. Reviewed-by :Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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caca6a03d3
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@ -31,19 +31,12 @@ static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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static DEFINE_MUTEX(clocks_mutex);
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static DEFINE_SPINLOCK(clockfw_lock);
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static DEFINE_SPINLOCK(clockfw_lock);
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static unsigned psc_domain(struct clk *clk)
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{
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return (clk->flags & PSC_DSP)
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? DAVINCI_GPSC_DSPDOMAIN
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: DAVINCI_GPSC_ARMDOMAIN;
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}
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static void __clk_enable(struct clk *clk)
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static void __clk_enable(struct clk *clk)
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{
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{
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if (clk->parent)
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if (clk->parent)
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__clk_enable(clk->parent);
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__clk_enable(clk->parent);
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if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
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if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
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davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
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davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
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true, clk->flags);
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true, clk->flags);
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}
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}
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@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk)
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return;
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return;
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if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
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if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
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(clk->flags & CLK_PSC))
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(clk->flags & CLK_PSC))
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davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
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davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
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false, clk->flags);
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false, clk->flags);
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if (clk->parent)
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if (clk->parent)
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__clk_disable(clk->parent);
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__clk_disable(clk->parent);
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@ -237,7 +230,7 @@ static int __init clk_disable_unused(void)
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pr_debug("Clocks: disable unused %s\n", ck->name);
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pr_debug("Clocks: disable unused %s\n", ck->name);
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davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
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davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
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false, ck->flags);
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false, ck->flags);
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}
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}
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spin_unlock_irq(&clockfw_lock);
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spin_unlock_irq(&clockfw_lock);
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@ -93,6 +93,7 @@ struct clk {
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u8 usecount;
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u8 usecount;
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u8 lpsc;
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u8 lpsc;
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u8 gpsc;
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u8 gpsc;
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u8 domain;
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u32 flags;
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u32 flags;
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struct clk *parent;
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struct clk *parent;
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struct list_head children; /* list of children */
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struct list_head children; /* list of children */
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@ -107,11 +108,10 @@ struct clk {
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/* Clock flags: SoC-specific flags start at BIT(16) */
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/* Clock flags: SoC-specific flags start at BIT(16) */
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#define ALWAYS_ENABLED BIT(1)
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#define ALWAYS_ENABLED BIT(1)
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#define CLK_PSC BIT(2)
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#define CLK_PSC BIT(2)
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#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
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#define CLK_PLL BIT(3) /* PLL-derived clock */
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#define CLK_PLL BIT(4) /* PLL-derived clock */
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#define PRE_PLL BIT(4) /* source is before PLL mult/div */
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#define PRE_PLL BIT(5) /* source is before PLL mult/div */
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#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
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#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
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#define PSC_FORCE BIT(6) /* Force module state transtition */
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#define PSC_FORCE BIT(7) /* Force module state transtition */
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#define CLK(dev, con, ck) \
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#define CLK(dev, con, ck) \
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{ \
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{ \
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@ -130,7 +130,7 @@ static struct clk dsp_clk = {
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.name = "dsp",
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.name = "dsp",
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.parent = &pll1_sysclk1,
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_GEM,
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.lpsc = DAVINCI_LPSC_GEM,
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.flags = PSC_DSP,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.usecount = 1, /* REVISIT how to disable? */
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.usecount = 1, /* REVISIT how to disable? */
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};
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};
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@ -145,7 +145,7 @@ static struct clk vicp_clk = {
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.name = "vicp",
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.name = "vicp",
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.parent = &pll1_sysclk2,
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_IMCOP,
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.lpsc = DAVINCI_LPSC_IMCOP,
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.flags = PSC_DSP,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.usecount = 1, /* REVISIT how to disable? */
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.usecount = 1, /* REVISIT how to disable? */
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};
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};
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