GenWQE PCI support, health monitoring and recovery
Module initialization and PCIe setup. Card health monitoring and
recovery functionality. Character device creation and deletion are
controlled from here.
Signed-off-by: Frank Haverkamp <haver@linux.vnet.ibm.com>
Co-authors: Joerg-Stephan Vogt <jsvogt@de.ibm.com>,
Michael Jung <MIJUNG@de.ibm.com>,
Michael Ruettger <michael@ibmra.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Frank Haverkamp
Greg Kroah-Hartman
parent
e7f5f275c6
commit
12eb468325
File diff suppressed because it is too large
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#ifndef __CARD_BASE_H__
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#define __CARD_BASE_H__
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/**
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* IBM Accelerator Family 'GenWQE'
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*
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* (C) Copyright IBM Corp. 2013
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*
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* Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
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* Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
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* Author: Michael Jung <mijung@de.ibm.com>
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* Author: Michael Ruettger <michael@ibmra.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License (version 2 only)
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Interfaces within the GenWQE module. Defines genwqe_card and
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* ddcb_queue as well as ddcb_requ.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/cdev.h>
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#include <linux/stringify.h>
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#include <linux/pci.h>
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#include <linux/semaphore.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <linux/version.h>
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#include <linux/debugfs.h>
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#include <linux/genwqe/genwqe_card.h>
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#include "genwqe_driver.h"
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#define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */
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#define GENWQE_FLAG_MSI_ENABLED (1 << 0)
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#define GENWQE_MAX_VFS 15 /* maximum 15 VFs are possible */
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#define GENWQE_MAX_FUNCS 16 /* 1 PF and 15 VFs */
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#define GENWQE_CARD_NO_MAX (16 * GENWQE_MAX_FUNCS)
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/* Compile parameters, some of them appear in debugfs for later adjustment */
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#define genwqe_ddcb_max 32 /* DDCBs on the work-queue */
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#define genwqe_polling_enabled 0 /* in case of irqs not working */
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#define genwqe_ddcb_software_timeout 10 /* timeout per DDCB in seconds */
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#define genwqe_kill_timeout 8 /* time until process gets killed */
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#define genwqe_vf_jobtimeout_msec 250 /* 250 msec */
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#define genwqe_pf_jobtimeout_msec 8000 /* 8 sec should be ok */
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#define genwqe_health_check_interval 4 /* <= 0: disabled */
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/* Sysfs attribute groups used when we create the genwqe device */
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extern const struct attribute_group *genwqe_attribute_groups[];
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/*
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* Config space for Genwqe5 A7:
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* 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00
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* 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00
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* 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04]
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* 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
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*/
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#define PCI_DEVICE_GENWQE 0x044b /* Genwqe DeviceID */
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#define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */
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#define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */
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#define PCI_CLASSCODE_GENWQE5 0x1200 /* UNKNOWN */
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#define PCI_SUBVENDOR_ID_IBM_SRIOV 0x0000
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#define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */
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#define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */
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#define GENWQE_SLU_ARCH_REQ 2 /* Required SLU architecture level */
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/**
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* struct genwqe_reg - Genwqe data dump functionality
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*/
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struct genwqe_reg {
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u32 addr;
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u32 idx;
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u64 val;
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};
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/*
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* enum genwqe_dbg_type - Specify chip unit to dump/debug
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*/
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enum genwqe_dbg_type {
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GENWQE_DBG_UNIT0 = 0, /* captured before prev errs cleared */
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GENWQE_DBG_UNIT1 = 1,
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GENWQE_DBG_UNIT2 = 2,
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GENWQE_DBG_UNIT3 = 3,
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GENWQE_DBG_UNIT4 = 4,
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GENWQE_DBG_UNIT5 = 5,
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GENWQE_DBG_UNIT6 = 6,
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GENWQE_DBG_UNIT7 = 7,
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GENWQE_DBG_REGS = 8,
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GENWQE_DBG_DMA = 9,
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GENWQE_DBG_UNITS = 10, /* max number of possible debug units */
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};
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/* Software error injection to simulate card failures */
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#define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */
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#define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */
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#define GENWQE_INJECT_GFIR_FATAL 0x00000004 /* GFIR = 0x0000ffff */
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#define GENWQE_INJECT_GFIR_INFO 0x00000008 /* GFIR = 0xffff0000 */
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/*
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* Genwqe card description and management data.
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*
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* Error-handling in case of card malfunction
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* ------------------------------------------
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*
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* If the card is detected to be defective the outside environment
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* will cause the PCI layer to call deinit (the cleanup function for
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* probe). This is the same effect like doing a unbind/bind operation
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* on the card.
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*
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* The genwqe card driver implements a health checking thread which
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* verifies the card function. If this detects a problem the cards
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* device is being shutdown and restarted again, along with a reset of
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* the card and queue.
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*
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* All functions accessing the card device return either -EIO or -ENODEV
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* code to indicate the malfunction to the user. The user has to close
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* the file descriptor and open a new one, once the card becomes
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* available again.
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*
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* If the open file descriptor is setup to receive SIGIO, the signal is
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* genereated for the application which has to provide a handler to
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* react on it. If the application does not close the open
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* file descriptor a SIGKILL is send to enforce freeing the cards
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* resources.
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*
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* I did not find a different way to prevent kernel problems due to
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* reference counters for the cards character devices getting out of
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* sync. The character device deallocation does not block, even if
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* there is still an open file descriptor pending. If this pending
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* descriptor is closed, the data structures used by the character
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* device is reinstantiated, which will lead to the reference counter
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* dropping below the allowed values.
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*
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* Card recovery
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* -------------
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*
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* To test the internal driver recovery the following command can be used:
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* sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject'
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*/
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/**
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* struct dma_mapping_type - Mapping type definition
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*
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* To avoid memcpying data arround we use user memory directly. To do
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* this we need to pin/swap-in the memory and request a DMA address
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* for it.
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*/
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enum dma_mapping_type {
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GENWQE_MAPPING_RAW = 0, /* contignous memory buffer */
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GENWQE_MAPPING_SGL_TEMP, /* sglist dynamically used */
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GENWQE_MAPPING_SGL_PINNED, /* sglist used with pinning */
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};
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/**
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* struct dma_mapping - Information about memory mappings done by the driver
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*/
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struct dma_mapping {
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enum dma_mapping_type type;
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void *u_vaddr; /* user-space vaddr/non-aligned */
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void *k_vaddr; /* kernel-space vaddr/non-aligned */
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dma_addr_t dma_addr; /* physical DMA address */
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struct page **page_list; /* list of pages used by user buff */
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dma_addr_t *dma_list; /* list of dma addresses per page */
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unsigned int nr_pages; /* number of pages */
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unsigned int size; /* size in bytes */
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struct list_head card_list; /* list of usr_maps for card */
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struct list_head pin_list; /* list of pinned memory for dev */
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};
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static inline void genwqe_mapping_init(struct dma_mapping *m,
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enum dma_mapping_type type)
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{
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memset(m, 0, sizeof(*m));
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m->type = type;
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}
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/**
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* struct ddcb_queue - DDCB queue data
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* @ddcb_max: Number of DDCBs on the queue
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* @ddcb_next: Next free DDCB
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* @ddcb_act: Next DDCB supposed to finish
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* @ddcb_seq: Sequence number of last DDCB
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* @ddcbs_in_flight: Currently enqueued DDCBs
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* @ddcbs_completed: Number of already completed DDCBs
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* @busy: Number of -EBUSY returns
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* @ddcb_daddr: DMA address of first DDCB in the queue
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* @ddcb_vaddr: Kernel virtual address of first DDCB in the queue
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* @ddcb_req: Associated requests (one per DDCB)
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* @ddcb_waitqs: Associated wait queues (one per DDCB)
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* @ddcb_lock: Lock to protect queuing operations
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* @ddcb_waitq: Wait on next DDCB finishing
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*/
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struct ddcb_queue {
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int ddcb_max; /* amount of DDCBs */
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int ddcb_next; /* next available DDCB num */
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int ddcb_act; /* DDCB to be processed */
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u16 ddcb_seq; /* slc seq num */
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unsigned int ddcbs_in_flight; /* number of ddcbs in processing */
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unsigned int ddcbs_completed;
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unsigned int ddcbs_max_in_flight;
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unsigned int busy; /* how many times -EBUSY? */
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dma_addr_t ddcb_daddr; /* DMA address */
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struct ddcb *ddcb_vaddr; /* kernel virtual addr for DDCBs */
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struct ddcb_requ **ddcb_req; /* ddcb processing parameter */
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wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */
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spinlock_t ddcb_lock; /* exclusive access to queue */
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wait_queue_head_t ddcb_waitq; /* wait for ddcb processing */
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/* registers or the respective queue to be used */
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u32 IO_QUEUE_CONFIG;
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u32 IO_QUEUE_STATUS;
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u32 IO_QUEUE_SEGMENT;
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u32 IO_QUEUE_INITSQN;
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u32 IO_QUEUE_WRAP;
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u32 IO_QUEUE_OFFSET;
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u32 IO_QUEUE_WTIME;
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u32 IO_QUEUE_ERRCNTS;
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u32 IO_QUEUE_LRW;
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};
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/*
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* GFIR, SLU_UNITCFG, APP_UNITCFG
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* 8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC.
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*/
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#define GENWQE_FFDC_REGS (3 + (8 * (2 + 2 * 64)))
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struct genwqe_ffdc {
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unsigned int entries;
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struct genwqe_reg *regs;
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};
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/**
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* struct genwqe_dev - GenWQE device information
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* @card_state: Card operation state, see above
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* @ffdc: First Failure Data Capture buffers for each unit
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* @card_thread: Working thread to operate the DDCB queue
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* @card_waitq: Wait queue used in card_thread
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* @queue: DDCB queue
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* @health_thread: Card monitoring thread (only for PFs)
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* @health_waitq: Wait queue used in health_thread
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* @pci_dev: Associated PCI device (function)
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* @mmio: Base address of 64-bit register space
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* @mmio_len: Length of register area
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* @file_lock: Lock to protect access to file_list
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* @file_list: List of all processes with open GenWQE file descriptors
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*
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* This struct contains all information needed to communicate with a
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* GenWQE card. It is initialized when a GenWQE device is found and
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* destroyed when it goes away. It holds data to maintain the queue as
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* well as data needed to feed the user interfaces.
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*/
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struct genwqe_dev {
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enum genwqe_card_state card_state;
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spinlock_t print_lock;
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int card_idx; /* card index 0..CARD_NO_MAX-1 */
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u64 flags; /* general flags */
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/* FFDC data gathering */
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struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS];
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/* DDCB workqueue */
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struct task_struct *card_thread;
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wait_queue_head_t queue_waitq;
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struct ddcb_queue queue; /* genwqe DDCB queue */
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unsigned int irqs_processed;
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/* Card health checking thread */
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struct task_struct *health_thread;
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wait_queue_head_t health_waitq;
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/* char device */
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dev_t devnum_genwqe; /* major/minor num card */
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struct class *class_genwqe; /* reference to class object */
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struct device *dev; /* for device creation */
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struct cdev cdev_genwqe; /* char device for card */
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struct dentry *debugfs_root; /* debugfs card root directory */
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struct dentry *debugfs_genwqe; /* debugfs driver root directory */
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/* pci resources */
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struct pci_dev *pci_dev; /* PCI device */
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void __iomem *mmio; /* BAR-0 MMIO start */
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unsigned long mmio_len;
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u16 num_vfs;
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u32 vf_jobtimeout_msec[GENWQE_MAX_VFS];
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int is_privileged; /* access to all regs possible */
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/* config regs which we need often */
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u64 slu_unitcfg;
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u64 app_unitcfg;
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u64 softreset;
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u64 err_inject;
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u64 last_gfir;
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char app_name[5];
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spinlock_t file_lock; /* lock for open files */
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struct list_head file_list; /* list of open files */
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/* debugfs parameters */
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int ddcb_software_timeout; /* wait until DDCB times out */
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int skip_recovery; /* circumvention if recovery fails */
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int kill_timeout; /* wait after sending SIGKILL */
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};
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/**
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* enum genwqe_requ_state - State of a DDCB execution request
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*/
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enum genwqe_requ_state {
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GENWQE_REQU_NEW = 0,
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GENWQE_REQU_ENQUEUED = 1,
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GENWQE_REQU_TAPPED = 2,
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GENWQE_REQU_FINISHED = 3,
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GENWQE_REQU_STATE_MAX,
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};
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/**
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* struct ddcb_requ - Kernel internal representation of the DDCB request
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* @cmd: User space representation of the DDCB execution request
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*/
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struct ddcb_requ {
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/* kernel specific content */
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enum genwqe_requ_state req_state; /* request status */
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int num; /* ddcb_no for this request */
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struct ddcb_queue *queue; /* associated queue */
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struct dma_mapping dma_mappings[DDCB_FIXUPS];
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struct sg_entry *sgl[DDCB_FIXUPS];
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dma_addr_t sgl_dma_addr[DDCB_FIXUPS];
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size_t sgl_size[DDCB_FIXUPS];
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/* kernel/user shared content */
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struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */
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struct genwqe_debug_data debug_data;
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};
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/**
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* struct genwqe_file - Information for open GenWQE devices
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*/
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struct genwqe_file {
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struct genwqe_dev *cd;
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struct genwqe_driver *client;
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struct file *filp;
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struct fasync_struct *async_queue;
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struct task_struct *owner;
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struct list_head list; /* entry in list of open files */
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spinlock_t map_lock; /* lock for dma_mappings */
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struct list_head map_list; /* list of dma_mappings */
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spinlock_t pin_lock; /* lock for pinned memory */
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struct list_head pin_list; /* list of pinned memory */
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};
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int genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */
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int genwqe_finish_queue(struct genwqe_dev *cd);
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int genwqe_release_service_layer(struct genwqe_dev *cd);
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/**
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* genwqe_get_slu_id() - Read Service Layer Unit Id
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* Return: 0x00: Development code
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* 0x01: SLC1 (old)
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* 0x02: SLC2 (sept2012)
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* 0x03: SLC2 (feb2013, generic driver)
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*/
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static inline int genwqe_get_slu_id(struct genwqe_dev *cd)
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{
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return (int)((cd->slu_unitcfg >> 32) & 0xff);
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}
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int genwqe_ddcbs_in_flight(struct genwqe_dev *cd);
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u8 genwqe_card_type(struct genwqe_dev *cd);
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int genwqe_card_reset(struct genwqe_dev *cd);
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int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count);
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void genwqe_reset_interrupt_capability(struct genwqe_dev *cd);
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int genwqe_device_create(struct genwqe_dev *cd);
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int genwqe_device_remove(struct genwqe_dev *cd);
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/* debugfs */
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int genwqe_init_debugfs(struct genwqe_dev *cd);
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void genqwe_exit_debugfs(struct genwqe_dev *cd);
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int genwqe_read_softreset(struct genwqe_dev *cd);
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/* Hardware Circumventions */
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int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd);
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int genwqe_flash_readback_fails(struct genwqe_dev *cd);
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/**
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* genwqe_write_vreg() - Write register in VF window
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* @cd: genwqe device
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* @reg: register address
|
||||
* @val: value to write
|
||||
* @func: 0: PF, 1: VF0, ..., 15: VF14
|
||||
*/
|
||||
int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func);
|
||||
|
||||
/**
|
||||
* genwqe_read_vreg() - Read register in VF window
|
||||
* @cd: genwqe device
|
||||
* @reg: register address
|
||||
* @func: 0: PF, 1: VF0, ..., 15: VF14
|
||||
*
|
||||
* Return: content of the register
|
||||
*/
|
||||
u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func);
|
||||
|
||||
/* FFDC Buffer Management */
|
||||
int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id);
|
||||
int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id,
|
||||
struct genwqe_reg *regs, unsigned int max_regs);
|
||||
int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs,
|
||||
unsigned int max_regs, int all);
|
||||
int genwqe_ffdc_dump_dma(struct genwqe_dev *cd,
|
||||
struct genwqe_reg *regs, unsigned int max_regs);
|
||||
|
||||
int genwqe_init_debug_data(struct genwqe_dev *cd,
|
||||
struct genwqe_debug_data *d);
|
||||
|
||||
void genwqe_init_crc32(void);
|
||||
int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len);
|
||||
|
||||
/* Memory allocation/deallocation; dma address handling */
|
||||
int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m,
|
||||
void *uaddr, unsigned long size,
|
||||
struct ddcb_requ *req);
|
||||
|
||||
int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m,
|
||||
struct ddcb_requ *req);
|
||||
|
||||
struct sg_entry *genwqe_alloc_sgl(struct genwqe_dev *cd, int num_pages,
|
||||
dma_addr_t *dma_addr, size_t *sgl_size);
|
||||
|
||||
void genwqe_free_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list,
|
||||
dma_addr_t dma_addr, size_t size);
|
||||
|
||||
int genwqe_setup_sgl(struct genwqe_dev *cd,
|
||||
unsigned long offs,
|
||||
unsigned long size,
|
||||
struct sg_entry *sgl, /* genwqe sgl */
|
||||
dma_addr_t dma_addr, size_t sgl_size,
|
||||
dma_addr_t *dma_list, int page_offs, int num_pages);
|
||||
|
||||
int genwqe_check_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list,
|
||||
int size);
|
||||
|
||||
static inline bool dma_mapping_used(struct dma_mapping *m)
|
||||
{
|
||||
if (!m)
|
||||
return 0;
|
||||
return m->size != 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* __genwqe_execute_ddcb() - Execute DDCB request with addr translation
|
||||
*
|
||||
* This function will do the address translation changes to the DDCBs
|
||||
* according to the definitions required by the ATS field. It looks up
|
||||
* the memory allocation buffer or does vmap/vunmap for the respective
|
||||
* user-space buffers, inclusive page pinning and scatter gather list
|
||||
* buildup and teardown.
|
||||
*/
|
||||
int __genwqe_execute_ddcb(struct genwqe_dev *cd,
|
||||
struct genwqe_ddcb_cmd *cmd);
|
||||
|
||||
/**
|
||||
* __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation
|
||||
*
|
||||
* This version will not do address translation or any modifcation of
|
||||
* the DDCB data. It is used e.g. for the MoveFlash DDCB which is
|
||||
* entirely prepared by the driver itself. That means the appropriate
|
||||
* DMA addresses are already in the DDCB and do not need any
|
||||
* modification.
|
||||
*/
|
||||
int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd,
|
||||
struct genwqe_ddcb_cmd *cmd);
|
||||
|
||||
int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
|
||||
int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
|
||||
int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
|
||||
|
||||
/* register access */
|
||||
int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val);
|
||||
u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs);
|
||||
int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val);
|
||||
u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs);
|
||||
|
||||
void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,
|
||||
dma_addr_t *dma_handle);
|
||||
void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size,
|
||||
void *vaddr, dma_addr_t dma_handle);
|
||||
|
||||
/* Base clock frequency in MHz */
|
||||
int genwqe_base_clock_frequency(struct genwqe_dev *cd);
|
||||
|
||||
/* Before FFDC is captured the traps should be stopped. */
|
||||
void genwqe_stop_traps(struct genwqe_dev *cd);
|
||||
void genwqe_start_traps(struct genwqe_dev *cd);
|
||||
|
||||
/* Hardware circumvention */
|
||||
bool genwqe_need_err_masking(struct genwqe_dev *cd);
|
||||
|
||||
/**
|
||||
* genwqe_is_privileged() - Determine operation mode for PCI function
|
||||
*
|
||||
* On Intel with SRIOV support we see:
|
||||
* PF: is_physfn = 1 is_virtfn = 0
|
||||
* VF: is_physfn = 0 is_virtfn = 1
|
||||
*
|
||||
* On Systems with no SRIOV support _and_ virtualized systems we get:
|
||||
* is_physfn = 0 is_virtfn = 0
|
||||
*
|
||||
* Other vendors have individual pci device ids to distinguish between
|
||||
* virtual function drivers and physical function drivers. GenWQE
|
||||
* unfortunately has just on pci device id for both, VFs and PF.
|
||||
*
|
||||
* The following code is used to distinguish if the card is running in
|
||||
* privileged mode, either as true PF or in a virtualized system with
|
||||
* full register access e.g. currently on PowerPC.
|
||||
*
|
||||
* if (pci_dev->is_virtfn)
|
||||
* cd->is_privileged = 0;
|
||||
* else
|
||||
* cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM)
|
||||
* != IO_ILLEGAL_VALUE);
|
||||
*/
|
||||
static inline int genwqe_is_privileged(struct genwqe_dev *cd)
|
||||
{
|
||||
return cd->is_privileged;
|
||||
}
|
||||
|
||||
#endif /* __CARD_BASE_H__ */
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#ifndef __GENWQE_DRIVER_H__
|
||||
#define __GENWQE_DRIVER_H__
|
||||
|
||||
/**
|
||||
* IBM Accelerator Family 'GenWQE'
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2013
|
||||
*
|
||||
* Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
|
||||
* Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
|
||||
* Author: Michael Jung <mijung@de.ibm.com>
|
||||
* Author: Michael Ruettger <michael@ibmra.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License (version 2 only)
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/iommu.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#include <linux/genwqe/genwqe_card.h>
|
||||
|
||||
#define DRV_VERS_STRING "2.0.0"
|
||||
|
||||
/*
|
||||
* Static minor number assignement, until we decide/implement
|
||||
* something dynamic.
|
||||
*/
|
||||
#define GENWQE_MAX_MINOR 128 /* up to 128 possible genwqe devices */
|
||||
|
||||
/**
|
||||
* genwqe_requ_alloc() - Allocate a new DDCB execution request
|
||||
*
|
||||
* This data structure contains the user visiable fields of the DDCB
|
||||
* to be executed.
|
||||
*
|
||||
* Return: ptr to genwqe_ddcb_cmd data structure
|
||||
*/
|
||||
struct genwqe_ddcb_cmd *ddcb_requ_alloc(void);
|
||||
|
||||
/**
|
||||
* ddcb_requ_free() - Free DDCB execution request.
|
||||
* @req: ptr to genwqe_ddcb_cmd data structure.
|
||||
*/
|
||||
void ddcb_requ_free(struct genwqe_ddcb_cmd *req);
|
||||
|
||||
u32 genwqe_crc32(u8 *buff, size_t len, u32 init);
|
||||
|
||||
static inline void genwqe_hexdump(struct pci_dev *pci_dev,
|
||||
const void *buff, unsigned int size)
|
||||
{
|
||||
char prefix[32];
|
||||
|
||||
scnprintf(prefix, sizeof(prefix), "%s %s: ",
|
||||
GENWQE_DEVNAME, pci_name(pci_dev));
|
||||
dynamic_hex_dump(prefix, DUMP_PREFIX_OFFSET, 16, 1, buff, size, true);
|
||||
}
|
||||
|
||||
#endif /* __GENWQE_DRIVER_H__ */
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
#ifndef __GENWQE_CARD_H__
|
||||
#define __GENWQE_CARD_H__
|
||||
|
||||
/**
|
||||
* IBM Accelerator Family 'GenWQE'
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2013
|
||||
*
|
||||
* Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
|
||||
* Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
|
||||
* Author: Michael Jung <mijung@de.ibm.com>
|
||||
* Author: Michael Ruettger <michael@ibmra.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License (version 2 only)
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* User-space API for the GenWQE card. For debugging and test purposes
|
||||
* the register addresses are included here too.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
/* Basename of sysfs, debugfs and /dev interfaces */
|
||||
#define GENWQE_DEVNAME "genwqe"
|
||||
|
||||
#define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
|
||||
#define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
|
||||
#define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
|
||||
#define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
|
||||
|
||||
/* MMIO Unit offsets: Each UnitID occupies a defined address range */
|
||||
#define GENWQE_UID_OFFS(uid) ((uid) << 24)
|
||||
#define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
|
||||
#define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1)
|
||||
#define GENWQE_APP_OFFS GENWQE_UID_OFFS(2)
|
||||
#define GENWQE_MAX_UNITS 3
|
||||
|
||||
/* Common offsets per UnitID */
|
||||
#define IO_EXTENDED_ERROR_POINTER 0x00000048
|
||||
#define IO_ERROR_INJECT_SELECTOR 0x00000060
|
||||
#define IO_EXTENDED_DIAG_SELECTOR 0x00000070
|
||||
#define IO_EXTENDED_DIAG_READ_MBX 0x00000078
|
||||
#define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
|
||||
|
||||
#define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) (((ring) << 8) | (trace))
|
||||
|
||||
/* UnitID 0: Service Layer Unit (SLU) */
|
||||
|
||||
/* SLU: Unit Configuration Register */
|
||||
#define IO_SLU_UNITCFG 0x00000000
|
||||
#define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 /* 27:20 */
|
||||
|
||||
/* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */
|
||||
#define IO_SLU_FIR 0x00000008 /* read only, wr direct */
|
||||
#define IO_SLU_FIR_CLR 0x00000010 /* read and clear */
|
||||
|
||||
/* SLU: First Error Capture Register (FEC/WOF) */
|
||||
#define IO_SLU_FEC 0x00000018
|
||||
|
||||
#define IO_SLU_ERR_ACT_MASK 0x00000020
|
||||
#define IO_SLU_ERR_ATTN_MASK 0x00000028
|
||||
#define IO_SLU_FIRX1_ACT_MASK 0x00000030
|
||||
#define IO_SLU_FIRX0_ACT_MASK 0x00000038
|
||||
#define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040
|
||||
#define IO_SLU_EXTENDED_ERR_PTR 0x00000048
|
||||
#define IO_SLU_COMMON_CONFIG 0x00000060
|
||||
|
||||
#define IO_SLU_FLASH_FIR 0x00000108
|
||||
#define IO_SLU_SLC_FIR 0x00000110
|
||||
#define IO_SLU_RIU_TRAP 0x00000280
|
||||
#define IO_SLU_FLASH_FEC 0x00000308
|
||||
#define IO_SLU_SLC_FEC 0x00000310
|
||||
|
||||
/*
|
||||
* The Virtual Function's Access is from offset 0x00010000
|
||||
* The Physical Function's Access is from offset 0x00050000
|
||||
* Single Shared Registers exists only at offset 0x00060000
|
||||
*
|
||||
* SLC: Queue Virtual Window Window for accessing into a specific VF
|
||||
* queue. When accessing the 0x10000 space using the 0x50000 address
|
||||
* segment, the value indicated here is used to specify which VF
|
||||
* register is decoded. This register, and the 0x50000 register space
|
||||
* can only be accessed by the PF. Example, if this register is set to
|
||||
* 0x2, then a read from 0x50000 is the same as a read from 0x10000
|
||||
* from VF=2.
|
||||
*/
|
||||
|
||||
/* SLC: Queue Segment */
|
||||
#define IO_SLC_QUEUE_SEGMENT 0x00010000
|
||||
#define IO_SLC_VF_QUEUE_SEGMENT 0x00050000
|
||||
|
||||
/* SLC: Queue Offset */
|
||||
#define IO_SLC_QUEUE_OFFSET 0x00010008
|
||||
#define IO_SLC_VF_QUEUE_OFFSET 0x00050008
|
||||
|
||||
/* SLC: Queue Configuration */
|
||||
#define IO_SLC_QUEUE_CONFIG 0x00010010
|
||||
#define IO_SLC_VF_QUEUE_CONFIG 0x00050010
|
||||
|
||||
/* SLC: Job Timout/Only accessible for the PF */
|
||||
#define IO_SLC_APPJOB_TIMEOUT 0x00010018
|
||||
#define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018
|
||||
#define TIMEOUT_250MS 0x0000000f
|
||||
#define HEARTBEAT_DISABLE 0x0000ff00
|
||||
|
||||
/* SLC: Queue InitSequence Register */
|
||||
#define IO_SLC_QUEUE_INITSQN 0x00010020
|
||||
#define IO_SLC_VF_QUEUE_INITSQN 0x00050020
|
||||
|
||||
/* SLC: Queue Wrap */
|
||||
#define IO_SLC_QUEUE_WRAP 0x00010028
|
||||
#define IO_SLC_VF_QUEUE_WRAP 0x00050028
|
||||
|
||||
/* SLC: Queue Status */
|
||||
#define IO_SLC_QUEUE_STATUS 0x00010100
|
||||
#define IO_SLC_VF_QUEUE_STATUS 0x00050100
|
||||
|
||||
/* SLC: Queue Working Time */
|
||||
#define IO_SLC_QUEUE_WTIME 0x00010030
|
||||
#define IO_SLC_VF_QUEUE_WTIME 0x00050030
|
||||
|
||||
/* SLC: Queue Error Counts */
|
||||
#define IO_SLC_QUEUE_ERRCNTS 0x00010038
|
||||
#define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038
|
||||
|
||||
/* SLC: Queue Loast Response Word */
|
||||
#define IO_SLC_QUEUE_LRW 0x00010040
|
||||
#define IO_SLC_VF_QUEUE_LRW 0x00050040
|
||||
|
||||
/* SLC: Freerunning Timer */
|
||||
#define IO_SLC_FREE_RUNNING_TIMER 0x00010108
|
||||
#define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108
|
||||
|
||||
/* SLC: Queue Virtual Access Region */
|
||||
#define IO_PF_SLC_VIRTUAL_REGION 0x00050000
|
||||
|
||||
/* SLC: Queue Virtual Window */
|
||||
#define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000
|
||||
|
||||
/* SLC: DDCB Application Job Pending [n] (n=0:63) */
|
||||
#define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8*(n))
|
||||
#define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n)
|
||||
|
||||
/* SLC: Parser Trap RAM [n] (n=0:31) */
|
||||
#define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8*(n))
|
||||
|
||||
/* SLC: Dispatcher Trap RAM [n] (n=0:31) */
|
||||
#define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n))
|
||||
|
||||
/* Global Fault Isolation Register (GFIR) */
|
||||
#define IO_SLC_CFGREG_GFIR 0x00020000
|
||||
#define GFIR_ERR_TRIGGER 0x0000ffff
|
||||
|
||||
/* SLU: Soft Reset Register */
|
||||
#define IO_SLC_CFGREG_SOFTRESET 0x00020018
|
||||
|
||||
/* SLU: Misc Debug Register */
|
||||
#define IO_SLC_MISC_DEBUG 0x00020060
|
||||
#define IO_SLC_MISC_DEBUG_CLR 0x00020068
|
||||
#define IO_SLC_MISC_DEBUG_SET 0x00020070
|
||||
|
||||
/* Temperature Sensor Reading */
|
||||
#define IO_SLU_TEMPERATURE_SENSOR 0x00030000
|
||||
#define IO_SLU_TEMPERATURE_CONFIG 0x00030008
|
||||
|
||||
/* Voltage Margining Control */
|
||||
#define IO_SLU_VOLTAGE_CONTROL 0x00030080
|
||||
#define IO_SLU_VOLTAGE_NOMINAL 0x00000000
|
||||
#define IO_SLU_VOLTAGE_DOWN5 0x00000006
|
||||
#define IO_SLU_VOLTAGE_UP5 0x00000007
|
||||
|
||||
/* Direct LED Control Register */
|
||||
#define IO_SLU_LEDCONTROL 0x00030100
|
||||
|
||||
/* SLU: Flashbus Direct Access -A5 */
|
||||
#define IO_SLU_FLASH_DIRECTACCESS 0x00040010
|
||||
|
||||
/* SLU: Flashbus Direct Access2 -A5 */
|
||||
#define IO_SLU_FLASH_DIRECTACCESS2 0x00040020
|
||||
|
||||
/* SLU: Flashbus Command Interface -A5 */
|
||||
#define IO_SLU_FLASH_CMDINTF 0x00040030
|
||||
|
||||
/* SLU: BitStream Loaded */
|
||||
#define IO_SLU_BITSTREAM 0x00040040
|
||||
|
||||
/* This Register has a switch which will change the CAs to UR */
|
||||
#define IO_HSU_ERR_BEHAVIOR 0x01001010
|
||||
|
||||
#define IO_SLC2_SQB_TRAP 0x00062000
|
||||
#define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008
|
||||
#define IO_SLC2_FLS_MASTER_TRAP 0x00062010
|
||||
|
||||
/* UnitID 1: HSU Registers */
|
||||
#define IO_HSU_UNITCFG 0x01000000
|
||||
#define IO_HSU_FIR 0x01000008
|
||||
#define IO_HSU_FIR_CLR 0x01000010
|
||||
#define IO_HSU_FEC 0x01000018
|
||||
#define IO_HSU_ERR_ACT_MASK 0x01000020
|
||||
#define IO_HSU_ERR_ATTN_MASK 0x01000028
|
||||
#define IO_HSU_FIRX1_ACT_MASK 0x01000030
|
||||
#define IO_HSU_FIRX0_ACT_MASK 0x01000038
|
||||
#define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040
|
||||
#define IO_HSU_EXTENDED_ERR_PTR 0x01000048
|
||||
#define IO_HSU_COMMON_CONFIG 0x01000060
|
||||
|
||||
/* UnitID 2: Application Unit (APP) */
|
||||
#define IO_APP_UNITCFG 0x02000000
|
||||
#define IO_APP_FIR 0x02000008
|
||||
#define IO_APP_FIR_CLR 0x02000010
|
||||
#define IO_APP_FEC 0x02000018
|
||||
#define IO_APP_ERR_ACT_MASK 0x02000020
|
||||
#define IO_APP_ERR_ATTN_MASK 0x02000028
|
||||
#define IO_APP_FIRX1_ACT_MASK 0x02000030
|
||||
#define IO_APP_FIRX0_ACT_MASK 0x02000038
|
||||
#define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040
|
||||
#define IO_APP_EXTENDED_ERR_PTR 0x02000048
|
||||
#define IO_APP_COMMON_CONFIG 0x02000060
|
||||
|
||||
#define IO_APP_DEBUG_REG_01 0x02010000
|
||||
#define IO_APP_DEBUG_REG_02 0x02010008
|
||||
#define IO_APP_DEBUG_REG_03 0x02010010
|
||||
#define IO_APP_DEBUG_REG_04 0x02010018
|
||||
#define IO_APP_DEBUG_REG_05 0x02010020
|
||||
#define IO_APP_DEBUG_REG_06 0x02010028
|
||||
#define IO_APP_DEBUG_REG_07 0x02010030
|
||||
#define IO_APP_DEBUG_REG_08 0x02010038
|
||||
#define IO_APP_DEBUG_REG_09 0x02010040
|
||||
#define IO_APP_DEBUG_REG_10 0x02010048
|
||||
#define IO_APP_DEBUG_REG_11 0x02010050
|
||||
#define IO_APP_DEBUG_REG_12 0x02010058
|
||||
#define IO_APP_DEBUG_REG_13 0x02010060
|
||||
#define IO_APP_DEBUG_REG_14 0x02010068
|
||||
#define IO_APP_DEBUG_REG_15 0x02010070
|
||||
#define IO_APP_DEBUG_REG_16 0x02010078
|
||||
#define IO_APP_DEBUG_REG_17 0x02010080
|
||||
#define IO_APP_DEBUG_REG_18 0x02010088
|
||||
|
||||
/* Read/write from/to registers */
|
||||
struct genwqe_reg_io {
|
||||
__u64 num; /* register offset/address */
|
||||
__u64 val64;
|
||||
};
|
||||
|
||||
/*
|
||||
* All registers of our card will return values not equal this values.
|
||||
* If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the
|
||||
* card can be considered as unusable. It will need recovery.
|
||||
*/
|
||||
#define IO_ILLEGAL_VALUE 0xffffffffffffffffull
|
||||
|
||||
/*
|
||||
* Generic DDCB execution interface.
|
||||
*
|
||||
* This interface is a first prototype resulting from discussions we
|
||||
* had with other teams which wanted to use the Genwqe card. It allows
|
||||
* to issue a DDCB request in a generic way. The request will block
|
||||
* until it finishes or time out with error.
|
||||
*
|
||||
* Some DDCBs require DMA addresses to be specified in the ASIV
|
||||
* block. The interface provies the capability to let the kernel
|
||||
* driver know where those addresses are by specifying the ATS field,
|
||||
* such that it can replace the user-space addresses with appropriate
|
||||
* DMA addresses or DMA addresses of a scatter gather list which is
|
||||
* dynamically created.
|
||||
*
|
||||
* Our hardware will refuse DDCB execution if the ATS field is not as
|
||||
* expected. That means the DDCB execution engine in the chip knows
|
||||
* where it expects DMA addresses within the ASIV part of the DDCB and
|
||||
* will check that against the ATS field definition. Any invalid or
|
||||
* unknown ATS content will lead to DDCB refusal.
|
||||
*/
|
||||
|
||||
/* Genwqe chip Units */
|
||||
#define DDCB_ACFUNC_SLU 0x00 /* chip service layer unit */
|
||||
#define DDCB_ACFUNC_APP 0x01 /* chip application */
|
||||
|
||||
/* DDCB return codes (RETC) */
|
||||
#define DDCB_RETC_IDLE 0x0000 /* Unexecuted/DDCB created */
|
||||
#define DDCB_RETC_PENDING 0x0101 /* Pending Execution */
|
||||
#define DDCB_RETC_COMPLETE 0x0102 /* Cmd complete. No error */
|
||||
#define DDCB_RETC_FAULT 0x0104 /* App Err, recoverable */
|
||||
#define DDCB_RETC_ERROR 0x0108 /* App Err, non-recoverable */
|
||||
#define DDCB_RETC_FORCED_ERROR 0x01ff /* overwritten by driver */
|
||||
|
||||
#define DDCB_RETC_UNEXEC 0x0110 /* Unexe/Removed from queue */
|
||||
#define DDCB_RETC_TERM 0x0120 /* Terminated */
|
||||
#define DDCB_RETC_RES0 0x0140 /* Reserved */
|
||||
#define DDCB_RETC_RES1 0x0180 /* Reserved */
|
||||
|
||||
/* DDCB Command Options (CMDOPT) */
|
||||
#define DDCB_OPT_ECHO_FORCE_NO 0x0000 /* ECHO DDCB */
|
||||
#define DDCB_OPT_ECHO_FORCE_102 0x0001 /* force return code */
|
||||
#define DDCB_OPT_ECHO_FORCE_104 0x0002
|
||||
#define DDCB_OPT_ECHO_FORCE_108 0x0003
|
||||
|
||||
#define DDCB_OPT_ECHO_FORCE_110 0x0004 /* only on PF ! */
|
||||
#define DDCB_OPT_ECHO_FORCE_120 0x0005
|
||||
#define DDCB_OPT_ECHO_FORCE_140 0x0006
|
||||
#define DDCB_OPT_ECHO_FORCE_180 0x0007
|
||||
|
||||
#define DDCB_OPT_ECHO_COPY_NONE (0 << 5)
|
||||
#define DDCB_OPT_ECHO_COPY_ALL (1 << 5)
|
||||
|
||||
/* Definitions of Service Layer Commands */
|
||||
#define SLCMD_ECHO_SYNC 0x00 /* PF/VF */
|
||||
#define SLCMD_MOVE_FLASH 0x06 /* PF only */
|
||||
#define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */
|
||||
#define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 /* mode: download */
|
||||
#define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 /* mode: emulation */
|
||||
#define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 /* mode: upload */
|
||||
#define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 /* mode: verify */
|
||||
#define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2)/* just dump DDCB and exit */
|
||||
#define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3)/* wait for RETC >= 0102 */
|
||||
#define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4)
|
||||
#define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5)
|
||||
|
||||
enum genwqe_card_state {
|
||||
GENWQE_CARD_UNUSED = 0,
|
||||
GENWQE_CARD_USED = 1,
|
||||
GENWQE_CARD_FATAL_ERROR = 2,
|
||||
GENWQE_CARD_STATE_MAX,
|
||||
};
|
||||
|
||||
/* common struct for chip image exchange */
|
||||
struct genwqe_bitstream {
|
||||
__u64 data_addr; /* pointer to image data */
|
||||
__u32 size; /* size of image file */
|
||||
__u32 crc; /* crc of this image */
|
||||
__u64 target_addr; /* starting address in Flash */
|
||||
__u32 partition; /* '0', '1', or 'v' */
|
||||
__u32 uid; /* 1=host/x=dram */
|
||||
|
||||
__u64 slu_id; /* informational/sim: SluID */
|
||||
__u64 app_id; /* informational/sim: AppID */
|
||||
|
||||
__u16 retc; /* returned from processing */
|
||||
__u16 attn; /* attention code from processing */
|
||||
__u32 progress; /* progress code from processing */
|
||||
};
|
||||
|
||||
/* Issuing a specific DDCB command */
|
||||
#define DDCB_LENGTH 256 /* for debug data */
|
||||
#define DDCB_ASIV_LENGTH 104 /* len of the DDCB ASIV array */
|
||||
#define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
|
||||
#define DDCB_ASV_LENGTH 64 /* len of the DDCB ASV array */
|
||||
#define DDCB_FIXUPS 12 /* maximum number of fixups */
|
||||
|
||||
struct genwqe_debug_data {
|
||||
char driver_version[64];
|
||||
__u64 slu_unitcfg;
|
||||
__u64 app_unitcfg;
|
||||
|
||||
__u8 ddcb_before[DDCB_LENGTH];
|
||||
__u8 ddcb_prev[DDCB_LENGTH];
|
||||
__u8 ddcb_finished[DDCB_LENGTH];
|
||||
};
|
||||
|
||||
/*
|
||||
* Address Translation Specification (ATS) definitions
|
||||
*
|
||||
* Each 4 bit within the ATS 64-bit word specify the required address
|
||||
* translation at the defined offset.
|
||||
*
|
||||
* 63 LSB
|
||||
* 6666.5555.5555.5544.4444.4443.3333.3333 ... 11
|
||||
* 3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210
|
||||
*
|
||||
* offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78
|
||||
* res res res res ASIV ...
|
||||
* The first 4 entries in the ATS word are reserved. The following nibbles
|
||||
* each describe at an 8 byte offset the format of the required data.
|
||||
*/
|
||||
#define ATS_TYPE_DATA 0x0ull /* data */
|
||||
#define ATS_TYPE_FLAT_RD 0x4ull /* flat buffer read only */
|
||||
#define ATS_TYPE_FLAT_RDWR 0x5ull /* flat buffer read/write */
|
||||
#define ATS_TYPE_SGL_RD 0x6ull /* sgl read only */
|
||||
#define ATS_TYPE_SGL_RDWR 0x7ull /* sgl read/write */
|
||||
|
||||
#define ATS_SET_FLAGS(_struct, _field, _flags) \
|
||||
(((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8))))
|
||||
|
||||
#define ATS_GET_FLAGS(_ats, _byte_offs) \
|
||||
(((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf)
|
||||
|
||||
/**
|
||||
* struct genwqe_ddcb_cmd - User parameter for generic DDCB commands
|
||||
*
|
||||
* On the way into the kernel the driver will read the whole data
|
||||
* structure. On the way out the driver will not copy the ASIV data
|
||||
* back to user-space.
|
||||
*/
|
||||
struct genwqe_ddcb_cmd {
|
||||
/* START of data copied to/from driver */
|
||||
__u64 next_addr; /* chaining genwqe_ddcb_cmd */
|
||||
__u64 flags; /* reserved */
|
||||
|
||||
__u8 acfunc; /* accelerators functional unit */
|
||||
__u8 cmd; /* command to execute */
|
||||
__u8 asiv_length; /* used parameter length */
|
||||
__u8 asv_length; /* length of valid return values */
|
||||
__u16 cmdopts; /* command options */
|
||||
__u16 retc; /* return code from processing */
|
||||
|
||||
__u16 attn; /* attention code from processing */
|
||||
__u16 vcrc; /* variant crc16 */
|
||||
__u32 progress; /* progress code from processing */
|
||||
|
||||
__u64 deque_ts; /* dequeue time stamp */
|
||||
__u64 cmplt_ts; /* completion time stamp */
|
||||
__u64 disp_ts; /* SW processing start */
|
||||
|
||||
/* move to end and avoid copy-back */
|
||||
__u64 ddata_addr; /* collect debug data */
|
||||
|
||||
/* command specific values */
|
||||
__u8 asv[DDCB_ASV_LENGTH];
|
||||
|
||||
/* END of data copied from driver */
|
||||
union {
|
||||
struct {
|
||||
__u64 ats;
|
||||
__u8 asiv[DDCB_ASIV_LENGTH_ATS];
|
||||
};
|
||||
/* used for flash update to keep it backward compatible */
|
||||
__u8 __asiv[DDCB_ASIV_LENGTH];
|
||||
};
|
||||
/* END of data copied to driver */
|
||||
};
|
||||
|
||||
#define GENWQE_IOC_CODE 0xa5
|
||||
|
||||
/* Access functions */
|
||||
#define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io)
|
||||
#define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io)
|
||||
#define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io)
|
||||
#define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io)
|
||||
#define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io)
|
||||
#define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io)
|
||||
|
||||
#define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state)
|
||||
|
||||
/**
|
||||
* struct genwqe_mem - Memory pinning/unpinning information
|
||||
* @addr: virtual user space address
|
||||
* @size: size of the area pin/dma-map/unmap
|
||||
* direction: 0: read/1: read and write
|
||||
*
|
||||
* Avoid pinning and unpinning of memory pages dynamically. Instead
|
||||
* the idea is to pin the whole buffer space required for DDCB
|
||||
* opertionas in advance. The driver will reuse this pinning and the
|
||||
* memory associated with it to setup the sglists for the DDCB
|
||||
* requests without the need to allocate and free memory or map and
|
||||
* unmap to get the DMA addresses.
|
||||
*
|
||||
* The inverse operation needs to be called after the pinning is not
|
||||
* needed anymore. The pinnings else the pinnings will get removed
|
||||
* after the device is closed. Note that pinnings will required
|
||||
* memory.
|
||||
*/
|
||||
struct genwqe_mem {
|
||||
__u64 addr;
|
||||
__u64 size;
|
||||
__u64 direction;
|
||||
__u64 flags;
|
||||
};
|
||||
|
||||
#define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem)
|
||||
#define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem)
|
||||
|
||||
/*
|
||||
* Generic synchronous DDCB execution interface.
|
||||
* Synchronously execute a DDCB.
|
||||
*
|
||||
* Return: 0 on success or negative error code.
|
||||
* -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups
|
||||
* no mappings found/could not create mappings
|
||||
* -EFAULT: illegal addresses in fixups, purging failed
|
||||
* -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE
|
||||
*/
|
||||
#define GENWQE_EXECUTE_DDCB \
|
||||
_IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd)
|
||||
|
||||
#define GENWQE_EXECUTE_RAW_DDCB \
|
||||
_IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd)
|
||||
|
||||
/* Service Layer functions (PF only) */
|
||||
#define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream)
|
||||
#define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream)
|
||||
|
||||
#endif /* __GENWQE_CARD_H__ */
|
||||
Loading…
Reference in New Issue