powerpc/85xx: Save scratch registers to thread info instead of using SPRGs.
We expect this is actually faster, and we end up needing more space than we can get from the SPRGs in some instances. This is also useful when running as a guest OS - SPRGs4-7 do not have guest versions. 8 slots are allocated in thread_info for this even though we only actually use 4 of them - this allows space for future code to have more scratch space (and we know we'll need it for things like hugetlb). Signed-off-by: Ashish Kalra <Ashish.Kalra@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Ashish Kalra
Kumar Gala
parent
dc2c9c52b6
commit
1325a684b5
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@ -20,6 +20,7 @@
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/cache.h>
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#include <asm/ptrace.h>
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#include <asm/types.h>
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@ -156,6 +157,10 @@ struct thread_struct {
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#endif
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struct pt_regs *regs; /* Pointer to saved register state */
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mm_segment_t fs; /* for get_fs() validation */
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#ifdef CONFIG_BOOKE
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/* BookE base exception scratch space; align on cacheline */
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unsigned long normsave[8] ____cacheline_aligned;
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#endif
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#ifdef CONFIG_PPC32
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void *pgdir; /* root of page-table tree */
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#endif
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@ -872,8 +872,8 @@
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#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
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#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
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#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
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#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R
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#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W
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#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
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#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
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#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
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#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
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#ifdef CONFIG_E200
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@ -82,6 +82,9 @@ int main(void)
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DEFINE(KSP, offsetof(struct thread_struct, ksp));
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DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
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DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
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#ifdef CONFIG_BOOKE
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DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
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#endif
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DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
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DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0]));
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DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr));
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@ -20,33 +20,43 @@
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addi reg,reg,val@l
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#endif
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/*
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* Macro used to get to thread save registers.
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* Note that entries 0-3 are used for the prolog code, and the remaining
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* entries are available for specific exception use in the event a handler
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* requires more than 4 scratch registers.
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*/
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#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
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#define NORMAL_EXCEPTION_PROLOG \
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mtspr SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\
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mtspr SPRN_SPRG_WSCRATCH1,r11; \
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mtspr SPRN_SPRG_WSCRATCH2,r1; \
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mfcr r10; /* save CR in r10 for now */\
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mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
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mfspr r10, SPRN_SPRG_THREAD; \
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stw r11, THREAD_NORMSAVE(0)(r10); \
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stw r13, THREAD_NORMSAVE(2)(r10); \
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mfcr r13; /* save CR in r13 for now */\
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mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
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andi. r11,r11,MSR_PR; \
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mr r11, r1; \
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beq 1f; \
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mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\
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lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
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ALLOC_STACK_FRAME(r1, THREAD_SIZE); \
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1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
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mr r11,r1; \
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stw r10,_CCR(r11); /* save various registers */\
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/* if from user, start at top of this thread's kernel stack */ \
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lwz r11, THREAD_INFO-THREAD(r10); \
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ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
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1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
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stw r13, _CCR(r11); /* save various registers */ \
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stw r12,GPR12(r11); \
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stw r9,GPR9(r11); \
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mfspr r10,SPRN_SPRG_RSCRATCH0; \
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stw r10,GPR10(r11); \
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mfspr r12,SPRN_SPRG_RSCRATCH1; \
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mfspr r13, SPRN_SPRG_RSCRATCH0; \
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stw r13, GPR10(r11); \
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lwz r12, THREAD_NORMSAVE(0)(r10); \
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stw r12,GPR11(r11); \
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lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
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mflr r10; \
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stw r10,_LINK(r11); \
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mfspr r10,SPRN_SPRG_RSCRATCH2; \
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mfspr r12,SPRN_SRR0; \
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stw r10,GPR1(r11); \
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stw r1, GPR1(r11); \
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mfspr r9,SPRN_SRR1; \
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stw r10,0(r11); \
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stw r1, 0(r11); \
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mr r1, r11; \
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rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
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stw r0,GPR0(r11); \
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lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
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@ -346,11 +346,12 @@ interrupt_base:
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/* Data TLB Error Interrupt */
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START_EXCEPTION(DataTLBError)
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mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
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mtspr SPRN_SPRG_WSCRATCH1, r11
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mtspr SPRN_SPRG_WSCRATCH2, r12
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mtspr SPRN_SPRG_WSCRATCH3, r13
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mfcr r11
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mtspr SPRN_SPRG_WSCRATCH4, r11
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mfspr r10, SPRN_SPRG_THREAD
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stw r11, THREAD_NORMSAVE(0)(r10)
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stw r12, THREAD_NORMSAVE(1)(r10)
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stw r13, THREAD_NORMSAVE(2)(r10)
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mfcr r13
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stw r13, THREAD_NORMSAVE(3)(r10)
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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@ -416,11 +417,12 @@ interrupt_base:
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/* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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mfspr r11, SPRN_SPRG_RSCRATCH4
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mfspr r10, SPRN_SPRG_THREAD
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lwz r11, THREAD_NORMSAVE(3)(r10)
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mtcr r11
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mfspr r13, SPRN_SPRG_RSCRATCH3
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mfspr r12, SPRN_SPRG_RSCRATCH2
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mfspr r11, SPRN_SPRG_RSCRATCH1
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lwz r13, THREAD_NORMSAVE(2)(r10)
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lwz r12, THREAD_NORMSAVE(1)(r10)
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lwz r11, THREAD_NORMSAVE(0)(r10)
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mfspr r10, SPRN_SPRG_RSCRATCH0
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b DataStorage
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@ -432,11 +434,12 @@ interrupt_base:
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*/
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START_EXCEPTION(InstructionTLBError)
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mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
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mtspr SPRN_SPRG_WSCRATCH1, r11
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mtspr SPRN_SPRG_WSCRATCH2, r12
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mtspr SPRN_SPRG_WSCRATCH3, r13
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mfcr r11
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mtspr SPRN_SPRG_WSCRATCH4, r11
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mfspr r10, SPRN_SPRG_THREAD
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stw r11, THREAD_NORMSAVE(0)(r10)
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stw r12, THREAD_NORMSAVE(1)(r10)
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stw r13, THREAD_NORMSAVE(2)(r10)
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mfcr r13
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stw r13, THREAD_NORMSAVE(3)(r10)
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mfspr r10, SPRN_SRR0 /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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@ -496,11 +499,12 @@ interrupt_base:
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/* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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mfspr r11, SPRN_SPRG_RSCRATCH4
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mfspr r10, SPRN_SPRG_THREAD
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lwz r11, THREAD_NORMSAVE(3)(r10)
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mtcr r11
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mfspr r13, SPRN_SPRG_RSCRATCH3
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mfspr r12, SPRN_SPRG_RSCRATCH2
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mfspr r11, SPRN_SPRG_RSCRATCH1
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lwz r13, THREAD_NORMSAVE(2)(r10)
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lwz r12, THREAD_NORMSAVE(1)(r10)
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lwz r11, THREAD_NORMSAVE(0)(r10)
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mfspr r10, SPRN_SPRG_RSCRATCH0
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b InstructionStorage
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@ -621,11 +625,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
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tlbwe
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/* Done...restore registers and get out of here. */
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mfspr r11, SPRN_SPRG_RSCRATCH4
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mfspr r10, SPRN_SPRG_THREAD
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lwz r11, THREAD_NORMSAVE(3)(r10)
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mtcr r11
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mfspr r13, SPRN_SPRG_RSCRATCH3
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mfspr r12, SPRN_SPRG_RSCRATCH2
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mfspr r11, SPRN_SPRG_RSCRATCH1
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lwz r13, THREAD_NORMSAVE(2)(r10)
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lwz r12, THREAD_NORMSAVE(1)(r10)
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lwz r11, THREAD_NORMSAVE(0)(r10)
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mfspr r10, SPRN_SPRG_RSCRATCH0
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rfi /* Force context change */
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