Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] AACI: timeout will reach -1 [ARM] Storage class should be before const qualifier [ARM] pxa: stop and disable IRQ for each DMA channels at startup [ARM] pxa: make more SSCR0 bit definitions visible on multiple processors [ARM] pxa: fix missing of __REG() definition for ac97 registers access [ARM] pxa: fix NAND and MMC clock initialization for pxa3xx
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commit
1385a7ae65
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@ -13,8 +13,8 @@
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#include <asm/cacheflush.h>
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#include <asm/mach-types.h>
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const extern unsigned char relocate_new_kernel[];
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const extern unsigned int relocate_new_kernel_size;
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extern const unsigned char relocate_new_kernel[];
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extern const unsigned int relocate_new_kernel_size;
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extern void setup_mm_for_reboot(char mode);
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@ -121,6 +121,16 @@ int __init pxa_init_dma(int num_ch)
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if (dma_channels == NULL)
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return -ENOMEM;
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/* dma channel priorities on pxa2xx processors:
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* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
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* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
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* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
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*/
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for (i = 0; i < num_ch; i++) {
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DCSR(i) = 0;
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dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
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}
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ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
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if (ret) {
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printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
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@ -128,14 +138,6 @@ int __init pxa_init_dma(int num_ch)
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return ret;
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}
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/* dma channel priorities on pxa2xx processors:
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* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
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* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
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* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
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*/
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for (i = 0; i < num_ch; i++)
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dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
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num_dma_channels = num_ch;
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return 0;
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}
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@ -1,6 +1,8 @@
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#ifndef __ASM_ARCH_REGS_AC97_H
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#define __ASM_ARCH_REGS_AC97_H
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#include <mach/hardware.h>
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/*
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* AC97 Controller registers
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*/
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@ -41,6 +41,9 @@
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#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
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#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
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#endif
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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#define SSCR0_EDSS (1 << 20) /* Extended data size select */
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#define SSCR0_NCS (1 << 21) /* Network clock select */
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#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
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@ -88,13 +88,13 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
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static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
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static struct clk_lookup common_clkregs[] = {
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INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", "NANDCLK"),
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INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
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};
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static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
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static struct clk_lookup pxa310_clkregs[] = {
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INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", "MMCCLK"),
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INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
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};
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static int __init pxa300_init(void)
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@ -83,7 +83,7 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
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static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
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static struct clk_lookup pxa320_clkregs[] = {
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INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", "NANDCLK"),
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INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
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};
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static int __init pxa320_init(void)
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@ -90,7 +90,7 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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*/
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do {
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v = readl(aaci->base + AACI_SLFR);
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} while ((v & (SLFR_1TXB|SLFR_2TXB)) && timeout--);
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} while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
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if (!timeout)
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dev_err(&aaci->dev->dev,
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@ -126,7 +126,7 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
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*/
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do {
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v = readl(aaci->base + AACI_SLFR);
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} while ((v & SLFR_1TXB) && timeout--);
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} while ((v & SLFR_1TXB) && --timeout);
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if (!timeout) {
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dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
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@ -147,7 +147,7 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
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do {
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cond_resched();
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v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
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} while ((v != (SLFR_1RXV|SLFR_2RXV)) && timeout--);
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} while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
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if (!timeout) {
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dev_err(&aaci->dev->dev, "timeout on RX valid\n");
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