ARM: ixp4xx: use __iomem pointers for MMIO
ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. At the moment, this patch conflicts with other patches in linux-next, need to sort this out. Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx;
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*************************************************************************/
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*************************************************************************/
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static struct map_desc ixp4xx_io_desc[] __initdata = {
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static struct map_desc ixp4xx_io_desc[] __initdata = {
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{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
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{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
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.virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
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.virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
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.pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
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.length = IXP4XX_PERIPHERAL_REGION_SIZE,
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.length = IXP4XX_PERIPHERAL_REGION_SIZE,
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.type = MT_DEVICE
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.type = MT_DEVICE
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}, { /* Expansion Bus Config Registers */
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}, { /* Expansion Bus Config Registers */
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.virtual = IXP4XX_EXP_CFG_BASE_VIRT,
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.virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
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.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
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.length = IXP4XX_EXP_CFG_REGION_SIZE,
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.length = IXP4XX_EXP_CFG_REGION_SIZE,
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.type = MT_DEVICE
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.type = MT_DEVICE
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}, { /* PCI Registers */
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}, { /* PCI Registers */
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.virtual = IXP4XX_PCI_CFG_BASE_VIRT,
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.virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
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.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
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.length = IXP4XX_PCI_CFG_REGION_SIZE,
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.length = IXP4XX_PCI_CFG_REGION_SIZE,
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.type = MT_DEVICE
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.type = MT_DEVICE
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},
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},
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#ifdef CONFIG_DEBUG_LL
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#ifdef CONFIG_DEBUG_LL
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{ /* Debug UART mapping */
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{ /* Debug UART mapping */
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.virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
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.virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
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.pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
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.length = IXP4XX_DEBUG_UART_REGION_SIZE,
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.length = IXP4XX_DEBUG_UART_REGION_SIZE,
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.type = MT_DEVICE
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.type = MT_DEVICE
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@ -14,6 +14,7 @@
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#ifndef __ASM_ARCH_CPU_H__
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#ifndef __ASM_ARCH_CPU_H__
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#define __ASM_ARCH_CPU_H__
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#define __ASM_ARCH_CPU_H__
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <asm/cputype.h>
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/* Processor id value in CP15 Register 0 */
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/* Processor id value in CP15 Register 0 */
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@ -37,7 +38,7 @@
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static inline u32 ixp4xx_read_feature_bits(void)
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static inline u32 ixp4xx_read_feature_bits(void)
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{
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{
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u32 val = ~*IXP4XX_EXP_CFG2;
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u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
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if (cpu_is_ixp42x_rev_a0())
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if (cpu_is_ixp42x_rev_a0())
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return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
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return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
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@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
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static inline void ixp4xx_write_feature_bits(u32 value)
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static inline void ixp4xx_write_feature_bits(u32 value)
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{
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{
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*IXP4XX_EXP_CFG2 = ~value;
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__raw_writel(~value, IXP4XX_EXP_CFG2);
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}
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}
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#endif /* _ASM_ARCH_CPU_H */
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#endif /* _ASM_ARCH_CPU_H */
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@ -49,21 +49,21 @@
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* Expansion BUS Configuration registers
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* Expansion BUS Configuration registers
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*/
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*/
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#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
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#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
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#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
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#define IXP4XX_EXP_CFG_BASE_VIRT IOMEM(0xFFBFE000)
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#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
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#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
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/*
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/*
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* PCI Config registers
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* PCI Config registers
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*/
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*/
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#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
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#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
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#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
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#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFFBFF000)
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#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
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#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
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/*
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/*
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* Peripheral space
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* Peripheral space
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*/
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*/
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#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
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#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
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#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
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#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFFBEB000)
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#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
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#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
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/*
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/*
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@ -73,7 +73,7 @@
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* aligned so that it * can be used with the low-level debug code.
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* aligned so that it * can be used with the low-level debug code.
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*/
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*/
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#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
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#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
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#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
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#define IXP4XX_DEBUG_UART_BASE_VIRT IOMEM(0xffb00000)
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#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
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#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
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#define IXP4XX_EXP_CS0_OFFSET 0x00
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#define IXP4XX_EXP_CS0_OFFSET 0x00
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@ -92,7 +92,7 @@
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/*
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/*
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* Expansion Bus Controller registers.
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* Expansion Bus Controller registers.
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*/
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*/
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#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
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#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
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#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
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#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
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#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
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#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
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