ARM: dts: meson: fix PHY deassert timing requirements

[ Upstream commit 656ab1bdcd2b755dc161a9774201100d5bf74b8d ]

According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. On similar boards with the same PHY this fixes an issue where
Ethernet link would not come up when using ip link set down/up.

Fixes: a2c6e82e53 ("ARM: dts: meson: switch to the generic Ethernet PHY reset bindings")
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # on Odroid-C1+
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/ff78772b306411e145769c46d4090554344db41e.1607363522.git.stefan@agner.ch
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Stefan Agner 2020-12-07 18:58:01 +01:00 committed by Greg Kroah-Hartman
parent 154105c0ba
commit 13f4c61d2f
2 changed files with 2 additions and 2 deletions

View File

@ -219,7 +219,7 @@
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;

View File

@ -83,7 +83,7 @@
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
};
};