Merge branch 'clk-stm32mp1' into clk-fixes
* clk-stm32mp1: clk: stm32mp1: remove ck_apb_dbg clock clk: stm32mp1: set stgen_k clock as critical clk: stm32mp1: add missing tzc2 clock clk: stm32mp1: fix SAI3 & SAI4 clocks clk: stm32mp1: remove unused dfsdm_src[] const clk: stm32mp1: add missing static
This commit is contained in:
Stephen Boyd
commit
1486776535
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@ -216,7 +216,7 @@ static const char * const usart1_src[] = {
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"pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
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};
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const char * const usart234578_src[] = {
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static const char * const usart234578_src[] = {
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"pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
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};
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@ -224,10 +224,6 @@ static const char * const usart6_src[] = {
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"pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
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};
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static const char * const dfsdm_src[] = {
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"pclk2", "ck_mcu"
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};
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static const char * const fdcan_src[] = {
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"ck_hse", "pll3_q", "pll4_q"
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};
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@ -316,10 +312,8 @@ struct stm32_clk_mgate {
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struct clock_config {
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u32 id;
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const char *name;
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union {
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const char *parent_name;
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const char * const *parent_names;
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};
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const char *parent_name;
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const char * const *parent_names;
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int num_parents;
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unsigned long flags;
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void *cfg;
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@ -469,7 +463,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
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}
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}
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const struct clk_ops mp1_gate_clk_ops = {
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static const struct clk_ops mp1_gate_clk_ops = {
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.enable = mp1_gate_clk_enable,
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.disable = mp1_gate_clk_disable,
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.is_enabled = clk_gate_is_enabled,
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@ -698,7 +692,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
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mp1_gate_clk_disable(hw);
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}
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const struct clk_ops mp1_mgate_clk_ops = {
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static const struct clk_ops mp1_mgate_clk_ops = {
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.enable = mp1_mgate_clk_enable,
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.disable = mp1_mgate_clk_disable,
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.is_enabled = clk_gate_is_enabled,
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@ -732,7 +726,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
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return 0;
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}
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const struct clk_ops clk_mmux_ops = {
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static const struct clk_ops clk_mmux_ops = {
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.get_parent = clk_mmux_get_parent,
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.set_parent = clk_mmux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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@ -1048,10 +1042,10 @@ struct stm32_pll_cfg {
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u32 offset;
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};
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struct clk_hw *_clk_register_pll(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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static struct clk_hw *_clk_register_pll(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
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@ -1405,7 +1399,8 @@ enum {
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G_USBH,
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G_ETHSTP,
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G_RTCAPB,
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G_TZC,
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G_TZC1,
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G_TZC2,
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G_TZPC,
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G_IWDG1,
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G_BSEC,
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@ -1417,7 +1412,7 @@ enum {
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G_LAST
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};
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struct stm32_mgate mp1_mgate[G_LAST];
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static struct stm32_mgate mp1_mgate[G_LAST];
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#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
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_mgate, _ops)\
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@ -1440,7 +1435,7 @@ struct stm32_mgate mp1_mgate[G_LAST];
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&mp1_mgate[_id], &mp1_mgate_clk_ops)
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/* Peripheral gates */
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struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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/* Multi gates */
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K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
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K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
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@ -1506,7 +1501,8 @@ struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
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K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
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K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
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K_GATE(G_TZC, RCC_APB5ENSETR, 12, 0),
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K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
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K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
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K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
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K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
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K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
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@ -1600,7 +1596,7 @@ enum {
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M_LAST
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};
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struct stm32_mmux ker_mux[M_LAST];
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static struct stm32_mmux ker_mux[M_LAST];
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#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
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[_id] = {\
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@ -1623,7 +1619,7 @@ struct stm32_mmux ker_mux[M_LAST];
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_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
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&ker_mux[_id], &clk_mmux_ops)
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const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
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static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
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/* Kernel multi mux */
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K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
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K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
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@ -1860,7 +1856,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
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PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
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CLK_IS_CRITICAL, G_RTCAPB),
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PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
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PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
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PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
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PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
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PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
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PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
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@ -1916,8 +1913,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
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KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
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KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
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KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IGNORE_UNUSED,
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G_STGEN, M_STGEN),
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KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
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KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
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KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
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KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
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@ -1948,8 +1944,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
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KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
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KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
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KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
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KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
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KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
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KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
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KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
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KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
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KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
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@ -1992,10 +1988,6 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
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/* Debug clocks */
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FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
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GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
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GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
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COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
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@ -76,7 +76,7 @@
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#define I2C6 63
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#define USART1 64
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#define RTCAPB 65
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#define TZC 66
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#define TZC1 66
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#define TZPC 67
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#define IWDG1 68
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#define BSEC 69
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@ -123,6 +123,7 @@
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#define CRC1 110
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#define USBH 111
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#define ETHSTP 112
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#define TZC2 113
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/* Kernel clocks */
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#define SDMMC1_K 118
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@ -228,7 +229,6 @@
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#define CK_MCO2 212
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/* TRACE & DEBUG clocks */
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#define DBG 213
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#define CK_DBG 214
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#define CK_TRACE 215
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