thermal: samsung: Add TMU support for Exynos5420 SoCs
Exynos5420 has 5 TMU channels, the TRIMINFO register is misplaced for TMU channels 2, 3 and 4 TRIMINFO at 0x1006c000 contains data for TMU channel 3 TRIMINFO at 0x100a0000 contains data for TMU channel 4 TRIMINFO at 0x10068000 contains data for TMU channel 2 This patch 1 Adds the neccessary register changes and arch information to support Exynos5420 SoCs. 2. Handles the gate clock for misplaced TRIMINFO register 3. Updates the Documentation at Documentation/devicetree/bindings/thermal/exynos-thermal.txt Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Naveen Krishna Chatradhi
Eduardo Valentin
parent
9025d563cd
commit
14a11dc7e0
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@ -6,6 +6,9 @@
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"samsung,exynos4412-tmu"
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"samsung,exynos4210-tmu"
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"samsung,exynos5250-tmu"
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"samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
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"samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
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Exynos5420 (Must pass triminfo base and triminfo clock)
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"samsung,exynos5440-tmu"
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- interrupt-parent : The phandle for the interrupt controller
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- reg : Address range of the thermal registers. For soc's which has multiple
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@ -13,9 +16,24 @@
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interrupt related then 2 set of register has to supplied. First set
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belongs to register set of TMU instance and second set belongs to
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registers shared with the TMU instance.
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NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
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channels 2, 3 and 4
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Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
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register, also provide clock to access that base.
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TRIMINFO at 0x1006c000 contains data for TMU channel 3
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TRIMINFO at 0x100a0000 contains data for TMU channel 4
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TRIMINFO at 0x10068000 contains data for TMU channel 2
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- interrupts : Should contain interrupt for thermal system
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- clocks : The main clock for TMU device
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- clocks : The main clocks for TMU device
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-- 1. operational clock for TMU channel
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-- 2. optional clock to access the shared registers of TMU channel
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- clock-names : Thermal system clock name
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-- "tmu_apbif" operational clock for current TMU channel
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-- "tmu_triminfo_apbif" clock to access the shared triminfo register
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for current TMU channel
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- vtmu-supply: This entry is optional and provides the regulator node supplying
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voltage to TMU. If needed this entry can be placed inside
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board/platform specific dts file.
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@ -43,6 +61,31 @@ Example 2):
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clock-names = "tmu_apbif";
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};
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Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
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tmu_cpu2: tmu@10068000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x10068000 0x100>, <0x1006c000 0x4>;
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interrupts = <0 184 0>;
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clocks = <&clock 318>, <&clock 318>;
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clock-names = "tmu_apbif", "tmu_triminfo_apbif";
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};
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tmu_cpu3: tmu@1006c000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
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interrupts = <0 185 0>;
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clocks = <&clock 318>, <&clock 319>;
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clock-names = "tmu_apbif", "tmu_triminfo_apbif";
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};
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tmu_gpu: tmu@100a0000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x100a0000 0x100>, <0x10068000 0x4>;
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interrupts = <0 215 0>;
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clocks = <&clock 319>, <&clock 318>;
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clock-names = "tmu_apbif", "tmu_triminfo_apbif";
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};
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Note: For multi-instance tmu each instance should have an alias correctly
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numbered in "aliases" node.
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@ -47,6 +47,7 @@
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* @irq_work: pointer to the irq work structure.
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* @lock: lock to implement synchronization.
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* @clk: pointer to the clock structure.
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* @clk_sec: pointer to the clock structure for accessing the base_second.
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* @temp_error1: fused value of the first point trim.
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* @temp_error2: fused value of the second point trim.
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* @regulator: pointer to the TMU regulator structure.
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@ -61,7 +62,7 @@ struct exynos_tmu_data {
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enum soc_type soc;
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struct work_struct irq_work;
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struct mutex lock;
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struct clk *clk;
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struct clk *clk, *clk_sec;
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u8 temp_error1, temp_error2;
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struct regulator *regulator;
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struct thermal_sensor_conf *reg_conf;
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@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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if (TMU_SUPPORTS(pdata, READY_STATUS)) {
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status = readb(data->base + reg->tmu_status);
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@ -186,7 +189,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
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}
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} else {
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trim_info = readl(data->base + reg->triminfo_data);
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/* On exynos5420 the triminfo register is in the shared space */
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if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
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trim_info = readl(data->base_second +
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reg->triminfo_data);
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else
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trim_info = readl(data->base + reg->triminfo_data);
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}
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
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@ -302,6 +310,8 @@ skip_calib_data:
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out:
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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return ret;
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}
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@ -453,12 +463,16 @@ static void exynos_tmu_work(struct work_struct *work)
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int val_irq, val_type;
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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/* Find which sensor generated this interrupt */
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if (reg->tmu_irqstatus) {
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val_type = readl(data->base_second + reg->tmu_irqstatus);
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if (!((val_type >> data->id) & 0x1))
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goto out;
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}
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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exynos_report_trigger(data->reg_conf);
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mutex_lock(&data->lock);
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@ -498,6 +512,14 @@ static const struct of_device_id exynos_tmu_match[] = {
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.compatible = "samsung,exynos5250-tmu",
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.data = (void *)EXYNOS5250_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5420-tmu",
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.data = (void *)EXYNOS5420_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5420-tmu-ext-triminfo",
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.data = (void *)EXYNOS5420_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5440-tmu",
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.data = (void *)EXYNOS5440_TMU_DRV_DATA,
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@ -629,13 +651,30 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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return PTR_ERR(data->clk);
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}
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data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
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if (IS_ERR(data->clk_sec)) {
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if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
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dev_err(&pdev->dev, "Failed to get triminfo clock\n");
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return PTR_ERR(data->clk_sec);
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}
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} else {
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ret = clk_prepare(data->clk_sec);
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if (ret) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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return ret;
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}
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}
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ret = clk_prepare(data->clk);
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if (ret)
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return ret;
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if (ret) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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goto err_clk_sec;
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}
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if (pdata->type == SOC_ARCH_EXYNOS4210 ||
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pdata->type == SOC_ARCH_EXYNOS4412 ||
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pdata->type == SOC_ARCH_EXYNOS5250 ||
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pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
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pdata->type == SOC_ARCH_EXYNOS5440)
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data->soc = pdata->type;
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else {
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@ -704,6 +743,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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return 0;
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err_clk:
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clk_unprepare(data->clk);
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err_clk_sec:
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if (!IS_ERR(data->clk_sec))
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clk_unprepare(data->clk_sec);
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return ret;
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}
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@ -716,6 +758,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
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exynos_unregister_thermal(data->reg_conf);
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clk_unprepare(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_unprepare(data->clk_sec);
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if (!IS_ERR(data->regulator))
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regulator_disable(data->regulator);
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@ -43,6 +43,7 @@ enum soc_type {
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SOC_ARCH_EXYNOS4210 = 1,
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SOC_ARCH_EXYNOS4412,
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SOC_ARCH_EXYNOS5250,
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SOC_ARCH_EXYNOS5420_TRIMINFO,
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SOC_ARCH_EXYNOS5440,
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};
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@ -194,6 +194,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5420)
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static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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/* INTEN_RISE3 Not availble in exynos5420 */
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
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.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
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.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
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.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
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.emul_con = EXYNOS_EMUL_CON,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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#define __EXYNOS5420_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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.trigger_levels[1] = 103, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50, \
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.freq_tab[0] = { \
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.freq_clip_max = 800 * 1000, \
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.temp_level = 85, \
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}, \
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.freq_tab[1] = { \
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.freq_clip_max = 200 * 1000, \
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.temp_level = 103, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos5420_tmu_registers, \
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#define EXYNOS5420_TMU_DATA \
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__EXYNOS5420_TMU_DATA \
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.type = SOC_ARCH_EXYNOS5250, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME)
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#define EXYNOS5420_TMU_DATA_SHARED \
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__EXYNOS5420_TMU_DATA \
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.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
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struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5420_TMU_DATA },
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{ EXYNOS5420_TMU_DATA },
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{ EXYNOS5420_TMU_DATA_SHARED },
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{ EXYNOS5420_TMU_DATA_SHARED },
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{ EXYNOS5420_TMU_DATA_SHARED },
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},
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.tmu_count = 5,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
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@ -72,6 +72,7 @@
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#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
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#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
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#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
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#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT 16
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#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT 4
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#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
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#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
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@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
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#define EXYNOS5250_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS5420)
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extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
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#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
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#else
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#define EXYNOS5420_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
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#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
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