Timer fix for am33xx, runtime PM fix for UART, audio McBSP fixes,
mux and pinctrl fixes, and Beagle OPP fix. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQiDFhAAoJEBvUPslcq6VzWaoP/iLrCUkSv/7e3Y+r/59B7xPD D4Uco/7dBE7m8ropaDgeLJRugXCF3SCJjDaHwKhQFImdQCkaN7wXdfiECEx0Qgk4 kU6qD1amNd304XbAjDNn49jzAd83n3BedcvPjt5uea35na7Jo34n1IxDw8iJ2ZjB UGpBccOFErXEgzXGB6CVh3gJcD8LasM6zkyfQJDTOkT0+eLeRGlktwwxLyEbxBsp mp0+6bz4L+IdeP3tlhp1Ta4qRVd8J1A1fQ6L3Sv/IxIDjsUNX0WYMRJqjjiFXvBF rE65unZIwRBDXjstsicwYlAgmFnvzdeVE5G6hqrkdWhU96iWXJwa1t2nboroSt43 t1k8MU8RE1BD3g2U5JIpjNqp6r2l6bI3Uf/RQ6UPWvtyszIPjm/xpqlVrDplmGvE 7yq0iPVft2dikXUIZ7mS+2JagqmTvEbFS/upPjCx77Z+USrbbXmC3/0Yvs+40AeO nHkbk9o3ZLXOph9631csKkZhMXJzu3V3D8UCoLM2ce+pZDEqTYC4zmwkHRI8KNIl 02VnDTm4eunarFKSIn/G0srShKsOjxnOUS2Q094tEHg2LopSfP0gDZ3y124pefm9 /IXPSRLOtGatwCjfjuyai7EaWU/vLeTF9mYSH+RLWxA7xHQDJZhzqxvD/PNjWN9r 5rExktjgajQKaNhKdMMB =GIXH -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.7-rc2/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes From Tony Lindgren <tony@atomide.com>: Timer fix for am33xx, runtime PM fix for UART, audio McBSP fixes, mux and pinctrl fixes, and Beagle OPP fix. * tag 'omap-for-v3.7-rc2/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: AM33XX: Fix configuration of dmtimer parent clock by dmtimer driverDate:Wed, 17 Oct 2012 13:55:55 -0500 ARM: OMAP3: Beagle: fix OPP customization and initcall ordering ARM: OMAP3: Fix 3430 legacy mux names for ssi1 signals. ARM: OMAP2+: Fix location of select PINCTRL ARM/dts: omap3: Fix mcbsp2/3 hwmods to be able to probe the drivers for audio ARM: OMAP2: UART: fix console UART mismatched runtime PM status ARM: OMAP3: PM: apply part of the erratum i582 workaround Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
14d188bbac
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@ -257,7 +257,7 @@
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interrupt-names = "common", "tx", "rx", "sidetone";
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interrupt-names = "common", "tx", "rx", "sidetone";
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interrupt-parent = <&intc>;
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interrupt-parent = <&intc>;
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ti,buffer-size = <1280>;
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ti,buffer-size = <1280>;
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ti,hwmods = "mcbsp2";
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ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
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};
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};
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mcbsp3: mcbsp@49024000 {
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mcbsp3: mcbsp@49024000 {
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@ -272,7 +272,7 @@
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interrupt-names = "common", "tx", "rx", "sidetone";
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interrupt-names = "common", "tx", "rx", "sidetone";
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interrupt-parent = <&intc>;
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interrupt-parent = <&intc>;
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ti,buffer-size = <128>;
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp3";
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ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
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};
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};
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mcbsp4: mcbsp@49026000 {
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mcbsp4: mcbsp@49026000 {
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@ -11,7 +11,6 @@ config ARCH_OMAP2PLUS_TYPICAL
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select I2C_OMAP
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select I2C_OMAP
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select MENELAUS if ARCH_OMAP2
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select MENELAUS if ARCH_OMAP2
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select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
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select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
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select PINCTRL
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select PM_RUNTIME
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select PM_RUNTIME
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select REGULATOR
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select REGULATOR
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select SERIAL_OMAP
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select SERIAL_OMAP
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@ -24,6 +24,7 @@
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#include <linux/input.h>
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#include <linux/input.h>
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#include <linux/gpio_keys.h>
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#include <linux/gpio_keys.h>
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#include <linux/opp.h>
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#include <linux/opp.h>
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#include <linux/cpu.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/partitions.h>
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@ -444,27 +445,31 @@ static struct omap_board_mux board_mux[] __initdata = {
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};
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};
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#endif
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#endif
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static void __init beagle_opp_init(void)
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static int __init beagle_opp_init(void)
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{
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{
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int r = 0;
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int r = 0;
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/* Initialize the omap3 opp table */
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if (!machine_is_omap3_beagle())
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if (omap3_opp_init()) {
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return 0;
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/* Initialize the omap3 opp table if not already created. */
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r = omap3_opp_init();
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if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
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pr_err("%s: opp default init failed\n", __func__);
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pr_err("%s: opp default init failed\n", __func__);
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return;
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return r;
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}
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}
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/* Custom OPP enabled for all xM versions */
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/* Custom OPP enabled for all xM versions */
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if (cpu_is_omap3630()) {
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if (cpu_is_omap3630()) {
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struct device *mpu_dev, *iva_dev;
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struct device *mpu_dev, *iva_dev;
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mpu_dev = omap_device_get_by_hwmod_name("mpu");
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mpu_dev = get_cpu_device(0);
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iva_dev = omap_device_get_by_hwmod_name("iva");
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iva_dev = omap_device_get_by_hwmod_name("iva");
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if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) {
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if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) {
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pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
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pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
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__func__, mpu_dev, iva_dev);
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__func__, mpu_dev, iva_dev);
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return;
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return -ENODEV;
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}
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}
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/* Enable MPU 1GHz and lower opps */
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/* Enable MPU 1GHz and lower opps */
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r = opp_enable(mpu_dev, 800000000);
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r = opp_enable(mpu_dev, 800000000);
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@ -484,8 +489,9 @@ static void __init beagle_opp_init(void)
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opp_disable(iva_dev, 660000000);
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opp_disable(iva_dev, 660000000);
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}
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}
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}
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}
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return;
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return 0;
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}
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}
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device_initcall(beagle_opp_init);
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static void __init omap3_beagle_init(void)
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static void __init omap3_beagle_init(void)
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{
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{
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@ -522,8 +528,6 @@ static void __init omap3_beagle_init(void)
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/* Ensure SDRC pins are mux'd for self-refresh */
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/* Ensure SDRC pins are mux'd for self-refresh */
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omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
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omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
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omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
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omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
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beagle_opp_init();
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}
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}
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MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
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MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
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@ -1073,6 +1073,8 @@ static struct omap_clk am33xx_clks[] = {
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CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
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CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
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CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
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CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
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CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
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CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
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CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
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CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
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};
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};
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int __init am33xx_clk_init(void)
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int __init am33xx_clk_init(void)
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@ -614,16 +614,16 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
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"sys_off_mode", NULL, NULL, NULL,
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"sys_off_mode", NULL, NULL, NULL,
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"gpio_9", NULL, NULL, "safe_mode"),
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"gpio_9", NULL, NULL, "safe_mode"),
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_OMAP3_MUXENTRY(UART1_CTS, 150,
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_OMAP3_MUXENTRY(UART1_CTS, 150,
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"uart1_cts", NULL, NULL, NULL,
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"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
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"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
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"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
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_OMAP3_MUXENTRY(UART1_RTS, 149,
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_OMAP3_MUXENTRY(UART1_RTS, 149,
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"uart1_rts", NULL, NULL, NULL,
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"uart1_rts", "ssi1_flag_tx", NULL, NULL,
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"gpio_149", NULL, NULL, "safe_mode"),
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"gpio_149", NULL, NULL, "safe_mode"),
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_OMAP3_MUXENTRY(UART1_RX, 151,
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_OMAP3_MUXENTRY(UART1_RX, 151,
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"uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
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"uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
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"gpio_151", NULL, NULL, "safe_mode"),
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"gpio_151", NULL, NULL, "safe_mode"),
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_OMAP3_MUXENTRY(UART1_TX, 148,
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_OMAP3_MUXENTRY(UART1_TX, 148,
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"uart1_tx", NULL, NULL, NULL,
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"uart1_tx", "ssi1_dat_tx", NULL, NULL,
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"gpio_148", NULL, NULL, "safe_mode"),
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"gpio_148", NULL, NULL, "safe_mode"),
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_OMAP3_MUXENTRY(UART2_CTS, 144,
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_OMAP3_MUXENTRY(UART2_CTS, 144,
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"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
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"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
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@ -91,6 +91,7 @@ extern void omap3_save_scratchpad_contents(void);
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#define PM_RTA_ERRATUM_i608 (1 << 0)
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#define PM_RTA_ERRATUM_i608 (1 << 0)
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#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
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#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
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#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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extern u16 pm34xx_errata;
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extern u16 pm34xx_errata;
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@ -652,14 +652,17 @@ static void __init pm_errata_configure(void)
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/* Enable the l2 cache toggling in sleep logic */
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/* Enable the l2 cache toggling in sleep logic */
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enable_omap3630_toggle_l2_on_restore();
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enable_omap3630_toggle_l2_on_restore();
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if (omap_rev() < OMAP3630_REV_ES1_2)
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if (omap_rev() < OMAP3630_REV_ES1_2)
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pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
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pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
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PM_PER_MEMORIES_ERRATUM_i582);
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} else if (cpu_is_omap34xx()) {
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pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
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}
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}
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}
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}
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int __init omap3_pm_init(void)
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int __init omap3_pm_init(void)
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{
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{
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struct power_state *pwrst, *tmp;
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struct power_state *pwrst, *tmp;
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struct clockdomain *neon_clkdm, *mpu_clkdm;
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struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
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int ret;
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int ret;
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if (!omap3_has_io_chain_ctrl())
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if (!omap3_has_io_chain_ctrl())
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@ -711,6 +714,8 @@ int __init omap3_pm_init(void)
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neon_clkdm = clkdm_lookup("neon_clkdm");
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neon_clkdm = clkdm_lookup("neon_clkdm");
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mpu_clkdm = clkdm_lookup("mpu_clkdm");
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mpu_clkdm = clkdm_lookup("mpu_clkdm");
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per_clkdm = clkdm_lookup("per_clkdm");
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wkup_clkdm = clkdm_lookup("wkup_clkdm");
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#ifdef CONFIG_SUSPEND
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#ifdef CONFIG_SUSPEND
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omap_pm_suspend = omap3_pm_suspend;
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omap_pm_suspend = omap3_pm_suspend;
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@ -727,6 +732,27 @@ int __init omap3_pm_init(void)
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if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
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if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
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omap3630_ctrl_disable_rta();
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omap3630_ctrl_disable_rta();
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/*
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* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
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* not correctly reset when the PER powerdomain comes back
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* from OFF or OSWR when the CORE powerdomain is kept active.
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* See OMAP36xx Erratum i582 "PER Domain reset issue after
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* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
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* complete workaround. The kernel must also prevent the PER
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* powerdomain from going to OSWR/OFF while the CORE
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* powerdomain is not going to OSWR/OFF. And if PER last
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* power state was off while CORE last power state was ON, the
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* UART3/4 and McBSP2/3 SIDETONE devices need to run a
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* self-test using their loopback tests; if that fails, those
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* devices are unusable until the PER/CORE can complete a transition
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* from ON to OSWR/OFF and then back to ON.
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*
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* XXX Technically this workaround is only needed if off-mode
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* or OSWR is enabled.
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*/
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if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
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clkdm_add_wkdep(per_clkdm, wkup_clkdm);
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clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
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clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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omap3_secure_ram_storage =
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omap3_secure_ram_storage =
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@ -329,6 +329,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
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oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
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oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
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if (console_uart_id == bdata->id) {
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omap_device_enable(pdev);
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pm_runtime_set_active(&pdev->dev);
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}
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oh->dev_attr = uart;
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oh->dev_attr = uart;
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if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
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if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
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@ -26,6 +26,7 @@ config ARCH_OMAP2PLUS
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select CLKDEV_LOOKUP
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select CLKDEV_LOOKUP
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_CHIP
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select OMAP_DM_TIMER
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select OMAP_DM_TIMER
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select PINCTRL
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select PROC_DEVICETREE if PROC_FS
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select PROC_DEVICETREE if PROC_FS
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select SPARSE_IRQ
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select SPARSE_IRQ
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select USE_OF
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select USE_OF
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||||||
|
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