sh: migrate SH_CLK_MD to mode pin API.
This kills off the hardcoded SH_CLK_MD introduced by the SH-2 boards and converts over to the mode pin API. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
a7bcf21e60
commit
16b259203c
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@ -567,15 +567,6 @@ config SH_CLK_CPG_LEGACY
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
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!CPU_SHX3 && !CPU_SUBTYPE_SH7757
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!CPU_SHX3 && !CPU_SUBTYPE_SH7757
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config SH_CLK_MD
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int "CPU Mode Pin Setting"
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depends on CPU_SH2
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default 6 if CPU_SUBTYPE_SH7206
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default 5 if CPU_SUBTYPE_SH7619
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default 0
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help
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MD2 - MD0 pin setting.
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source "kernel/time/Kconfig"
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source "kernel/time/Kconfig"
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endmenu
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endmenu
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@ -79,6 +79,11 @@ static int __init se7206_devices_setup(void)
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}
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}
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__initcall(se7206_devices_setup);
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__initcall(se7206_devices_setup);
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static int se7206_mode_pins(void)
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{
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return MODE_PIN1 | MODE_PIN2;
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}
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/*
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/*
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* The Machine Vector
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* The Machine Vector
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*/
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*/
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@ -87,4 +92,5 @@ static struct sh_machine_vector mv_se __initmv = {
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.mv_name = "SolutionEngine",
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.mv_name = "SolutionEngine",
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.mv_nr_irqs = 256,
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.mv_nr_irqs = 256,
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.mv_init_irq = init_se7206_IRQ,
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.mv_init_irq = init_se7206_IRQ,
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.mv_mode_pins = se7206_mode_pins,
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};
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};
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@ -11,6 +11,11 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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#include <asm/machvec.h>
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static int se7619_mode_pins(void)
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{
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return MODE_PIN2 | MODE_PIN0;
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}
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/*
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/*
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* The Machine Vector
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* The Machine Vector
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*/
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*/
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@ -18,4 +23,5 @@
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static struct sh_machine_vector mv_se __initmv = {
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static struct sh_machine_vector mv_se __initmv = {
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.mv_name = "SolutionEngine",
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.mv_name = "SolutionEngine",
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.mv_nr_irqs = 108,
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.mv_nr_irqs = 108,
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.mv_mode_pins = se7619_mode_pins,
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};
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};
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@ -14,24 +14,18 @@
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*/
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*/
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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static const int pll1rate[] = {1,2};
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static const int pll1rate[] = {1,2};
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static const int pfc_divisors[] = {1,2,0,4};
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static const int pfc_divisors[] = {1,2,0,4};
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static unsigned int pll2_mult;
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#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
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#define PLL2 (4)
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#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
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#define PLL2 (2)
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#else
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#error "Illigal Clock Mode!"
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#endif
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static void master_clk_init(struct clk *clk)
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static void master_clk_init(struct clk *clk)
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{
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{
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clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
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clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
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}
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}
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static struct clk_ops sh7619_master_clk_ops = {
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static struct clk_ops sh7619_master_clk_ops = {
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@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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{
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if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
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test_mode_pin(MODE_PIN2 | MODE_PIN1))
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pll2_mult = 2;
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else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
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pll2_mult = 4;
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BUG_ON(!pll2_mult);
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if (idx < ARRAY_SIZE(sh7619_clk_ops))
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if (idx < ARRAY_SIZE(sh7619_clk_ops))
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*ops = sh7619_clk_ops[idx];
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*ops = sh7619_clk_ops[idx];
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}
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}
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@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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#define ifc_divisors pfc_divisors
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#if (CONFIG_SH_CLK_MD == 0)
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static unsigned int pll2_mult;
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#define PLL2 (4)
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#elif (CONFIG_SH_CLK_MD == 2)
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#define PLL2 (2)
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#elif (CONFIG_SH_CLK_MD == 3)
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#define PLL2 (1)
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#else
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#error "Illegal Clock Mode!"
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#endif
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static void master_clk_init(struct clk *clk)
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static void master_clk_init(struct clk *clk)
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{
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{
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return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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clk->rate = 10000000 * pll2_mult *
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pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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}
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static struct clk_ops sh7201_master_clk_ops = {
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static struct clk_ops sh7201_master_clk_ops = {
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@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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{
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if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
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pll2_mult = 1;
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else if (test_mode_pin(MODE_PIN1))
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pll2_mult = 2;
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else
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pll2_mult = 4;
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if (idx < ARRAY_SIZE(sh7201_clk_ops))
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if (idx < ARRAY_SIZE(sh7201_clk_ops))
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*ops = sh7201_clk_ops[idx];
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*ops = sh7201_clk_ops[idx];
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}
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}
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@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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#define ifc_divisors pfc_divisors
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#if (CONFIG_SH_CLK_MD == 0)
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static unsigned int pll2_mult;
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#define PLL2 (1)
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#elif (CONFIG_SH_CLK_MD == 1)
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#define PLL2 (2)
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#elif (CONFIG_SH_CLK_MD == 2)
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#define PLL2 (4)
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#elif (CONFIG_SH_CLK_MD == 3)
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#define PLL2 (4)
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#else
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#error "Illegal Clock Mode!"
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#endif
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static void master_clk_init(struct clk *clk)
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static void master_clk_init(struct clk *clk)
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{
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{
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clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
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clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
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}
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}
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static struct clk_ops sh7203_master_clk_ops = {
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static struct clk_ops sh7203_master_clk_ops = {
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@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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{
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if (test_mode_pin(MODE_PIN1))
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pll2_mult = 4;
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else if (test_mode_pin(MODE_PIN0))
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pll2_mult = 2;
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else
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pll2_mult = 1;
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if (idx < ARRAY_SIZE(sh7203_clk_ops))
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if (idx < ARRAY_SIZE(sh7203_clk_ops))
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*ops = sh7203_clk_ops[idx];
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*ops = sh7203_clk_ops[idx];
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}
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}
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@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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#define ifc_divisors pfc_divisors
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#if (CONFIG_SH_CLK_MD == 2)
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static unsigned int pll2_mult;
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#define PLL2 (4)
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#elif (CONFIG_SH_CLK_MD == 6)
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#define PLL2 (2)
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#elif (CONFIG_SH_CLK_MD == 7)
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#define PLL2 (1)
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#else
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#error "Illigal Clock Mode!"
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#endif
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static void master_clk_init(struct clk *clk)
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static void master_clk_init(struct clk *clk)
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{
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{
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clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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}
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static struct clk_ops sh7206_master_clk_ops = {
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static struct clk_ops sh7206_master_clk_ops = {
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@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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{
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if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
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pll2_mult = 1;
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else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
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pll2_mult = 2;
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else if (test_mode_pin(MODE_PIN1))
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pll2_mult = 4;
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if (idx < ARRAY_SIZE(sh7206_clk_ops))
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if (idx < ARRAY_SIZE(sh7206_clk_ops))
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*ops = sh7206_clk_ops[idx];
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*ops = sh7206_clk_ops[idx];
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}
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}
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