Merge branch 'spi-4.17' into spi-4.18 for the merge window
This commit is contained in:
commit
16c10b3bf8
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@ -488,7 +488,7 @@ static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
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static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
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static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
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{
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{
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if (!has_bspi(qspi) || (qspi->bspi_enabled))
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if (!has_bspi(qspi))
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return;
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return;
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qspi->bspi_enabled = 1;
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qspi->bspi_enabled = 1;
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@ -503,7 +503,7 @@ static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
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static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
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static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
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{
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{
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if (!has_bspi(qspi) || (!qspi->bspi_enabled))
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if (!has_bspi(qspi))
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return;
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return;
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qspi->bspi_enabled = 0;
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qspi->bspi_enabled = 0;
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@ -517,16 +517,19 @@ static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
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static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
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static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
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{
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{
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u32 data = 0;
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u32 rd = 0;
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u32 wr = 0;
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if (qspi->curr_cs == cs)
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return;
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if (qspi->base[CHIP_SELECT]) {
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if (qspi->base[CHIP_SELECT]) {
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data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
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rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
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data = (data & ~0xff) | (1 << cs);
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wr = (rd & ~0xff) | (1 << cs);
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bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
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if (rd == wr)
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return;
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bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
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usleep_range(10, 20);
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usleep_range(10, 20);
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}
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}
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dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
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qspi->curr_cs = cs;
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qspi->curr_cs = cs;
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}
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}
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@ -753,8 +756,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
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dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
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dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
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}
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}
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mspi_cdram = MSPI_CDRAM_CONT_BIT;
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mspi_cdram = MSPI_CDRAM_CONT_BIT;
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mspi_cdram |= (~(1 << spi->chip_select) &
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MSPI_CDRAM_PCS);
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if (has_bspi(qspi))
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mspi_cdram &= ~1;
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else
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mspi_cdram |= (~(1 << spi->chip_select) &
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MSPI_CDRAM_PCS);
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mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
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mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
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MSPI_CDRAM_BITSE_BIT);
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MSPI_CDRAM_BITSE_BIT);
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@ -184,6 +184,11 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
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irqreturn_t ret = IRQ_NONE;
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irqreturn_t ret = IRQ_NONE;
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/* IRQ may be shared, so return if our interrupts are disabled */
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if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
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(BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
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return ret;
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/* check if we have data to read */
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/* check if we have data to read */
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while (bs->rx_len &&
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while (bs->rx_len &&
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(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
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(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
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@ -313,6 +313,14 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
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while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
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while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
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(xspi->tx_bytes > 0)) {
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(xspi->tx_bytes > 0)) {
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/* When xspi in busy condition, bytes may send failed,
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* then spi control did't work thoroughly, add one byte delay
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*/
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if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
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CDNS_SPI_IXR_TXFULL)
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usleep_range(10, 20);
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if (xspi->txbuf)
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if (xspi->txbuf)
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cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
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cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
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else
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else
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@ -567,14 +567,16 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
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/* Configure native chip select mode/polarity early */
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/* Configure native chip select mode/polarity early */
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clr = MDR1_SYNCMD_MASK;
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clr = MDR1_SYNCMD_MASK;
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set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;
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set = MDR1_SYNCMD_SPI;
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if (spi->mode & SPI_CS_HIGH)
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if (spi->mode & SPI_CS_HIGH)
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clr |= BIT(MDR1_SYNCAC_SHIFT);
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clr |= BIT(MDR1_SYNCAC_SHIFT);
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else
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else
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set |= BIT(MDR1_SYNCAC_SHIFT);
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set |= BIT(MDR1_SYNCAC_SHIFT);
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pm_runtime_get_sync(&p->pdev->dev);
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pm_runtime_get_sync(&p->pdev->dev);
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tmp = sh_msiof_read(p, TMDR1) & ~clr;
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tmp = sh_msiof_read(p, TMDR1) & ~clr;
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sh_msiof_write(p, TMDR1, tmp | set);
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sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
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tmp = sh_msiof_read(p, RMDR1) & ~clr;
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sh_msiof_write(p, RMDR1, tmp | set);
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pm_runtime_put(&p->pdev->dev);
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pm_runtime_put(&p->pdev->dev);
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p->native_cs_high = spi->mode & SPI_CS_HIGH;
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p->native_cs_high = spi->mode & SPI_CS_HIGH;
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p->native_cs_inited = true;
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p->native_cs_inited = true;
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