ath9k_hw: remove ATH9K_CAP_MCAST_KEYSRCH
The driver always sets this to enabled, but this can be simplified with a small change to ah->sta_id1_defaults instead. This change also removes the now-obsolete ath9k_hw_setcapability function. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -569,11 +569,6 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
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*/
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for (i = 0; i < common->keymax; i++)
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ath9k_hw_keyreset(priv->ah, (u16) i);
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/* turn on mcast key search if possible */
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if (!ath9k_hw_getcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
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(void)ath9k_hw_setcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH,
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1, 1, NULL);
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}
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static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
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@ -425,7 +425,9 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
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ah->ah_flags = AH_USE_EEPROM;
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ah->atim_window = 0;
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ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
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ah->sta_id1_defaults =
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AR_STA_ID1_CRPT_MIC_ENABLE |
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AR_STA_ID1_MCAST_KSRCH;
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ah->beacon_interval = 100;
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ah->enable_32kHz_clock = DONT_USE_32KHZ;
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ah->slottime = (u32) -1;
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@ -2259,20 +2261,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 *result)
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{
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switch (type) {
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case ATH9K_CAP_MCAST_KEYSRCH:
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switch (capability) {
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case 0:
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return true;
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case 1:
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if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
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return false;
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} else {
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return (ah->sta_id1_defaults &
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AR_STA_ID1_MCAST_KSRCH) ? true :
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false;
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}
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}
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return false;
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case ATH9K_CAP_DS:
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return (AR_SREV_9280_20_OR_LATER(ah) &&
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(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
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@ -2283,21 +2271,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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}
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EXPORT_SYMBOL(ath9k_hw_getcapability);
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bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 setting, int *status)
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{
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switch (type) {
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case ATH9K_CAP_MCAST_KEYSRCH:
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if (setting)
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ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
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else
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ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
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return true;
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default:
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return false;
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}
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}
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EXPORT_SYMBOL(ath9k_hw_setcapability);
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/****************************/
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/* GPIO / RFKILL / Antennae */
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@ -207,7 +207,6 @@ enum ath9k_hw_caps {
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};
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enum ath9k_capability_type {
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ATH9K_CAP_MCAST_KEYSRCH,
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ATH9K_CAP_DS
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};
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@ -855,8 +854,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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int ath9k_hw_fill_cap_info(struct ath_hw *ah);
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bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 *result);
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bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 setting, int *status);
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u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
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/* Key Cache Management */
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@ -387,12 +387,6 @@ static void ath9k_init_crypto(struct ath_softc *sc)
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*/
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if (!(sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA))
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common->splitmic = 1;
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/* turn on mcast key search if possible */
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if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
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(void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
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1, 1, NULL);
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}
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static int ath9k_init_btcoex(struct ath_softc *sc)
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