gpu: host1x: handle the correct # of syncpt regs
commit22bbd5d949
upstream. BIT_WORD() truncates rather than rounds, so the loops in syncpt_thresh_isr() and _host1x_intr_disable_all_syncpt_intrs() use <= rather than < in an attempt to process the correct number of registers when rounding of the conversion of count of bits to count of words is necessary. However, when rounding isn't necessary because the value is already a multiple of the divisor (as is the case for all values of nb_pts the code actually sees), this causes one too many registers to be processed. Solve this by using and explicit DIV_ROUND_UP() call, rather than BIT_WORD(), and comparing with < rather than <=. Fixes:7ede0b0bf3
("gpu: host1x: Add syncpoint wait and interrupts") Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -47,7 +47,7 @@ static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
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unsigned long reg;
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unsigned long reg;
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int i, id;
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int i, id;
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for (i = 0; i <= BIT_WORD(host->info->nb_pts); i++) {
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for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) {
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reg = host1x_sync_readl(host,
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reg = host1x_sync_readl(host,
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HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
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HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
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for_each_set_bit(id, ®, BITS_PER_LONG) {
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for_each_set_bit(id, ®, BITS_PER_LONG) {
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@ -64,7 +64,7 @@ static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
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{
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{
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u32 i;
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u32 i;
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for (i = 0; i <= BIT_WORD(host->info->nb_pts); ++i) {
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for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) {
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host1x_sync_writel(host, 0xffffffffu,
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host1x_sync_writel(host, 0xffffffffu,
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HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
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HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
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host1x_sync_writel(host, 0xffffffffu,
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host1x_sync_writel(host, 0xffffffffu,
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