MIPS: traps: 64bit kernels should read CP0_EBase 64bit
When reading the CP0_EBase register containing the WG (write gate) bit, the ebase variable should be set to the full value of the register, i.e. on a 64-bit kernel the full 64-bit width of the register via read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width including bits 31:30 which may be writeable. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14148/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -2215,8 +2215,17 @@ void __init trap_init(void)
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} else {
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ebase = CAC_BASE;
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if (cpu_has_mips_r2_r6)
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ebase += (read_c0_ebase() & 0x3ffff000);
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if (cpu_has_mips_r2_r6) {
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if (cpu_has_ebase_wg) {
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#ifdef CONFIG_64BIT
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ebase = (read_c0_ebase_64() & ~0xfff);
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#else
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ebase = (read_c0_ebase() & ~0xfff);
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#endif
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} else {
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ebase += (read_c0_ebase() & 0x3ffff000);
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}
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}
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}
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if (cpu_has_mmips) {
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