soc/qman: Handle endianness of h/w descriptors
The hardware descriptors have big endian (BE) format. Provide proper endianness handling for the remaining descriptor fields, to ensure they are correctly accessed by non-BE CPUs too. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
parent
496bfa11de
commit
1805882276
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@ -140,10 +140,10 @@ enum qm_mr_cmode { /* matches QCSP_CFG::MM */
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struct qm_eqcr_entry {
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u8 _ncw_verb; /* writes to this are non-coherent */
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u8 dca;
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u16 seqnum;
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__be16 seqnum;
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u8 __reserved[4];
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u32 fqid; /* 24-bit */
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u32 tag;
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__be32 fqid; /* 24-bit */
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__be32 tag;
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struct qm_fd fd;
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u8 __reserved3[32];
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} __packed;
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@ -187,7 +187,7 @@ struct qm_mr {
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struct qm_mcc_fq {
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u8 _ncw_verb;
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u8 __reserved1[3];
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u32 fqid; /* 24-bit */
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__be32 fqid; /* 24-bit */
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u8 __reserved2[56];
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} __packed;
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@ -470,7 +470,7 @@ static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
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static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
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{
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DPAA_ASSERT(eqcr->busy);
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DPAA_ASSERT(!(eqcr->cursor->fqid & ~QM_FQID_MASK));
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DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
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DPAA_ASSERT(eqcr->available >= 1);
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}
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@ -1395,7 +1395,7 @@ static void qm_mr_process_task(struct work_struct *work)
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break;
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case QM_MR_VERB_FQPN:
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/* Parked */
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fq = tag_to_fq(msg->fq.context_b);
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fq = tag_to_fq(be32_to_cpu(msg->fq.context_b));
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fq_state_change(p, fq, msg, verb);
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if (fq->cb.fqs)
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fq->cb.fqs(p, fq, msg);
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@ -1409,7 +1409,7 @@ static void qm_mr_process_task(struct work_struct *work)
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}
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} else {
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/* Its a software ERN */
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fq = tag_to_fq(msg->ern.tag);
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fq = tag_to_fq(be32_to_cpu(msg->ern.tag));
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fq->cb.ern(p, fq, msg);
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}
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num++;
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@ -1521,7 +1521,7 @@ static inline unsigned int __poll_portal_fast(struct qman_portal *p,
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clear_vdqcr(p, fq);
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} else {
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/* SDQCR: context_b points to the FQ */
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fq = tag_to_fq(dq->context_b);
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fq = tag_to_fq(be32_to_cpu(dq->context_b));
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/* Now let the callback do its stuff */
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res = fq->cb.dqrr(p, fq, dq);
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/*
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@ -1738,9 +1738,9 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
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if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
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return -EINVAL;
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#endif
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if (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) {
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if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {
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/* And can't be set at the same time as TDTHRESH */
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if (opts->we_mask & QM_INITFQ_WE_TDTHRESH)
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if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)
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return -EINVAL;
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}
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/* Issue an INITFQ_[PARKED|SCHED] management command */
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@ -1764,14 +1764,16 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
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if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
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dma_addr_t phys_fq;
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mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB;
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mcc->initfq.fqd.context_b = fq_to_tag(fq);
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mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
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mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
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/*
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* and the physical address - NB, if the user wasn't trying to
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* set CONTEXTA, clear the stashing settings.
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*/
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if (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) {
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mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA;
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if (!(be16_to_cpu(mcc->initfq.we_mask) &
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QM_INITFQ_WE_CONTEXTA)) {
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mcc->initfq.we_mask |=
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cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
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memset(&mcc->initfq.fqd.context_a, 0,
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sizeof(mcc->initfq.fqd.context_a));
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} else {
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@ -1791,8 +1793,10 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
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if (flags & QMAN_INITFQ_FLAG_LOCAL) {
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int wq = 0;
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if (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) {
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mcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ;
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if (!(be16_to_cpu(mcc->initfq.we_mask) &
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QM_INITFQ_WE_DESTWQ)) {
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mcc->initfq.we_mask |=
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cpu_to_be16(QM_INITFQ_WE_DESTWQ);
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wq = 4;
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}
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qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
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@ -1811,13 +1815,13 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
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goto out;
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}
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if (opts) {
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if (opts->we_mask & QM_INITFQ_WE_FQCTRL) {
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if (opts->fqd.fq_ctrl & QM_FQCTRL_CGE)
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if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
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if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
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fq_set(fq, QMAN_FQ_STATE_CGR_EN);
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else
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fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
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}
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if (opts->we_mask & QM_INITFQ_WE_CGID)
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if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)
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fq->cgr_groupid = opts->fqd.cgid;
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}
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fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
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@ -1937,7 +1941,7 @@ int qman_retire_fq(struct qman_fq *fq, u32 *flags)
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msg.verb = QM_MR_VERB_FQRNI;
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msg.fq.fqs = mcr->alterfq.fqs;
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qm_fqid_set(&msg.fq, fq->fqid);
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msg.fq.context_b = fq_to_tag(fq);
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msg.fq.context_b = cpu_to_be32(fq_to_tag(fq));
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fq->cb.fqs(p, fq, &msg);
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}
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} else if (res == QM_MCR_RESULT_PENDING) {
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@ -2206,7 +2210,7 @@ int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
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goto out;
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qm_fqid_set(eq, fq->fqid);
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eq->tag = fq_to_tag(fq);
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eq->tag = cpu_to_be32(fq_to_tag(fq));
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eq->fd = *fd;
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qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
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@ -2253,17 +2257,18 @@ out:
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static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)
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{
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if (qman_ip_rev >= QMAN_REV30)
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cgr->cscn_targ_upd_ctrl = QM_CGR_TARG_UDP_CTRL_WRITE_BIT | pi;
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cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |
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QM_CGR_TARG_UDP_CTRL_WRITE_BIT);
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else
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cgr->cscn_targ = val | QM_CGR_TARG_PORTAL(pi);
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cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));
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}
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static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)
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{
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if (qman_ip_rev >= QMAN_REV30)
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cgr->cscn_targ_upd_ctrl = pi;
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cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);
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else
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cgr->cscn_targ = val & ~QM_CGR_TARG_PORTAL(pi);
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cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));
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}
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static u8 qman_cgr_cpus[CGR_NUM];
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@ -2315,8 +2320,8 @@ int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
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goto out;
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qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
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cgr_state.cgr.cscn_targ);
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local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
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be32_to_cpu(cgr_state.cgr.cscn_targ));
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local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
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/* send init if flags indicate so */
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if (flags & QMAN_CGR_FLAG_USE_INIT)
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@ -2383,9 +2388,9 @@ int qman_delete_cgr(struct qman_cgr *cgr)
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goto release_lock;
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}
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local_opts.we_mask = QM_CGR_WE_CSCN_TARG;
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local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);
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qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),
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cgr_state.cgr.cscn_targ);
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be32_to_cpu(cgr_state.cgr.cscn_targ));
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ret = qm_modify_cgr(cgr, 0, &local_opts);
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if (ret)
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@ -2835,7 +2840,7 @@ static int cgr_cleanup(u32 cgrid)
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err = qman_query_fq(&fq, &fqd);
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if (WARN_ON(err))
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return err;
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if ((fqd.fq_ctrl & QM_FQCTRL_CGE) &&
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if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
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fqd.cgid == cgrid) {
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pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
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cgrid, fq.fqid);
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@ -73,20 +73,20 @@ struct qm_mcr_querycgr {
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struct __qm_mc_cgr cgr; /* CGR fields */
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u8 __reserved2[6];
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u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */
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u32 i_bcnt_lo; /* low 32-bits of 40-bit */
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__be32 i_bcnt_lo; /* low 32-bits of 40-bit */
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u8 __reserved3[3];
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u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */
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u32 a_bcnt_lo; /* low 32-bits of 40-bit */
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u32 cscn_targ_swp[4];
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__be32 a_bcnt_lo; /* low 32-bits of 40-bit */
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__be32 cscn_targ_swp[4];
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} __packed;
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static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q)
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{
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return ((u64)q->i_bcnt_hi << 32) | (u64)q->i_bcnt_lo;
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return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo);
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}
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static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)
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{
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return ((u64)q->a_bcnt_hi << 32) | (u64)q->a_bcnt_lo;
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return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo);
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}
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/* "Query FQ Non-Programmable Fields" */
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@ -65,7 +65,7 @@ static void fd_init(struct qm_fd *fd)
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{
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qm_fd_addr_set64(fd, 0xabdeadbeefLLU);
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qm_fd_set_contig_big(fd, 0x0000ffff);
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fd->cmd = 0xfeedf00d;
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fd->cmd = cpu_to_be32(0xfeedf00d);
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}
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static void fd_inc(struct qm_fd *fd)
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@ -86,7 +86,7 @@ static void fd_inc(struct qm_fd *fd)
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len--;
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qm_fd_set_param(fd, fmt, off, len);
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fd->cmd++;
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fd->cmd = cpu_to_be32(be32_to_cpu(fd->cmd) + 1);
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}
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/* The only part of the 'fd' we can't memcmp() is the ppid */
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@ -406,8 +406,9 @@ static int init_handler(void *h)
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goto failed;
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}
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memset(&opts, 0, sizeof(opts));
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opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
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opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING;
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opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL |
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QM_INITFQ_WE_CONTEXTA);
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opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING);
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qm_fqd_set_stashing(&opts.fqd, 0, STASH_DATA_CL, STASH_CTX_CL);
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err = qman_init_fq(&handler->rx, QMAN_INITFQ_FLAG_SCHED |
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QMAN_INITFQ_FLAG_LOCAL, &opts);
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@ -244,11 +244,11 @@ static inline int qm_sg_entry_get_off(const struct qm_sg_entry *sg)
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struct qm_dqrr_entry {
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u8 verb;
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u8 stat;
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u16 seqnum; /* 15-bit */
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__be16 seqnum; /* 15-bit */
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u8 tok;
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u8 __reserved2[3];
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u32 fqid; /* 24-bit */
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u32 context_b;
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__be32 fqid; /* 24-bit */
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__be32 context_b;
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struct qm_fd fd;
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u8 __reserved4[32];
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} __packed;
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@ -264,8 +264,8 @@ struct qm_dqrr_entry {
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/* 'fqid' is a 24-bit field in every h/w descriptor */
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#define QM_FQID_MASK GENMASK(23, 0)
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#define qm_fqid_set(p, v) ((p)->fqid = ((v) & QM_FQID_MASK))
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#define qm_fqid_get(p) ((p)->fqid & QM_FQID_MASK)
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#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
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#define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK)
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/* "ERN Message Response" */
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/* "FQ State Change Notification" */
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@ -277,11 +277,11 @@ union qm_mr_entry {
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struct {
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u8 verb;
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u8 dca;
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u16 seqnum;
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__be16 seqnum;
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u8 rc; /* Rej Code: 8-bit */
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u8 __reserved[3];
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u32 fqid; /* 24-bit */
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u32 tag;
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__be32 fqid; /* 24-bit */
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__be32 tag;
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struct qm_fd fd;
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u8 __reserved1[32];
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} __packed ern;
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@ -289,8 +289,8 @@ union qm_mr_entry {
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u8 verb;
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u8 fqs; /* Frame Queue Status */
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u8 __reserved1[6];
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u32 fqid; /* 24-bit */
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u32 context_b;
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__be32 fqid; /* 24-bit */
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__be32 context_b;
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u8 __reserved2[48];
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} __packed fq; /* FQRN/FQRNI/FQRL/FQPN */
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};
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@ -409,8 +409,8 @@ static inline u64 qm_fqd_context_a_get64(const struct qm_fqd *fqd)
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static inline void qm_fqd_stashing_set64(struct qm_fqd *fqd, u64 addr)
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{
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fqd->context_a.context_hi = upper_32_bits(addr);
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fqd->context_a.context_lo = lower_32_bits(addr);
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fqd->context_a.context_hi = cpu_to_be16(upper_32_bits(addr));
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fqd->context_a.context_lo = cpu_to_be32(lower_32_bits(addr));
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}
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static inline void qm_fqd_context_a_set64(struct qm_fqd *fqd, u64 addr)
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@ -525,7 +525,7 @@ static inline int qm_fqd_get_wq(const struct qm_fqd *fqd)
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*/
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struct qm_cgr_wr_parm {
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/* MA[24-31], Mn[19-23], SA[12-18], Sn[6-11], Pn[0-5] */
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u32 word;
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__be32 word;
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};
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/*
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* This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding
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@ -536,7 +536,7 @@ struct qm_cgr_wr_parm {
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*/
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struct qm_cgr_cs_thres {
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/* _res[13-15], TA[5-12], Tn[0-4] */
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u16 word;
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__be16 word;
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};
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/*
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* This identical structure of CGR fields is present in the "Init/Modify CGR"
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@ -553,10 +553,10 @@ struct __qm_mc_cgr {
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u8 cscn_en; /* boolean, use QM_CGR_EN */
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union {
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struct {
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u16 cscn_targ_upd_ctrl; /* use QM_CGR_TARG_UDP_* */
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||||
u16 cscn_targ_dcp_low;
|
||||
__be16 cscn_targ_upd_ctrl; /* use QM_CGR_TARG_UDP_* */
|
||||
__be16 cscn_targ_dcp_low;
|
||||
};
|
||||
u32 cscn_targ; /* use QM_CGR_TARG_* */
|
||||
__be32 cscn_targ; /* use QM_CGR_TARG_* */
|
||||
};
|
||||
u8 cstd_en; /* boolean, use QM_CGR_EN */
|
||||
u8 cs; /* boolean, only used in query response */
|
||||
|
@ -572,7 +572,9 @@ struct __qm_mc_cgr {
|
|||
/* Convert CGR thresholds to/from "cs_thres" format */
|
||||
static inline u64 qm_cgr_cs_thres_get64(const struct qm_cgr_cs_thres *th)
|
||||
{
|
||||
return ((th->word >> 5) & 0xff) << (th->word & 0x1f);
|
||||
int thres = be16_to_cpu(th->word);
|
||||
|
||||
return ((thres >> 5) & 0xff) << (thres & 0x1f);
|
||||
}
|
||||
|
||||
static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val,
|
||||
|
@ -588,23 +590,23 @@ static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val,
|
|||
if (roundup && oddbit)
|
||||
val++;
|
||||
}
|
||||
th->word = ((val & 0xff) << 5) | (e & 0x1f);
|
||||
th->word = cpu_to_be16(((val & 0xff) << 5) | (e & 0x1f));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* "Initialize FQ" */
|
||||
struct qm_mcc_initfq {
|
||||
u8 __reserved1[2];
|
||||
u16 we_mask; /* Write Enable Mask */
|
||||
u32 fqid; /* 24-bit */
|
||||
u16 count; /* Initialises 'count+1' FQDs */
|
||||
__be16 we_mask; /* Write Enable Mask */
|
||||
__be32 fqid; /* 24-bit */
|
||||
__be16 count; /* Initialises 'count+1' FQDs */
|
||||
struct qm_fqd fqd; /* the FQD fields go here */
|
||||
u8 __reserved2[30];
|
||||
} __packed;
|
||||
/* "Initialize/Modify CGR" */
|
||||
struct qm_mcc_initcgr {
|
||||
u8 __reserve1[2];
|
||||
u16 we_mask; /* Write Enable Mask */
|
||||
__be16 we_mask; /* Write Enable Mask */
|
||||
struct __qm_mc_cgr cgr; /* CGR fields */
|
||||
u8 __reserved2[2];
|
||||
u8 cgid;
|
||||
|
|
Loading…
Reference in New Issue