Merge 4.7-rc4 into char-misc-next
We want those fixes in here to help with merge issues. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
commit
194c8581eb
2
.mailmap
2
.mailmap
|
@ -89,6 +89,7 @@ Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
|||
Linas Vepstas <linas@austin.ibm.com>
|
||||
Mark Brown <broonie@sirena.org.uk>
|
||||
Matthieu CASTET <castet.matthieu@free.fr>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com> <mchehab@infradead.org> <mchehab@redhat.com> <m.chehab@samsung.com> <mchehab@osg.samsung.com> <mchehab@s-opensource.com>
|
||||
Mayuresh Janorkar <mayur@ti.com>
|
||||
Michael Buesch <m@bues.ch>
|
||||
Michel Dänzer <michel@tungstengraphics.com>
|
||||
|
@ -122,6 +123,7 @@ Santosh Shilimkar <santosh.shilimkar@oracle.org>
|
|||
Sascha Hauer <s.hauer@pengutronix.de>
|
||||
S.Çağlar Onur <caglar@pardus.org.tr>
|
||||
Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com> <shuah.khan@hp.com> <shuahkh@osg.samsung.com> <shuah.kh@samsung.com>
|
||||
Simon Kelley <simon@thekelleys.org.uk>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
Stephen Hemminger <shemminger@osdl.org>
|
||||
|
|
1
CREDITS
1
CREDITS
|
@ -649,6 +649,7 @@ D: Configure, Menuconfig, xconfig
|
|||
|
||||
N: Mauro Carvalho Chehab
|
||||
E: m.chehab@samsung.org
|
||||
E: mchehab@osg.samsung.com
|
||||
E: mchehab@infradead.org
|
||||
D: Media subsystem (V4L/DVB) drivers and core
|
||||
D: EDAC drivers and EDAC 3.0 core rework
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
What: /config/usb-gadget/gadget/functions/uvc.name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: UVC function directory
|
||||
|
||||
streaming_maxburst - 0..15 (ss only)
|
||||
|
@ -9,37 +9,37 @@ Description: UVC function directory
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control
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||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Control descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/class
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/class/ss
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Super speed control class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/class/fs
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Full speed control class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/output
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Output terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/output/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default output terminal descriptors
|
||||
|
||||
All attributes read only:
|
||||
|
@ -53,12 +53,12 @@ Description: Default output terminal descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/camera
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Camera terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/camera/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default camera terminal descriptors
|
||||
|
||||
All attributes read only:
|
||||
|
@ -75,12 +75,12 @@ Description: Default camera terminal descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/processing
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Processing unit descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/processing/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default processing unit descriptors
|
||||
|
||||
All attributes read only:
|
||||
|
@ -94,49 +94,49 @@ Description: Default processing unit descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/header
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Control header descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/header/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific control header descriptors
|
||||
|
||||
dwClockFrequency
|
||||
bcdUVC
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Streaming descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class/ss
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Super speed streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class/hs
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: High speed streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class/fs
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Full speed streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/color_matching
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Color matching descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/color_matching/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default color matching descriptors
|
||||
|
||||
All attributes read only:
|
||||
|
@ -150,12 +150,12 @@ Description: Default color matching descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/mjpeg
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: MJPEG format descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/mjpeg/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific MJPEG format descriptors
|
||||
|
||||
All attributes read only,
|
||||
|
@ -174,7 +174,7 @@ Description: Specific MJPEG format descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/mjpeg/name/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific MJPEG frame descriptors
|
||||
|
||||
dwFrameInterval - indicates how frame interval can be
|
||||
|
@ -196,12 +196,12 @@ Description: Specific MJPEG frame descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/uncompressed
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Uncompressed format descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/uncompressed/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific uncompressed format descriptors
|
||||
|
||||
bmaControls - this format's data for bmaControls in
|
||||
|
@ -221,7 +221,7 @@ Description: Specific uncompressed format descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/uncompressed/name/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific uncompressed frame descriptors
|
||||
|
||||
dwFrameInterval - indicates how frame interval can be
|
||||
|
@ -243,12 +243,12 @@ Description: Specific uncompressed frame descriptors
|
|||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/header
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Streaming header descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/header/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific streaming header descriptors
|
||||
|
||||
All attributes read only:
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
What /sys/bus/iio/devices/iio:deviceX/in_proximity_raw
|
||||
What /sys/bus/iio/devices/iio:deviceX/in_proximity_input
|
||||
Date: March 2014
|
||||
KernelVersion: 3.15
|
||||
Contact: Matt Ranostay <mranostay@gmail.com>
|
||||
|
|
|
@ -44,8 +44,8 @@ Required properties:
|
|||
- our-claim-gpio: The GPIO that we use to claim the bus.
|
||||
- their-claim-gpios: The GPIOs that the other sides use to claim the bus.
|
||||
Note that some implementations may only support a single other master.
|
||||
- Standard I2C mux properties. See mux.txt in this directory.
|
||||
- Single I2C child bus node at reg 0. See mux.txt in this directory.
|
||||
- Standard I2C mux properties. See i2c-mux.txt in this directory.
|
||||
- Single I2C child bus node at reg 0. See i2c-mux.txt in this directory.
|
||||
|
||||
Optional properties:
|
||||
- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us.
|
||||
|
|
|
@ -27,7 +27,8 @@ Required properties:
|
|||
- i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C
|
||||
parents.
|
||||
|
||||
Furthermore, I2C mux properties and child nodes. See mux.txt in this directory.
|
||||
Furthermore, I2C mux properties and child nodes. See i2c-mux.txt in this
|
||||
directory.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -22,8 +22,8 @@ Required properties:
|
|||
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
|
||||
port is connected to.
|
||||
- mux-gpios: list of gpios used to control the muxer
|
||||
* Standard I2C mux properties. See mux.txt in this directory.
|
||||
* I2C child bus nodes. See mux.txt in this directory.
|
||||
* Standard I2C mux properties. See i2c-mux.txt in this directory.
|
||||
* I2C child bus nodes. See i2c-mux.txt in this directory.
|
||||
|
||||
Optional properties:
|
||||
- idle-state: value to set the muxer to when idle. When no value is
|
||||
|
@ -33,7 +33,7 @@ For each i2c child node, an I2C child bus will be created. They will
|
|||
be numbered based on their order in the device tree.
|
||||
|
||||
Whenever an access is made to a device on a child bus, the value set
|
||||
in the revelant node's reg property will be output using the list of
|
||||
in the relevant node's reg property will be output using the list of
|
||||
GPIOs, the first in the list holding the least-significant value.
|
||||
|
||||
If an idle state is defined, using the idle-state (optional) property,
|
||||
|
|
|
@ -28,9 +28,9 @@ Also required are:
|
|||
* Standard pinctrl properties that specify the pin mux state for each child
|
||||
bus. See ../pinctrl/pinctrl-bindings.txt.
|
||||
|
||||
* Standard I2C mux properties. See mux.txt in this directory.
|
||||
* Standard I2C mux properties. See i2c-mux.txt in this directory.
|
||||
|
||||
* I2C child bus nodes. See mux.txt in this directory.
|
||||
* I2C child bus nodes. See i2c-mux.txt in this directory.
|
||||
|
||||
For each named state defined in the pinctrl-names property, an I2C child bus
|
||||
will be created. I2C child bus numbers are assigned based on the index into
|
||||
|
|
|
@ -7,8 +7,8 @@ Required properties:
|
|||
- compatible: i2c-mux-reg
|
||||
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
|
||||
port is connected to.
|
||||
* Standard I2C mux properties. See mux.txt in this directory.
|
||||
* I2C child bus nodes. See mux.txt in this directory.
|
||||
* Standard I2C mux properties. See i2c-mux.txt in this directory.
|
||||
* I2C child bus nodes. See i2c-mux.txt in this directory.
|
||||
|
||||
Optional properties:
|
||||
- reg: this pair of <offset size> specifies the register to control the mux.
|
||||
|
@ -24,7 +24,7 @@ Optional properties:
|
|||
given, it defaults to the last value used.
|
||||
|
||||
Whenever an access is made to a device on a child bus, the value set
|
||||
in the revelant node's reg property will be output to the register.
|
||||
in the relevant node's reg property will be output to the register.
|
||||
|
||||
If an idle state is defined, using the idle-state (optional) property,
|
||||
whenever an access is not being made to a device on a child bus, the
|
||||
|
|
|
@ -13,10 +13,10 @@ Optional properties:
|
|||
initialization. This is an array of 28 values(u8).
|
||||
|
||||
- marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
|
||||
firmware will use the pin to wakeup host system.
|
||||
firmware will use the pin to wakeup host system (u16).
|
||||
- marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host
|
||||
platform. The value will be configured to firmware. This
|
||||
is needed to work chip's sleep feature as expected.
|
||||
is needed to work chip's sleep feature as expected (u16).
|
||||
- interrupt-parent: phandle of the parent interrupt controller
|
||||
- interrupts : interrupt pin number to the cpu. Driver will request an irq based
|
||||
on this interrupt number. During system suspend, the irq will be
|
||||
|
@ -50,7 +50,7 @@ calibration data is also available in below example.
|
|||
0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
|
||||
0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
|
||||
0x00 0x00 0xf0 0x00>;
|
||||
marvell,wakeup-pin = <0x0d>;
|
||||
marvell,wakeup-gap-ms = <0x64>;
|
||||
marvell,wakeup-pin = /bits/ 16 <0x0d>;
|
||||
marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -255,6 +255,7 @@ synology Synology, Inc.
|
|||
SUNW Sun Microsystems, Inc
|
||||
tbs TBS Technologies
|
||||
tcl Toby Churchill Ltd.
|
||||
technexion TechNexion
|
||||
technologic Technologic Systems
|
||||
thine THine Electronics, Inc.
|
||||
ti Texas Instruments
|
||||
|
@ -269,6 +270,7 @@ tronsmart Tronsmart
|
|||
truly Truly Semiconductors Limited
|
||||
tyan Tyan Computer Corporation
|
||||
upisemi uPI Semiconductor Corp.
|
||||
uniwest United Western Technologies Corp (UniWest)
|
||||
urt United Radiant Technology Corporation
|
||||
usi Universal Scientific Industrial Co., Ltd.
|
||||
v3 V3 Semiconductor
|
||||
|
|
|
@ -74,8 +74,8 @@ blink_set() function (see <linux/leds.h>). To set an LED to blinking,
|
|||
however, it is better to use the API function led_blink_set(), as it
|
||||
will check and implement software fallback if necessary.
|
||||
|
||||
To turn off blinking again, use the API function led_brightness_set()
|
||||
as that will not just set the LED brightness but also stop any software
|
||||
To turn off blinking, use the API function led_brightness_set()
|
||||
with brightness value LED_OFF, which should stop any software
|
||||
timers that may have been required for blinking.
|
||||
|
||||
The blink_set() function should choose a user friendly blinking value
|
||||
|
|
66
MAINTAINERS
66
MAINTAINERS
|
@ -1159,6 +1159,7 @@ F: arch/arm/mach-footbridge/
|
|||
ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
|
||||
M: Shawn Guo <shawnguo@kernel.org>
|
||||
M: Sascha Hauer <kernel@pengutronix.de>
|
||||
R: Fabio Estevam <fabio.estevam@nxp.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
|
||||
|
@ -2242,7 +2243,8 @@ F: include/net/ax25.h
|
|||
F: net/ax25/
|
||||
|
||||
AZ6007 DVB DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -2709,7 +2711,8 @@ F: Documentation/filesystems/btrfs.txt
|
|||
F: fs/btrfs/
|
||||
|
||||
BTTV VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -3344,7 +3347,8 @@ S: Maintained
|
|||
F: drivers/media/dvb-frontends/cx24120*
|
||||
|
||||
CX88 VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -3774,6 +3778,7 @@ Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
|
|||
S: Maintained
|
||||
F: drivers/dma/
|
||||
F: include/linux/dmaengine.h
|
||||
F: Documentation/devicetree/bindings/dma/
|
||||
F: Documentation/dmaengine/
|
||||
T: git git://git.infradead.org/users/vkoul/slave-dma.git
|
||||
|
||||
|
@ -4291,7 +4296,8 @@ F: fs/ecryptfs/
|
|||
EDAC-CORE
|
||||
M: Doug Thompson <dougthompson@xmission.com>
|
||||
M: Borislav Petkov <bp@alien8.de>
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git for-next
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac.git linux_next
|
||||
|
@ -4336,7 +4342,8 @@ S: Maintained
|
|||
F: drivers/edac/e7xxx_edac.c
|
||||
|
||||
EDAC-GHES
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/ghes_edac.c
|
||||
|
@ -4360,19 +4367,22 @@ S: Maintained
|
|||
F: drivers/edac/i5000_edac.c
|
||||
|
||||
EDAC-I5400
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/i5400_edac.c
|
||||
|
||||
EDAC-I7300
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/i7300_edac.c
|
||||
|
||||
EDAC-I7CORE
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/i7core_edac.c
|
||||
|
@ -4409,7 +4419,8 @@ S: Maintained
|
|||
F: drivers/edac/r82600_edac.c
|
||||
|
||||
EDAC-SBRIDGE
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/sb_edac.c
|
||||
|
@ -4468,7 +4479,8 @@ S: Maintained
|
|||
F: drivers/net/ethernet/ibm/ehea/
|
||||
|
||||
EM28XX VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -6487,6 +6499,7 @@ F: include/uapi/linux/sunrpc/
|
|||
|
||||
KERNEL SELFTEST FRAMEWORK
|
||||
M: Shuah Khan <shuahkh@osg.samsung.com>
|
||||
M: Shuah Khan <shuah@kernel.org>
|
||||
L: linux-kselftest@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/shuah/linux-kselftest
|
||||
S: Maintained
|
||||
|
@ -7358,7 +7371,8 @@ S: Supported
|
|||
F: drivers/media/pci/netup_unidvb/*
|
||||
|
||||
MEDIA INPUT INFRASTRUCTURE (V4L/DVB)
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
P: LinuxTV.org Project
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
@ -8407,10 +8421,9 @@ F: drivers/i2c/busses/i2c-ocores.c
|
|||
OPEN FIRMWARE AND FLATTENED DEVICE TREE
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
M: Frank Rowand <frowand.list@gmail.com>
|
||||
M: Grant Likely <grant.likely@linaro.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
W: http://www.devicetree.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
|
||||
S: Maintained
|
||||
F: drivers/of/
|
||||
F: include/linux/of*.h
|
||||
|
@ -8418,12 +8431,10 @@ F: scripts/dtc/
|
|||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
M: Pawel Moll <pawel.moll@arm.com>
|
||||
M: Mark Rutland <mark.rutland@arm.com>
|
||||
M: Ian Campbell <ijc+devicetree@hellion.org.uk>
|
||||
M: Kumar Gala <galak@codeaurora.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
|
||||
Q: http://patchwork.ozlabs.org/project/devicetree-bindings/list/
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/
|
||||
F: arch/*/boot/dts/
|
||||
|
@ -9855,7 +9866,8 @@ S: Odd Fixes
|
|||
F: drivers/media/i2c/saa6588*
|
||||
|
||||
SAA7134 VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -10374,7 +10386,8 @@ S: Maintained
|
|||
F: drivers/media/radio/si4713/radio-usb-si4713.c
|
||||
|
||||
SIANO DVB DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -11140,7 +11153,8 @@ S: Maintained
|
|||
F: drivers/media/i2c/tda9840*
|
||||
|
||||
TEA5761 TUNER DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -11148,7 +11162,8 @@ S: Odd fixes
|
|||
F: drivers/media/tuners/tea5761.*
|
||||
|
||||
TEA5767 TUNER DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -11535,7 +11550,8 @@ F: include/linux/shmem_fs.h
|
|||
F: mm/shmem.c
|
||||
|
||||
TM6000 VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
@ -11889,7 +11905,8 @@ F: drivers/usb/common/usb-otg-fsm.c
|
|||
|
||||
USB OVER IP DRIVER
|
||||
M: Valentina Manea <valentina.manea.m@gmail.com>
|
||||
M: Shuah Khan <shuah.kh@samsung.com>
|
||||
M: Shuah Khan <shuahkh@osg.samsung.com>
|
||||
M: Shuah Khan <shuah@kernel.org>
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/usb/usbip_protocol.txt
|
||||
|
@ -11960,6 +11977,7 @@ L: linux-usb@vger.kernel.org
|
|||
W: http://www.linux-usb.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/usb/
|
||||
F: Documentation/usb/
|
||||
F: drivers/usb/
|
||||
F: include/linux/usb.h
|
||||
|
@ -12133,6 +12151,7 @@ VIRTIO CORE, NET AND BLOCK DRIVERS
|
|||
M: "Michael S. Tsirkin" <mst@redhat.com>
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/virtio/
|
||||
F: drivers/virtio/
|
||||
F: tools/virtio/
|
||||
F: drivers/net/virtio_net.c
|
||||
|
@ -12521,7 +12540,8 @@ S: Maintained
|
|||
F: arch/x86/entry/vdso/
|
||||
|
||||
XC2028/3028 TUNER DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
T: git git://linuxtv.org/media_tree.git
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 7
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Psychotic Stoned Sheep
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -606,6 +606,9 @@ config HAVE_ARCH_HASH
|
|||
file which provides platform-specific implementations of some
|
||||
functions in <linux/hash.h> or fs/namei.c.
|
||||
|
||||
config ISA_BUS_API
|
||||
def_bool ISA
|
||||
|
||||
#
|
||||
# ABI hall of shame
|
||||
#
|
||||
|
|
|
@ -741,6 +741,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
|
|||
sun7i-a20-olimex-som-evb.dtb \
|
||||
sun7i-a20-olinuxino-lime.dtb \
|
||||
sun7i-a20-olinuxino-lime2.dtb \
|
||||
sun7i-a20-olinuxino-lime2-emmc.dtb \
|
||||
sun7i-a20-olinuxino-micro.dtb \
|
||||
sun7i-a20-orangepi.dtb \
|
||||
sun7i-a20-orangepi-mini.dtb \
|
||||
|
|
|
@ -418,7 +418,7 @@
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
tps@24 {
|
||||
compatible = "ti,tps65218";
|
||||
|
|
|
@ -60,10 +60,26 @@
|
|||
|
||||
tps659038_pmic {
|
||||
compatible = "ti,tps659038-pmic";
|
||||
|
||||
smps12-in-supply = <&vmain>;
|
||||
smps3-in-supply = <&vmain>;
|
||||
smps45-in-supply = <&vmain>;
|
||||
smps6-in-supply = <&vmain>;
|
||||
smps7-in-supply = <&vmain>;
|
||||
smps8-in-supply = <&vmain>;
|
||||
smps9-in-supply = <&vmain>;
|
||||
ldo1-in-supply = <&vmain>;
|
||||
ldo2-in-supply = <&vmain>;
|
||||
ldo3-in-supply = <&vmain>;
|
||||
ldo4-in-supply = <&vmain>;
|
||||
ldo9-in-supply = <&vmain>;
|
||||
ldoln-in-supply = <&vmain>;
|
||||
ldousb-in-supply = <&vmain>;
|
||||
ldortc-in-supply = <&vmain>;
|
||||
|
||||
regulators {
|
||||
smps12_reg: smps12 {
|
||||
/* VDD_MPU */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps12";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
|
@ -73,7 +89,6 @@
|
|||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_DDR EMIF1 EMIF2 */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
|
@ -84,7 +99,6 @@
|
|||
smps45_reg: smps45 {
|
||||
/* VDD_DSPEVE on AM572 */
|
||||
/* VDD_IVA + VDD_DSP on AM571 */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
|
@ -94,7 +108,6 @@
|
|||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_GPU */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
|
@ -104,7 +117,6 @@
|
|||
|
||||
smps7_reg: smps7 {
|
||||
/* VDD_CORE */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps7";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
@ -115,13 +127,11 @@
|
|||
smps8_reg: smps8 {
|
||||
/* 5728 - VDD_IVAHD */
|
||||
/* 5718 - N.C. test point */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps8";
|
||||
};
|
||||
|
||||
smps9_reg: smps9 {
|
||||
/* VDD_3_3D */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "smps9";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -132,7 +142,6 @@
|
|||
ldo1_reg: ldo1 {
|
||||
/* VDDSHV8 - VSDMMC */
|
||||
/* NOTE: on rev 1.3a, data supply */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -142,7 +151,6 @@
|
|||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VDDSH18V */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -152,7 +160,6 @@
|
|||
|
||||
ldo3_reg: ldo3 {
|
||||
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -162,7 +169,6 @@
|
|||
|
||||
ldo4_reg: ldo4 {
|
||||
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -174,7 +180,6 @@
|
|||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VDD_RTC */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <840000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
|
@ -184,7 +189,6 @@
|
|||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1V8_PLL */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -194,7 +198,6 @@
|
|||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -204,7 +207,6 @@
|
|||
|
||||
ldortc_reg: ldortc {
|
||||
/* VDDA_RTC */
|
||||
vin-supply = <&vmain>;
|
||||
regulator-name = "ldortc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
|
|
@ -93,6 +93,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_pins>;
|
||||
|
@ -101,6 +105,10 @@
|
|||
cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pincntl {
|
||||
sd1_pins: pinmux_sd1_pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
|
@ -45,6 +45,14 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_pins>;
|
||||
|
@ -53,6 +61,7 @@
|
|||
dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */
|
||||
&edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */
|
||||
dma-names = "tx", "rx";
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&pincntl {
|
||||
|
|
|
@ -1451,6 +1451,8 @@
|
|||
ti,hwmods = "gpmc";
|
||||
reg = <0x50000000 0x37c>; /* device IO registers */
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma_xbar 4 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
|
|
|
@ -107,8 +107,8 @@
|
|||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
<0x58004300 0x20>,
|
||||
<0x58005054 0x4>,
|
||||
<0x58005300 0x20>;
|
||||
<0x58009054 0x4>,
|
||||
<0x58009300 0x20>;
|
||||
reg-names = "dss", "pll1_clkctrl", "pll1",
|
||||
"pll2_clkctrl", "pll2";
|
||||
|
||||
|
|
|
@ -242,7 +242,7 @@
|
|||
hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
port {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
|
@ -485,13 +485,20 @@
|
|||
edid-emulation = <5>;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port1 {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
|
|
|
@ -163,7 +163,7 @@
|
|||
hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
port {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
|
@ -631,13 +631,20 @@
|
|||
use-external-pwm;
|
||||
|
||||
ports {
|
||||
port0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port1 {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
|
|
|
@ -85,7 +85,7 @@
|
|||
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
|
||||
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
|
||||
>;
|
||||
|
|
|
@ -188,6 +188,7 @@
|
|||
vmmc-supply = <&vmmc1>;
|
||||
vmmc_aux-supply = <&vsim>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
|
|
|
@ -194,6 +194,12 @@
|
|||
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_wp_pins: pinmux_mmc1_cd_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
|
@ -250,3 +256,8 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
|
||||
wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
|
||||
};
|
||||
|
|
|
@ -288,7 +288,7 @@
|
|||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
|
||||
|
@ -300,7 +300,7 @@
|
|||
modem_pins: pinmux_modem {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
|
||||
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
|
||||
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
|
||||
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
|
||||
|
|
|
@ -97,7 +97,7 @@
|
|||
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
|
||||
|
@ -110,7 +110,7 @@
|
|||
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
|
||||
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */
|
||||
|
@ -120,7 +120,7 @@
|
|||
|
||||
modem_pins1: pinmux_modem_core1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
|
||||
OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
|
||||
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */
|
||||
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */
|
||||
>;
|
||||
|
|
|
@ -98,7 +98,7 @@
|
|||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
|
||||
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
|
||||
OMAP3_CORE1_IOPAD(0x217a, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
|
||||
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
|
||||
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
|
||||
>;
|
||||
};
|
||||
|
@ -107,7 +107,7 @@
|
|||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
|
||||
OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
|
||||
OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
|
||||
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
|
||||
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
|
||||
>;
|
||||
};
|
||||
|
@ -125,7 +125,7 @@
|
|||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
|
||||
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
|
||||
>;
|
||||
|
|
|
@ -14,6 +14,29 @@
|
|||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
vmain: fixedregulator-vmain {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vsys_cobra: fixedregulator-vsys_cobra {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_cobra";
|
||||
vin-supply = <&vmain>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vdds_1v8_main: fixedregulator-vdds_1v8_main {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdds_1v8_main";
|
||||
vin-supply = <&smps7_reg>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator-mmcsd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
|
@ -309,7 +332,7 @@
|
|||
|
||||
wlcore_irq_pin: pinmux_wlcore_irq_pin {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x40, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
|
||||
OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -409,6 +432,26 @@
|
|||
|
||||
ti,ldo6-vibrator;
|
||||
|
||||
smps123-in-supply = <&vsys_cobra>;
|
||||
smps45-in-supply = <&vsys_cobra>;
|
||||
smps6-in-supply = <&vsys_cobra>;
|
||||
smps7-in-supply = <&vsys_cobra>;
|
||||
smps8-in-supply = <&vsys_cobra>;
|
||||
smps9-in-supply = <&vsys_cobra>;
|
||||
smps10_out2-in-supply = <&vsys_cobra>;
|
||||
smps10_out1-in-supply = <&vsys_cobra>;
|
||||
ldo1-in-supply = <&vsys_cobra>;
|
||||
ldo2-in-supply = <&vsys_cobra>;
|
||||
ldo3-in-supply = <&vdds_1v8_main>;
|
||||
ldo4-in-supply = <&vdds_1v8_main>;
|
||||
ldo5-in-supply = <&vsys_cobra>;
|
||||
ldo6-in-supply = <&vdds_1v8_main>;
|
||||
ldo7-in-supply = <&vsys_cobra>;
|
||||
ldo8-in-supply = <&vsys_cobra>;
|
||||
ldo9-in-supply = <&vmmcsd_fixed>;
|
||||
ldoln-in-supply = <&vsys_cobra>;
|
||||
ldousb-in-supply = <&vsys_cobra>;
|
||||
|
||||
regulators {
|
||||
smps123_reg: smps123 {
|
||||
/* VDD_OPP_MPU */
|
||||
|
@ -600,7 +643,8 @@
|
|||
pinctrl-0 = <&twl6040_pins>;
|
||||
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
|
||||
ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
|
||||
|
||||
/* audpwron gpio defined in the board specific dts */
|
||||
|
||||
vio-supply = <&smps7_reg>;
|
||||
v2v1-supply = <&smps9_reg>;
|
||||
|
|
|
@ -35,6 +35,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* LDO4 is VPP1 - ball AD9 */
|
||||
&ldo4_reg {
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33,
|
||||
* VDDA_HDMI - ball AN25
|
||||
*/
|
||||
&ldo7_reg {
|
||||
status = "okay";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
&omap5_pmx_core {
|
||||
i2c4_pins: pinmux_i2c4_pins {
|
||||
pinctrl-single,pins = <
|
||||
|
@ -52,3 +68,13 @@
|
|||
<&gpio7 3 0>; /* 195, SDA */
|
||||
};
|
||||
|
||||
&twl6040 {
|
||||
ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */
|
||||
};
|
||||
|
||||
&twl6040_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */
|
||||
OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -51,3 +51,13 @@
|
|||
<&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
|
||||
<&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
|
||||
};
|
||||
|
||||
&twl6040 {
|
||||
ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
|
||||
};
|
||||
|
||||
&twl6040_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -136,6 +136,7 @@
|
|||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
|
|
|
@ -24,18 +24,21 @@
|
|||
compatible = "shared-dma-pool";
|
||||
reg = <0x40000000 0x01000000>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gp1_reserved: rproc@41000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x41000000 0x01000000>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audio_reserved: rproc@42000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x42000000 0x01000000>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmu_reserved: rproc@43000000 {
|
||||
|
|
|
@ -176,8 +176,6 @@
|
|||
};
|
||||
|
||||
®_dc1sw {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc-lcd";
|
||||
};
|
||||
|
||||
|
|
|
@ -135,8 +135,6 @@
|
|||
|
||||
®_dc1sw {
|
||||
regulator-name = "vcc-lcd-usb2";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
®_dc5ldo {
|
||||
|
|
|
@ -82,6 +82,7 @@ CONFIG_TOUCHSCREEN_MMS114=y
|
|||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_MAX77693_HAPTIC=y
|
||||
CONFIG_INPUT_MAX8997_HAPTIC=y
|
||||
CONFIG_KEYBOARD_SAMSUNG=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_SAMSUNG=y
|
||||
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
|
||||
|
|
|
@ -264,6 +264,7 @@ CONFIG_KEYBOARD_TEGRA=y
|
|||
CONFIG_KEYBOARD_SPEAR=y
|
||||
CONFIG_KEYBOARD_ST_KEYSCAN=y
|
||||
CONFIG_KEYBOARD_CROS_EC=m
|
||||
CONFIG_KEYBOARD_SAMSUNG=m
|
||||
CONFIG_MOUSE_PS2_ELANTECH=y
|
||||
CONFIG_MOUSE_CYAPA=m
|
||||
CONFIG_MOUSE_ELAN_I2C=y
|
||||
|
|
|
@ -193,6 +193,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
|
|||
|
||||
#define pmd_large(pmd) (pmd_val(pmd) & 2)
|
||||
#define pmd_bad(pmd) (pmd_val(pmd) & 2)
|
||||
#define pmd_present(pmd) (pmd_val(pmd))
|
||||
|
||||
#define copy_pmd(pmdpd,pmdps) \
|
||||
do { \
|
||||
|
|
|
@ -211,6 +211,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
|
|||
: !!(pmd_val(pmd) & (val)))
|
||||
#define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val)))
|
||||
|
||||
#define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID))
|
||||
#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
|
||||
#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
|
||||
static inline pte_t pte_mkspecial(pte_t pte)
|
||||
|
@ -249,10 +250,10 @@ PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
|
|||
#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
|
||||
#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
|
||||
|
||||
/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
|
||||
/* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
|
||||
static inline pmd_t pmd_mknotpresent(pmd_t pmd)
|
||||
{
|
||||
return __pmd(0);
|
||||
return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
|
||||
}
|
||||
|
||||
static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
|
||||
|
|
|
@ -182,7 +182,6 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
|
|||
#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
|
||||
|
||||
#define pmd_none(pmd) (!pmd_val(pmd))
|
||||
#define pmd_present(pmd) (pmd_val(pmd))
|
||||
|
||||
static inline pte_t *pmd_page_vaddr(pmd_t pmd)
|
||||
{
|
||||
|
|
|
@ -486,7 +486,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = {
|
|||
|
||||
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
|
||||
{
|
||||
trace_ipi_raise(target, ipi_types[ipinr]);
|
||||
trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
|
||||
__smp_cross_call(target, ipinr);
|
||||
}
|
||||
|
||||
|
|
|
@ -61,7 +61,6 @@ config ARCH_EXYNOS4
|
|||
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
|
||||
select CPU_EXYNOS4210
|
||||
select GIC_NON_BANKED
|
||||
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
help
|
||||
Samsung EXYNOS4 (Cortex-A9) SoC based systems
|
||||
|
|
|
@ -46,7 +46,7 @@ static int ksz8081_phy_fixup(struct phy_device *dev)
|
|||
static void __init imx6ul_enet_phy_init(void)
|
||||
{
|
||||
if (IS_BUILTIN(CONFIG_PHYLIB))
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff,
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
|
||||
ksz8081_phy_fixup);
|
||||
}
|
||||
|
||||
|
|
|
@ -43,8 +43,8 @@
|
|||
#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
|
||||
|
||||
/* IRQ handler register bitmasks */
|
||||
#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE))
|
||||
#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1)
|
||||
#define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
|
||||
#define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1)
|
||||
|
||||
/* Driver buffer byte offsets */
|
||||
#define BUF_MASK (FIQ_MASK * 4)
|
||||
|
@ -110,7 +110,7 @@ ENTRY(qwerty_fiqin_start)
|
|||
mov r8, #2 @ reset FIQ agreement
|
||||
str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
|
||||
|
||||
cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt?
|
||||
cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
|
||||
beq gpio @ yes - process it
|
||||
|
||||
mov r8, #1
|
||||
|
|
|
@ -109,7 +109,8 @@ void __init ams_delta_init_fiq(void)
|
|||
* Since no set_type() method is provided by OMAP irq chip,
|
||||
* switch to edge triggered interrupt type manually.
|
||||
*/
|
||||
offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
|
||||
offset = IRQ_ILR0_REG_OFFSET +
|
||||
((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
|
||||
val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
|
||||
omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
|
||||
|
||||
|
@ -149,7 +150,7 @@ void __init ams_delta_init_fiq(void)
|
|||
/*
|
||||
* Redirect GPIO interrupts to FIQ
|
||||
*/
|
||||
offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
|
||||
offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
|
||||
val = omap_readl(OMAP_IH1_BASE + offset) | 1;
|
||||
omap_writel(val, OMAP_IH1_BASE + offset);
|
||||
}
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
#ifndef __AMS_DELTA_FIQ_H
|
||||
#define __AMS_DELTA_FIQ_H
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
* Interrupt number used for passing control from FIQ to IRQ.
|
||||
* IRQ12, described as reserved, has been selected.
|
||||
|
|
|
@ -17,6 +17,7 @@ config ARCH_OMAP3
|
|||
select PM_OPP if PM
|
||||
select PM if CPU_IDLE
|
||||
select SOC_HAS_OMAP2_SDRC
|
||||
select ARM_ERRATA_430973
|
||||
|
||||
config ARCH_OMAP4
|
||||
bool "TI OMAP4"
|
||||
|
@ -36,6 +37,7 @@ config ARCH_OMAP4
|
|||
select PM if CPU_IDLE
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
select OMAP_INTERCONNECT
|
||||
|
||||
config SOC_OMAP5
|
||||
bool "TI OMAP5"
|
||||
|
@ -67,6 +69,8 @@ config SOC_AM43XX
|
|||
select HAVE_ARM_SCU
|
||||
select GENERIC_CLOCKEVENTS_BROADCAST
|
||||
select HAVE_ARM_TWD
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
|
||||
config SOC_DRA7XX
|
||||
bool "TI DRA7XX"
|
||||
|
@ -240,4 +244,12 @@ endmenu
|
|||
|
||||
endif
|
||||
|
||||
config OMAP5_ERRATA_801819
|
||||
bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
|
||||
depends on SOC_OMAP5 || SOC_DRA7XX
|
||||
help
|
||||
A livelock can occur in the L2 cache arbitration that might prevent
|
||||
a snoop from completing. Under certain conditions this can cause the
|
||||
system to deadlock.
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -46,6 +46,7 @@
|
|||
|
||||
#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
|
||||
#define OMAP5_MON_AMBA_IF_INDEX 0x108
|
||||
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
|
||||
|
||||
/* Secure PPA(Primary Protected Application) APIs */
|
||||
#define OMAP4_PPA_L2_POR_INDEX 0x23
|
||||
|
|
|
@ -50,6 +50,39 @@ void __iomem *omap4_get_scu_base(void)
|
|||
return scu_base;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP5_ERRATA_801819
|
||||
void omap5_erratum_workaround_801819(void)
|
||||
{
|
||||
u32 acr, revidr;
|
||||
u32 acr_mask;
|
||||
|
||||
/* REVIDR[3] indicates erratum fix available on silicon */
|
||||
asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
|
||||
if (revidr & (0x1 << 3))
|
||||
return;
|
||||
|
||||
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
|
||||
/*
|
||||
* BIT(27) - Disables streaming. All write-allocate lines allocate in
|
||||
* the L1 or L2 cache.
|
||||
* BIT(25) - Disables streaming. All write-allocate lines allocate in
|
||||
* the L1 cache.
|
||||
*/
|
||||
acr_mask = (0x3 << 25) | (0x3 << 27);
|
||||
/* do we already have it done.. if yes, skip expensive smc */
|
||||
if ((acr & acr_mask) == acr_mask)
|
||||
return;
|
||||
|
||||
acr |= acr_mask;
|
||||
omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
|
||||
|
||||
pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
|
||||
__func__, smp_processor_id());
|
||||
}
|
||||
#else
|
||||
static inline void omap5_erratum_workaround_801819(void) { }
|
||||
#endif
|
||||
|
||||
static void omap4_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
|
@ -64,12 +97,15 @@ static void omap4_secondary_init(unsigned int cpu)
|
|||
omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
|
||||
4, 0, 0, 0, 0, 0);
|
||||
|
||||
/*
|
||||
* Configure the CNTFRQ register for the secondary cpu's which
|
||||
* indicates the frequency of the cpu local timers.
|
||||
*/
|
||||
if (soc_is_omap54xx() || soc_is_dra7xx())
|
||||
if (soc_is_omap54xx() || soc_is_dra7xx()) {
|
||||
/*
|
||||
* Configure the CNTFRQ register for the secondary cpu's which
|
||||
* indicates the frequency of the cpu local timers.
|
||||
*/
|
||||
set_cntfreq();
|
||||
/* Configure ACR to disable streaming WA for 801819 */
|
||||
omap5_erratum_workaround_801819();
|
||||
}
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
|
@ -218,6 +254,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
|||
|
||||
if (cpu_is_omap446x())
|
||||
startup_addr = omap4460_secondary_startup;
|
||||
if (soc_is_dra74x() || soc_is_omap54xx())
|
||||
omap5_erratum_workaround_801819();
|
||||
|
||||
/*
|
||||
* Write the address of secondary startup routine into the
|
||||
|
|
|
@ -186,8 +186,9 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
|
|||
trace_state = (PWRDM_TRACE_STATES_FLAG |
|
||||
((next & OMAP_POWERSTATE_MASK) << 8) |
|
||||
((prev & OMAP_POWERSTATE_MASK) << 0));
|
||||
trace_power_domain_target(pwrdm->name, trace_state,
|
||||
smp_processor_id());
|
||||
trace_power_domain_target_rcuidle(pwrdm->name,
|
||||
trace_state,
|
||||
smp_processor_id());
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
@ -523,8 +524,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
|||
|
||||
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
|
||||
/* Trace the pwrdm desired target state */
|
||||
trace_power_domain_target(pwrdm->name, pwrst,
|
||||
smp_processor_id());
|
||||
trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
|
||||
smp_processor_id());
|
||||
/* Program the pwrdm desired target state */
|
||||
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
|
||||
}
|
||||
|
|
|
@ -36,14 +36,7 @@ static struct powerdomain iva_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_IVA_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 4,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* hwa_mem */
|
||||
[1] = PWRSTS_OFF_RET, /* sl2_mem */
|
||||
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
|
||||
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* hwa_mem */
|
||||
[1] = PWRSTS_ON, /* sl2_mem */
|
||||
|
@ -76,12 +69,7 @@ static struct powerdomain ipu_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_IPU_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 2,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* aessmem */
|
||||
[1] = PWRSTS_OFF_RET, /* periphmem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* aessmem */
|
||||
[1] = PWRSTS_ON, /* periphmem */
|
||||
|
@ -95,11 +83,7 @@ static struct powerdomain dss_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_DSS_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* dss_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dss_mem */
|
||||
},
|
||||
|
@ -111,13 +95,8 @@ static struct powerdomain l4per_7xx_pwrdm = {
|
|||
.name = "l4per_pwrdm",
|
||||
.prcm_offs = DRA7XX_PRM_L4PER_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 2,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* retained_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* nonretained_bank */
|
||||
[1] = PWRSTS_ON, /* retained_bank */
|
||||
|
@ -132,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* gpu_mem */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* gpu_mem */
|
||||
},
|
||||
|
@ -148,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* wkup_bank */
|
||||
},
|
||||
|
@ -161,15 +135,7 @@ static struct powerdomain core_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_CORE_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.banks = 5,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* core_ocmram */
|
||||
[2] = PWRSTS_OFF_RET, /* core_other_bank */
|
||||
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
|
||||
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* core_nret_bank */
|
||||
[1] = PWRSTS_ON, /* core_ocmram */
|
||||
|
@ -226,11 +192,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
|
|||
.prcm_offs = DRA7XX_PRM_VPE_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* vpe_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* vpe_bank */
|
||||
},
|
||||
|
@ -260,14 +222,8 @@ static struct powerdomain l3init_7xx_pwrdm = {
|
|||
.name = "l3init_pwrdm",
|
||||
.prcm_offs = DRA7XX_PRM_L3INIT_INST,
|
||||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* gmac_bank */
|
||||
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
|
||||
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* gmac_bank */
|
||||
[1] = PWRSTS_ON, /* l3init_bank1 */
|
||||
|
@ -283,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve3_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve3_bank */
|
||||
},
|
||||
|
@ -299,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* emu_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* emu_bank */
|
||||
},
|
||||
|
@ -314,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
|
||||
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
|
||||
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dsp2_edma */
|
||||
[1] = PWRSTS_ON, /* dsp2_l1 */
|
||||
|
@ -334,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
|
||||
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
|
||||
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* dsp1_edma */
|
||||
[1] = PWRSTS_ON, /* dsp1_l1 */
|
||||
|
@ -354,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* vip_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* vip_bank */
|
||||
},
|
||||
|
@ -370,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve4_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve4_bank */
|
||||
},
|
||||
|
@ -386,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve2_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve2_bank */
|
||||
},
|
||||
|
@ -402,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = {
|
|||
.prcm_partition = DRA7XX_PRM_PARTITION,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* eve1_bank */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* eve1_bank */
|
||||
},
|
||||
|
|
|
@ -496,8 +496,7 @@ void __init omap_init_time(void)
|
|||
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
|
||||
2, "timer_sys_ck", NULL, false);
|
||||
|
||||
if (of_have_populated_dt())
|
||||
clocksource_probe();
|
||||
clocksource_probe();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
|
||||
|
@ -505,6 +504,8 @@ void __init omap3_secure_sync32k_timer_init(void)
|
|||
{
|
||||
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
|
||||
2, "timer_sys_ck", NULL, false);
|
||||
|
||||
clocksource_probe();
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
|
@ -513,6 +514,8 @@ void __init omap3_gptimer_timer_init(void)
|
|||
{
|
||||
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
|
||||
1, "timer_sys_ck", "ti,timer-alwon", true);
|
||||
|
||||
clocksource_probe();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -68,7 +68,7 @@
|
|||
#include <linux/platform_data/asoc-s3c.h>
|
||||
#include <linux/platform_data/spi-s3c64xx.h>
|
||||
|
||||
static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
|
||||
#define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
|
||||
|
||||
/* AC97 */
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
|
|
|
@ -125,7 +125,7 @@
|
|||
#size-cells = <1>;
|
||||
#interrupts-cells = <3>;
|
||||
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
|
|
|
@ -163,7 +163,7 @@
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
|
@ -38,25 +38,54 @@ extern int kgdb_fault_expected;
|
|||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* gdb is expecting the following registers layout.
|
||||
* gdb remote procotol (well most versions of it) expects the following
|
||||
* register layout.
|
||||
*
|
||||
* General purpose regs:
|
||||
* r0-r30: 64 bit
|
||||
* sp,pc : 64 bit
|
||||
* pstate : 64 bit
|
||||
* Total: 34
|
||||
* pstate : 32 bit
|
||||
* Total: 33 + 1
|
||||
* FPU regs:
|
||||
* f0-f31: 128 bit
|
||||
* Total: 32
|
||||
* Extra regs
|
||||
* fpsr & fpcr: 32 bit
|
||||
* Total: 2
|
||||
* Total: 32 + 2
|
||||
*
|
||||
* To expand a little on the "most versions of it"... when the gdb remote
|
||||
* protocol for AArch64 was developed it depended on a statement in the
|
||||
* Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
|
||||
* and, as a result, allocated only 32-bits for the PSTATE in the remote
|
||||
* protocol. In fact this statement is still present in ARM DDI 0487A.i.
|
||||
*
|
||||
* Unfortunately "is a 32-bit register" has a very special meaning for
|
||||
* system registers. It means that "the upper bits, bits[63:32], are
|
||||
* RES0.". RES0 is heavily used in the ARM architecture documents as a
|
||||
* way to leave space for future architecture changes. So to translate a
|
||||
* little for people who don't spend their spare time reading ARM architecture
|
||||
* manuals, what "is a 32-bit register" actually means in this context is
|
||||
* "is a 64-bit register but one with no meaning allocated to any of the
|
||||
* upper 32-bits... *yet*".
|
||||
*
|
||||
* Perhaps then we should not be surprised that this has led to some
|
||||
* confusion. Specifically a patch, influenced by the above translation,
|
||||
* that extended PSTATE to 64-bit was accepted into gdb-7.7 but the patch
|
||||
* was reverted in gdb-7.8.1 and all later releases, when this was
|
||||
* discovered to be an undocumented protocol change.
|
||||
*
|
||||
* So... it is *not* wrong for us to only allocate 32-bits to PSTATE
|
||||
* here even though the kernel itself allocates 64-bits for the same
|
||||
* state. That is because this bit of code tells the kernel how the gdb
|
||||
* remote protocol (well most versions of it) describes the register state.
|
||||
*
|
||||
* Note that if you are using one of the versions of gdb that supports
|
||||
* the gdb-7.7 version of the protocol you cannot use kgdb directly
|
||||
* without providing a custom register description (gdb can load new
|
||||
* protocol descriptions at runtime).
|
||||
*/
|
||||
|
||||
#define _GP_REGS 34
|
||||
#define _GP_REGS 33
|
||||
#define _FP_REGS 32
|
||||
#define _EXTRA_REGS 2
|
||||
#define _EXTRA_REGS 3
|
||||
/*
|
||||
* general purpose registers size in bytes.
|
||||
* pstate is only 4 bytes. subtract 4 bytes
|
||||
|
|
|
@ -30,22 +30,53 @@ static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
|
|||
{
|
||||
unsigned int tmp;
|
||||
arch_spinlock_t lockval;
|
||||
u32 owner;
|
||||
|
||||
/*
|
||||
* Ensure prior spin_lock operations to other locks have completed
|
||||
* on this CPU before we test whether "lock" is locked.
|
||||
*/
|
||||
smp_mb();
|
||||
owner = READ_ONCE(lock->owner) << 16;
|
||||
|
||||
asm volatile(
|
||||
" sevl\n"
|
||||
"1: wfe\n"
|
||||
"2: ldaxr %w0, %2\n"
|
||||
/* Is the lock free? */
|
||||
" eor %w1, %w0, %w0, ror #16\n"
|
||||
" cbnz %w1, 1b\n"
|
||||
" cbz %w1, 3f\n"
|
||||
/* Lock taken -- has there been a subsequent unlock->lock transition? */
|
||||
" eor %w1, %w3, %w0, lsl #16\n"
|
||||
" cbz %w1, 1b\n"
|
||||
/*
|
||||
* The owner has been updated, so there was an unlock->lock
|
||||
* transition that we missed. That means we can rely on the
|
||||
* store-release of the unlock operation paired with the
|
||||
* load-acquire of the lock operation to publish any of our
|
||||
* previous stores to the new lock owner and therefore don't
|
||||
* need to bother with the writeback below.
|
||||
*/
|
||||
" b 4f\n"
|
||||
"3:\n"
|
||||
/*
|
||||
* Serialise against any concurrent lockers by writing back the
|
||||
* unlocked lock value
|
||||
*/
|
||||
ARM64_LSE_ATOMIC_INSN(
|
||||
/* LL/SC */
|
||||
" stxr %w1, %w0, %2\n"
|
||||
" cbnz %w1, 2b\n", /* Serialise against any concurrent lockers */
|
||||
/* LSE atomics */
|
||||
" nop\n"
|
||||
" nop\n")
|
||||
" nop\n",
|
||||
/* LSE atomics */
|
||||
" mov %w1, %w0\n"
|
||||
" cas %w0, %w0, %2\n"
|
||||
" eor %w1, %w1, %w0\n")
|
||||
/* Somebody else wrote to the lock, GOTO 10 and reload the value */
|
||||
" cbnz %w1, 2b\n"
|
||||
"4:"
|
||||
: "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
|
||||
:
|
||||
: "r" (owner)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
|
@ -148,6 +179,7 @@ static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
|
|||
|
||||
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
|
||||
{
|
||||
smp_mb(); /* See arch_spin_unlock_wait */
|
||||
return !arch_spin_value_unlocked(READ_ONCE(*lock));
|
||||
}
|
||||
|
||||
|
|
|
@ -58,7 +58,17 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
|
|||
{ "x30", 8, offsetof(struct pt_regs, regs[30])},
|
||||
{ "sp", 8, offsetof(struct pt_regs, sp)},
|
||||
{ "pc", 8, offsetof(struct pt_regs, pc)},
|
||||
{ "pstate", 8, offsetof(struct pt_regs, pstate)},
|
||||
/*
|
||||
* struct pt_regs thinks PSTATE is 64-bits wide but gdb remote
|
||||
* protocol disagrees. Therefore we must extract only the lower
|
||||
* 32-bits. Look for the big comment in asm/kgdb.h for more
|
||||
* detail.
|
||||
*/
|
||||
{ "pstate", 4, offsetof(struct pt_regs, pstate)
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
+ 4
|
||||
#endif
|
||||
},
|
||||
{ "v0", 16, -1 },
|
||||
{ "v1", 16, -1 },
|
||||
{ "v2", 16, -1 },
|
||||
|
@ -128,6 +138,8 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
|
|||
memset((char *)gdb_regs, 0, NUMREGBYTES);
|
||||
thread_regs = task_pt_regs(task);
|
||||
memcpy((void *)gdb_regs, (void *)thread_regs->regs, GP_REG_BYTES);
|
||||
/* Special case for PSTATE (check comments in asm/kgdb.h for details) */
|
||||
dbg_get_reg(33, gdb_regs + GP_REG_BYTES, thread_regs);
|
||||
}
|
||||
|
||||
void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
|
||||
|
|
|
@ -64,8 +64,7 @@ static void dump_mem(const char *lvl, const char *str, unsigned long bottom,
|
|||
|
||||
/*
|
||||
* We need to switch to kernel mode so that we can use __get_user
|
||||
* to safely read from kernel space. Note that we now dump the
|
||||
* code first, just in case the backtrace kills us.
|
||||
* to safely read from kernel space.
|
||||
*/
|
||||
fs = get_fs();
|
||||
set_fs(KERNEL_DS);
|
||||
|
@ -111,21 +110,12 @@ static void dump_backtrace_entry(unsigned long where)
|
|||
print_ip_sym(where);
|
||||
}
|
||||
|
||||
static void dump_instr(const char *lvl, struct pt_regs *regs)
|
||||
static void __dump_instr(const char *lvl, struct pt_regs *regs)
|
||||
{
|
||||
unsigned long addr = instruction_pointer(regs);
|
||||
mm_segment_t fs;
|
||||
char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* We need to switch to kernel mode so that we can use __get_user
|
||||
* to safely read from kernel space. Note that we now dump the
|
||||
* code first, just in case the backtrace kills us.
|
||||
*/
|
||||
fs = get_fs();
|
||||
set_fs(KERNEL_DS);
|
||||
|
||||
for (i = -4; i < 1; i++) {
|
||||
unsigned int val, bad;
|
||||
|
||||
|
@ -139,8 +129,18 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
|
|||
}
|
||||
}
|
||||
printk("%sCode: %s\n", lvl, str);
|
||||
}
|
||||
|
||||
set_fs(fs);
|
||||
static void dump_instr(const char *lvl, struct pt_regs *regs)
|
||||
{
|
||||
if (!user_mode(regs)) {
|
||||
mm_segment_t fs = get_fs();
|
||||
set_fs(KERNEL_DS);
|
||||
__dump_instr(lvl, regs);
|
||||
set_fs(fs);
|
||||
} else {
|
||||
__dump_instr(lvl, regs);
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
|
||||
|
|
|
@ -441,7 +441,7 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static struct fault_info {
|
||||
static const struct fault_info {
|
||||
int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs);
|
||||
int sig;
|
||||
int code;
|
||||
|
|
|
@ -74,7 +74,7 @@
|
|||
#define KVM_GUEST_KUSEG 0x00000000UL
|
||||
#define KVM_GUEST_KSEG0 0x40000000UL
|
||||
#define KVM_GUEST_KSEG23 0x60000000UL
|
||||
#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
|
||||
#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
|
||||
#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
|
||||
|
||||
#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
|
||||
|
@ -338,6 +338,7 @@ struct kvm_mips_tlb {
|
|||
#define KVM_MIPS_GUEST_TLB_SIZE 64
|
||||
struct kvm_vcpu_arch {
|
||||
void *host_ebase, *guest_ebase;
|
||||
int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
|
||||
unsigned long host_stack;
|
||||
unsigned long host_gp;
|
||||
|
||||
|
|
|
@ -1636,6 +1636,7 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
|
|||
if (index < 0) {
|
||||
vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
|
||||
vcpu->arch.host_cp0_badvaddr = va;
|
||||
vcpu->arch.pc = curr_pc;
|
||||
er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
|
||||
vcpu);
|
||||
preempt_enable();
|
||||
|
@ -1647,6 +1648,8 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
|
|||
* invalid exception to the guest
|
||||
*/
|
||||
if (!TLB_IS_VALID(*tlb, va)) {
|
||||
vcpu->arch.host_cp0_badvaddr = va;
|
||||
vcpu->arch.pc = curr_pc;
|
||||
er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
|
||||
run, vcpu);
|
||||
preempt_enable();
|
||||
|
@ -1666,7 +1669,7 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
|
|||
cache, op, base, arch->gprs[base], offset);
|
||||
er = EMULATE_FAIL;
|
||||
preempt_enable();
|
||||
goto dont_update_pc;
|
||||
goto done;
|
||||
|
||||
}
|
||||
|
||||
|
@ -1694,16 +1697,20 @@ skip_fault:
|
|||
kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
|
||||
cache, op, base, arch->gprs[base], offset);
|
||||
er = EMULATE_FAIL;
|
||||
preempt_enable();
|
||||
goto dont_update_pc;
|
||||
}
|
||||
|
||||
preempt_enable();
|
||||
done:
|
||||
/* Rollback PC only if emulation was unsuccessful */
|
||||
if (er == EMULATE_FAIL)
|
||||
vcpu->arch.pc = curr_pc;
|
||||
|
||||
dont_update_pc:
|
||||
/* Rollback PC */
|
||||
vcpu->arch.pc = curr_pc;
|
||||
done:
|
||||
/*
|
||||
* This is for exceptions whose emulation updates the PC, so do not
|
||||
* overwrite the PC under any circumstances
|
||||
*/
|
||||
|
||||
return er;
|
||||
}
|
||||
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#define MIPS_EXC_MAX 12
|
||||
/* XXXSL More to follow */
|
||||
|
||||
extern char __kvm_mips_vcpu_run_end[];
|
||||
extern char mips32_exception[], mips32_exceptionEnd[];
|
||||
extern char mips32_GuestException[], mips32_GuestExceptionEnd[];
|
||||
|
||||
|
|
|
@ -202,6 +202,7 @@ FEXPORT(__kvm_mips_load_k0k1)
|
|||
|
||||
/* Jump to guest */
|
||||
eret
|
||||
EXPORT(__kvm_mips_vcpu_run_end)
|
||||
|
||||
VECTOR(MIPSX(exception), unknown)
|
||||
/* Find out what mode we came from and jump to the proper handler. */
|
||||
|
|
|
@ -315,6 +315,15 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
|
|||
memcpy(gebase + offset, mips32_GuestException,
|
||||
mips32_GuestExceptionEnd - mips32_GuestException);
|
||||
|
||||
#ifdef MODULE
|
||||
offset += mips32_GuestExceptionEnd - mips32_GuestException;
|
||||
memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
|
||||
__kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
|
||||
vcpu->arch.vcpu_run = gebase + offset;
|
||||
#else
|
||||
vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
|
||||
#endif
|
||||
|
||||
/* Invalidate the icache for these ranges */
|
||||
local_flush_icache_range((unsigned long)gebase,
|
||||
(unsigned long)gebase + ALIGN(size, PAGE_SIZE));
|
||||
|
@ -404,7 +413,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
|||
/* Disable hardware page table walking while in guest */
|
||||
htw_stop();
|
||||
|
||||
r = __kvm_mips_vcpu_run(run, vcpu);
|
||||
r = vcpu->arch.vcpu_run(run, vcpu);
|
||||
|
||||
/* Re-enable HTW before enabling interrupts */
|
||||
htw_start();
|
||||
|
|
|
@ -245,6 +245,7 @@ struct kvm_vcpu_stat {
|
|||
u32 exit_stop_request;
|
||||
u32 exit_validity;
|
||||
u32 exit_instruction;
|
||||
u32 exit_pei;
|
||||
u32 halt_successful_poll;
|
||||
u32 halt_attempted_poll;
|
||||
u32 halt_poll_invalid;
|
||||
|
|
|
@ -341,6 +341,8 @@ static int handle_mvpg_pei(struct kvm_vcpu *vcpu)
|
|||
|
||||
static int handle_partial_execution(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
vcpu->stat.exit_pei++;
|
||||
|
||||
if (vcpu->arch.sie_block->ipa == 0xb254) /* MVPG */
|
||||
return handle_mvpg_pei(vcpu);
|
||||
if (vcpu->arch.sie_block->ipa >> 8 == 0xae) /* SIGP */
|
||||
|
|
|
@ -61,6 +61,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
|
|||
{ "exit_external_request", VCPU_STAT(exit_external_request) },
|
||||
{ "exit_external_interrupt", VCPU_STAT(exit_external_interrupt) },
|
||||
{ "exit_instruction", VCPU_STAT(exit_instruction) },
|
||||
{ "exit_pei", VCPU_STAT(exit_pei) },
|
||||
{ "exit_program_interruption", VCPU_STAT(exit_program_interruption) },
|
||||
{ "exit_instr_and_program_int", VCPU_STAT(exit_instr_and_program) },
|
||||
{ "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
|
||||
|
@ -657,7 +658,7 @@ static int kvm_s390_set_processor(struct kvm *kvm, struct kvm_device_attr *attr)
|
|||
kvm->arch.model.cpuid = proc->cpuid;
|
||||
lowest_ibc = sclp.ibc >> 16 & 0xfff;
|
||||
unblocked_ibc = sclp.ibc & 0xfff;
|
||||
if (lowest_ibc) {
|
||||
if (lowest_ibc && proc->ibc) {
|
||||
if (proc->ibc > unblocked_ibc)
|
||||
kvm->arch.model.ibc = unblocked_ibc;
|
||||
else if (proc->ibc < lowest_ibc)
|
||||
|
|
|
@ -2439,6 +2439,15 @@ config PCI_CNB20LE_QUIRK
|
|||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
config ISA_BUS
|
||||
bool "ISA-style bus support on modern systems" if EXPERT
|
||||
select ISA_BUS_API
|
||||
help
|
||||
Enables ISA-style drivers on modern systems. This is necessary to
|
||||
support PC/104 devices on X86_64 platforms.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
# x86_64 have no ISA slots, but can have ISA-style DMA.
|
||||
config ISA_DMA_API
|
||||
bool "ISA-style DMA support" if (X86_64 && EXPERT)
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/irqbypass.h>
|
||||
#include <linux/hyperv.h>
|
||||
|
||||
#include <asm/apic.h>
|
||||
#include <asm/pvclock-abi.h>
|
||||
#include <asm/desc.h>
|
||||
#include <asm/mtrr.h>
|
||||
|
@ -1368,4 +1369,14 @@ static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
|
|||
|
||||
static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
|
||||
|
||||
static inline int kvm_cpu_get_apicid(int mps_cpu)
|
||||
{
|
||||
#ifdef CONFIG_X86_LOCAL_APIC
|
||||
return __default_cpu_present_to_apicid(mps_cpu);
|
||||
#else
|
||||
WARN_ON_ONCE(1);
|
||||
return BAD_APICID;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* _ASM_X86_KVM_HOST_H */
|
||||
|
|
|
@ -238,7 +238,9 @@ module_param(nested, int, S_IRUGO);
|
|||
|
||||
/* enable / disable AVIC */
|
||||
static int avic;
|
||||
#ifdef CONFIG_X86_LOCAL_APIC
|
||||
module_param(avic, int, S_IRUGO);
|
||||
#endif
|
||||
|
||||
static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
|
||||
static void svm_flush_tlb(struct kvm_vcpu *vcpu);
|
||||
|
@ -981,11 +983,14 @@ static __init int svm_hardware_setup(void)
|
|||
} else
|
||||
kvm_disable_tdp();
|
||||
|
||||
if (avic && (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC)))
|
||||
avic = false;
|
||||
|
||||
if (avic)
|
||||
pr_info("AVIC enabled\n");
|
||||
if (avic) {
|
||||
if (!npt_enabled ||
|
||||
!boot_cpu_has(X86_FEATURE_AVIC) ||
|
||||
!IS_ENABLED(CONFIG_X86_LOCAL_APIC))
|
||||
avic = false;
|
||||
else
|
||||
pr_info("AVIC enabled\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
@ -1324,7 +1329,7 @@ free_avic:
|
|||
static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
|
||||
{
|
||||
u64 entry;
|
||||
int h_physical_id = __default_cpu_present_to_apicid(vcpu->cpu);
|
||||
int h_physical_id = kvm_cpu_get_apicid(vcpu->cpu);
|
||||
struct vcpu_svm *svm = to_svm(vcpu);
|
||||
|
||||
if (!kvm_vcpu_apicv_active(vcpu))
|
||||
|
@ -1349,7 +1354,7 @@ static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
{
|
||||
u64 entry;
|
||||
/* ID = 0xff (broadcast), ID > 0xff (reserved) */
|
||||
int h_physical_id = __default_cpu_present_to_apicid(cpu);
|
||||
int h_physical_id = kvm_cpu_get_apicid(cpu);
|
||||
struct vcpu_svm *svm = to_svm(vcpu);
|
||||
|
||||
if (!kvm_vcpu_apicv_active(vcpu))
|
||||
|
@ -4236,7 +4241,7 @@ static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
|
|||
|
||||
if (avic_vcpu_is_running(vcpu))
|
||||
wrmsrl(SVM_AVIC_DOORBELL,
|
||||
__default_cpu_present_to_apicid(vcpu->cpu));
|
||||
kvm_cpu_get_apicid(vcpu->cpu));
|
||||
else
|
||||
kvm_vcpu_wake_up(vcpu);
|
||||
}
|
||||
|
|
|
@ -2072,7 +2072,8 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
unsigned int dest;
|
||||
|
||||
if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP))
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP) ||
|
||||
!kvm_vcpu_apicv_active(vcpu))
|
||||
return;
|
||||
|
||||
do {
|
||||
|
@ -2180,7 +2181,8 @@ static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
|
|||
struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
|
||||
|
||||
if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP))
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP) ||
|
||||
!kvm_vcpu_apicv_active(vcpu))
|
||||
return;
|
||||
|
||||
/* Set SN when the vCPU is preempted */
|
||||
|
@ -10714,7 +10716,8 @@ static int vmx_pre_block(struct kvm_vcpu *vcpu)
|
|||
struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
|
||||
|
||||
if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP))
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP) ||
|
||||
!kvm_vcpu_apicv_active(vcpu))
|
||||
return 0;
|
||||
|
||||
vcpu->pre_pcpu = vcpu->cpu;
|
||||
|
@ -10780,7 +10783,8 @@ static void vmx_post_block(struct kvm_vcpu *vcpu)
|
|||
unsigned long flags;
|
||||
|
||||
if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP))
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP) ||
|
||||
!kvm_vcpu_apicv_active(vcpu))
|
||||
return;
|
||||
|
||||
do {
|
||||
|
@ -10833,7 +10837,8 @@ static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
|
|||
int idx, ret = -EINVAL;
|
||||
|
||||
if (!kvm_arch_has_assigned_device(kvm) ||
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP))
|
||||
!irq_remapping_cap(IRQ_POSTING_CAP) ||
|
||||
!kvm_vcpu_apicv_active(kvm->vcpus[0]))
|
||||
return 0;
|
||||
|
||||
idx = srcu_read_lock(&kvm->irq_srcu);
|
||||
|
|
|
@ -113,6 +113,7 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector,
|
|||
ret = submit_bio_wait(type, bio);
|
||||
if (ret == -EOPNOTSUPP)
|
||||
ret = 0;
|
||||
bio_put(bio);
|
||||
}
|
||||
blk_finish_plug(&plug);
|
||||
|
||||
|
@ -165,8 +166,10 @@ int blkdev_issue_write_same(struct block_device *bdev, sector_t sector,
|
|||
}
|
||||
}
|
||||
|
||||
if (bio)
|
||||
if (bio) {
|
||||
ret = submit_bio_wait(REQ_WRITE | REQ_WRITE_SAME, bio);
|
||||
bio_put(bio);
|
||||
}
|
||||
return ret != -EOPNOTSUPP ? ret : 0;
|
||||
}
|
||||
EXPORT_SYMBOL(blkdev_issue_write_same);
|
||||
|
@ -206,8 +209,11 @@ static int __blkdev_issue_zeroout(struct block_device *bdev, sector_t sector,
|
|||
}
|
||||
}
|
||||
|
||||
if (bio)
|
||||
return submit_bio_wait(WRITE, bio);
|
||||
if (bio) {
|
||||
ret = submit_bio_wait(WRITE, bio);
|
||||
bio_put(bio);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -1262,12 +1262,9 @@ static blk_qc_t blk_mq_make_request(struct request_queue *q, struct bio *bio)
|
|||
|
||||
blk_queue_split(q, &bio, q->bio_split);
|
||||
|
||||
if (!is_flush_fua && !blk_queue_nomerges(q)) {
|
||||
if (blk_attempt_plug_merge(q, bio, &request_count,
|
||||
&same_queue_rq))
|
||||
return BLK_QC_T_NONE;
|
||||
} else
|
||||
request_count = blk_plug_queued_count(q);
|
||||
if (!is_flush_fua && !blk_queue_nomerges(q) &&
|
||||
blk_attempt_plug_merge(q, bio, &request_count, &same_queue_rq))
|
||||
return BLK_QC_T_NONE;
|
||||
|
||||
rq = blk_mq_map_request(q, bio, &data);
|
||||
if (unlikely(!rq))
|
||||
|
@ -1358,9 +1355,11 @@ static blk_qc_t blk_sq_make_request(struct request_queue *q, struct bio *bio)
|
|||
|
||||
blk_queue_split(q, &bio, q->bio_split);
|
||||
|
||||
if (!is_flush_fua && !blk_queue_nomerges(q) &&
|
||||
blk_attempt_plug_merge(q, bio, &request_count, NULL))
|
||||
return BLK_QC_T_NONE;
|
||||
if (!is_flush_fua && !blk_queue_nomerges(q)) {
|
||||
if (blk_attempt_plug_merge(q, bio, &request_count, NULL))
|
||||
return BLK_QC_T_NONE;
|
||||
} else
|
||||
request_count = blk_plug_queued_count(q);
|
||||
|
||||
rq = blk_mq_map_request(q, bio, &data);
|
||||
if (unlikely(!rq))
|
||||
|
|
|
@ -306,12 +306,6 @@ acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
|
|||
acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
|
||||
{
|
||||
u64 address;
|
||||
u8 access_width;
|
||||
u32 bit_width;
|
||||
u8 bit_offset;
|
||||
u64 value64;
|
||||
u32 new_value32, old_value32;
|
||||
u8 index;
|
||||
acpi_status status;
|
||||
|
||||
ACPI_FUNCTION_NAME(hw_write);
|
||||
|
@ -323,145 +317,23 @@ acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
|
|||
return (status);
|
||||
}
|
||||
|
||||
/* Convert access_width into number of bits based */
|
||||
|
||||
access_width = acpi_hw_get_access_bit_width(reg, 32);
|
||||
bit_width = reg->bit_offset + reg->bit_width;
|
||||
bit_offset = reg->bit_offset;
|
||||
|
||||
/*
|
||||
* Two address spaces supported: Memory or IO. PCI_Config is
|
||||
* not supported here because the GAS structure is insufficient
|
||||
*/
|
||||
index = 0;
|
||||
while (bit_width) {
|
||||
/*
|
||||
* Use offset style bit reads because "Index * AccessWidth" is
|
||||
* ensured to be less than 32-bits by acpi_hw_validate_register().
|
||||
*/
|
||||
new_value32 = ACPI_GET_BITS(&value, index * access_width,
|
||||
ACPI_MASK_BITS_ABOVE_32
|
||||
(access_width));
|
||||
if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
|
||||
status = acpi_os_write_memory((acpi_physical_address)
|
||||
address, (u64)value,
|
||||
reg->bit_width);
|
||||
} else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
|
||||
|
||||
if (bit_offset >= access_width) {
|
||||
bit_offset -= access_width;
|
||||
} else {
|
||||
/*
|
||||
* Use offset style bit masks because access_width is ensured
|
||||
* to be less than 32-bits by acpi_hw_validate_register() and
|
||||
* bit_offset/bit_width is less than access_width here.
|
||||
*/
|
||||
if (bit_offset) {
|
||||
new_value32 &= ACPI_MASK_BITS_BELOW(bit_offset);
|
||||
}
|
||||
if (bit_width < access_width) {
|
||||
new_value32 &= ACPI_MASK_BITS_ABOVE(bit_width);
|
||||
}
|
||||
|
||||
if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
|
||||
if (bit_offset || bit_width < access_width) {
|
||||
/*
|
||||
* Read old values in order not to modify the bits that
|
||||
* are beyond the register bit_width/bit_offset setting.
|
||||
*/
|
||||
status =
|
||||
acpi_os_read_memory((acpi_physical_address)
|
||||
address +
|
||||
index *
|
||||
ACPI_DIV_8
|
||||
(access_width),
|
||||
&value64,
|
||||
access_width);
|
||||
old_value32 = (u32)value64;
|
||||
|
||||
/*
|
||||
* Use offset style bit masks because access_width is
|
||||
* ensured to be less than 32-bits by
|
||||
* acpi_hw_validate_register() and bit_offset/bit_width is
|
||||
* less than access_width here.
|
||||
*/
|
||||
if (bit_offset) {
|
||||
old_value32 &=
|
||||
ACPI_MASK_BITS_ABOVE
|
||||
(bit_offset);
|
||||
bit_offset = 0;
|
||||
}
|
||||
if (bit_width < access_width) {
|
||||
old_value32 &=
|
||||
ACPI_MASK_BITS_BELOW
|
||||
(bit_width);
|
||||
}
|
||||
|
||||
new_value32 |= old_value32;
|
||||
}
|
||||
|
||||
value64 = (u64)new_value32;
|
||||
status =
|
||||
acpi_os_write_memory((acpi_physical_address)
|
||||
address +
|
||||
index *
|
||||
ACPI_DIV_8
|
||||
(access_width),
|
||||
value64, access_width);
|
||||
} else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
|
||||
|
||||
if (bit_offset || bit_width < access_width) {
|
||||
/*
|
||||
* Read old values in order not to modify the bits that
|
||||
* are beyond the register bit_width/bit_offset setting.
|
||||
*/
|
||||
status =
|
||||
acpi_hw_read_port((acpi_io_address)
|
||||
address +
|
||||
index *
|
||||
ACPI_DIV_8
|
||||
(access_width),
|
||||
&old_value32,
|
||||
access_width);
|
||||
|
||||
/*
|
||||
* Use offset style bit masks because access_width is
|
||||
* ensured to be less than 32-bits by
|
||||
* acpi_hw_validate_register() and bit_offset/bit_width is
|
||||
* less than access_width here.
|
||||
*/
|
||||
if (bit_offset) {
|
||||
old_value32 &=
|
||||
ACPI_MASK_BITS_ABOVE
|
||||
(bit_offset);
|
||||
bit_offset = 0;
|
||||
}
|
||||
if (bit_width < access_width) {
|
||||
old_value32 &=
|
||||
ACPI_MASK_BITS_BELOW
|
||||
(bit_width);
|
||||
}
|
||||
|
||||
new_value32 |= old_value32;
|
||||
}
|
||||
|
||||
status = acpi_hw_write_port((acpi_io_address)
|
||||
address +
|
||||
index *
|
||||
ACPI_DIV_8
|
||||
(access_width),
|
||||
new_value32,
|
||||
access_width);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Index * access_width is ensured to be less than 32-bits by
|
||||
* acpi_hw_validate_register().
|
||||
*/
|
||||
bit_width -=
|
||||
bit_width > access_width ? access_width : bit_width;
|
||||
index++;
|
||||
status = acpi_hw_write_port((acpi_io_address)
|
||||
address, value, reg->bit_width);
|
||||
}
|
||||
|
||||
ACPI_DEBUG_PRINT((ACPI_DB_IO,
|
||||
"Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
|
||||
value, access_width, ACPI_FORMAT_UINT64(address),
|
||||
value, reg->bit_width, ACPI_FORMAT_UINT64(address),
|
||||
acpi_ut_get_region_name(reg->space_id)));
|
||||
|
||||
return (status);
|
||||
|
|
|
@ -10,7 +10,7 @@ obj-$(CONFIG_DMA_CMA) += dma-contiguous.o
|
|||
obj-y += power/
|
||||
obj-$(CONFIG_HAS_DMA) += dma-mapping.o
|
||||
obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o
|
||||
obj-$(CONFIG_ISA) += isa.o
|
||||
obj-$(CONFIG_ISA_BUS_API) += isa.o
|
||||
obj-$(CONFIG_FW_LOADER) += firmware_class.o
|
||||
obj-$(CONFIG_NUMA) += node.o
|
||||
obj-$(CONFIG_MEMORY_HOTPLUG_SPARSE) += memory.o
|
||||
|
|
|
@ -180,4 +180,4 @@ static int __init isa_bus_init(void)
|
|||
return error;
|
||||
}
|
||||
|
||||
device_initcall(isa_bus_init);
|
||||
postcore_initcall(isa_bus_init);
|
||||
|
|
|
@ -24,10 +24,12 @@ static char *make_driver_name(struct device_driver *drv)
|
|||
|
||||
static void module_create_drivers_dir(struct module_kobject *mk)
|
||||
{
|
||||
if (!mk || mk->drivers_dir)
|
||||
return;
|
||||
static DEFINE_MUTEX(drivers_dir_mutex);
|
||||
|
||||
mk->drivers_dir = kobject_create_and_add("drivers", &mk->kobj);
|
||||
mutex_lock(&drivers_dir_mutex);
|
||||
if (mk && !mk->drivers_dir)
|
||||
mk->drivers_dir = kobject_create_and_add("drivers", &mk->kobj);
|
||||
mutex_unlock(&drivers_dir_mutex);
|
||||
}
|
||||
|
||||
void module_add_driver(struct module *mod, struct device_driver *drv)
|
||||
|
|
|
@ -211,7 +211,7 @@ int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev,
|
|||
}
|
||||
|
||||
/* Mark opp-table as multiple CPUs are sharing it now */
|
||||
opp_table->shared_opp = true;
|
||||
opp_table->shared_opp = OPP_TABLE_ACCESS_SHARED;
|
||||
}
|
||||
unlock:
|
||||
mutex_unlock(&opp_table_lock);
|
||||
|
@ -227,7 +227,8 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_set_sharing_cpus);
|
|||
*
|
||||
* This updates the @cpumask with CPUs that are sharing OPPs with @cpu_dev.
|
||||
*
|
||||
* Returns -ENODEV if OPP table isn't already present.
|
||||
* Returns -ENODEV if OPP table isn't already present and -EINVAL if the OPP
|
||||
* table's status is access-unknown.
|
||||
*
|
||||
* Locking: The internal opp_table and opp structures are RCU protected.
|
||||
* Hence this function internally uses RCU updater strategy with mutex locks
|
||||
|
@ -249,9 +250,14 @@ int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask)
|
|||
goto unlock;
|
||||
}
|
||||
|
||||
if (opp_table->shared_opp == OPP_TABLE_ACCESS_UNKNOWN) {
|
||||
ret = -EINVAL;
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
cpumask_clear(cpumask);
|
||||
|
||||
if (opp_table->shared_opp) {
|
||||
if (opp_table->shared_opp == OPP_TABLE_ACCESS_SHARED) {
|
||||
list_for_each_entry(opp_dev, &opp_table->dev_list, node)
|
||||
cpumask_set_cpu(opp_dev->dev->id, cpumask);
|
||||
} else {
|
||||
|
|
|
@ -34,7 +34,10 @@ static struct opp_table *_managed_opp(const struct device_node *np)
|
|||
* But the OPPs will be considered as shared only if the
|
||||
* OPP table contains a "opp-shared" property.
|
||||
*/
|
||||
return opp_table->shared_opp ? opp_table : NULL;
|
||||
if (opp_table->shared_opp == OPP_TABLE_ACCESS_SHARED)
|
||||
return opp_table;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -353,7 +356,10 @@ static int _of_add_opp_table_v2(struct device *dev, struct device_node *opp_np)
|
|||
}
|
||||
|
||||
opp_table->np = opp_np;
|
||||
opp_table->shared_opp = of_property_read_bool(opp_np, "opp-shared");
|
||||
if (of_property_read_bool(opp_np, "opp-shared"))
|
||||
opp_table->shared_opp = OPP_TABLE_ACCESS_SHARED;
|
||||
else
|
||||
opp_table->shared_opp = OPP_TABLE_ACCESS_EXCLUSIVE;
|
||||
|
||||
mutex_unlock(&opp_table_lock);
|
||||
|
||||
|
|
|
@ -119,6 +119,12 @@ struct opp_device {
|
|||
#endif
|
||||
};
|
||||
|
||||
enum opp_table_access {
|
||||
OPP_TABLE_ACCESS_UNKNOWN = 0,
|
||||
OPP_TABLE_ACCESS_EXCLUSIVE = 1,
|
||||
OPP_TABLE_ACCESS_SHARED = 2,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct opp_table - Device opp structure
|
||||
* @node: table node - contains the devices with OPPs that
|
||||
|
@ -166,7 +172,7 @@ struct opp_table {
|
|||
/* For backward compatibility with v1 bindings */
|
||||
unsigned int voltage_tolerance_v1;
|
||||
|
||||
bool shared_opp;
|
||||
enum opp_table_access shared_opp;
|
||||
struct dev_pm_opp *suspend_opp;
|
||||
|
||||
unsigned int *supported_hw;
|
||||
|
|
|
@ -941,7 +941,7 @@ static int nbd_dev_dbg_init(struct nbd_device *nbd)
|
|||
debugfs_create_u64("size_bytes", 0444, dir, &nbd->bytesize);
|
||||
debugfs_create_u32("timeout", 0444, dir, &nbd->xmit_timeout);
|
||||
debugfs_create_u32("blocksize", 0444, dir, &nbd->blksize);
|
||||
debugfs_create_file("flags", 0444, dir, &nbd, &nbd_dbg_flags_ops);
|
||||
debugfs_create_file("flags", 0444, dir, nbd, &nbd_dbg_flags_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -874,8 +874,12 @@ static int blkif_queue_rq(struct blk_mq_hw_ctx *hctx,
|
|||
const struct blk_mq_queue_data *qd)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct blkfront_ring_info *rinfo = (struct blkfront_ring_info *)hctx->driver_data;
|
||||
int qid = hctx->queue_num;
|
||||
struct blkfront_info *info = hctx->queue->queuedata;
|
||||
struct blkfront_ring_info *rinfo = NULL;
|
||||
|
||||
BUG_ON(info->nr_rings <= qid);
|
||||
rinfo = &info->rinfo[qid];
|
||||
blk_mq_start_request(qd->rq);
|
||||
spin_lock_irqsave(&rinfo->ring_lock, flags);
|
||||
if (RING_FULL(&rinfo->ring))
|
||||
|
@ -901,20 +905,9 @@ out_busy:
|
|||
return BLK_MQ_RQ_QUEUE_BUSY;
|
||||
}
|
||||
|
||||
static int blk_mq_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
|
||||
unsigned int index)
|
||||
{
|
||||
struct blkfront_info *info = (struct blkfront_info *)data;
|
||||
|
||||
BUG_ON(info->nr_rings <= index);
|
||||
hctx->driver_data = &info->rinfo[index];
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct blk_mq_ops blkfront_mq_ops = {
|
||||
.queue_rq = blkif_queue_rq,
|
||||
.map_queue = blk_mq_map_queue,
|
||||
.init_hctx = blk_mq_init_hctx,
|
||||
};
|
||||
|
||||
static int xlvbd_init_blk_queue(struct gendisk *gd, u16 sector_size,
|
||||
|
@ -950,6 +943,7 @@ static int xlvbd_init_blk_queue(struct gendisk *gd, u16 sector_size,
|
|||
return PTR_ERR(rq);
|
||||
}
|
||||
|
||||
rq->queuedata = info;
|
||||
queue_flag_set_unlocked(QUEUE_FLAG_VIRT, rq);
|
||||
|
||||
if (info->feature_discard) {
|
||||
|
@ -2149,6 +2143,8 @@ static int blkfront_resume(struct xenbus_device *dev)
|
|||
return err;
|
||||
|
||||
err = talk_to_blkback(dev, info);
|
||||
if (!err)
|
||||
blk_mq_update_nr_hw_queues(&info->tag_set, info->nr_rings);
|
||||
|
||||
/*
|
||||
* We have to wait for the backend to switch to
|
||||
|
@ -2485,10 +2481,23 @@ static void blkback_changed(struct xenbus_device *dev,
|
|||
break;
|
||||
|
||||
case XenbusStateConnected:
|
||||
if (dev->state != XenbusStateInitialised) {
|
||||
/*
|
||||
* talk_to_blkback sets state to XenbusStateInitialised
|
||||
* and blkfront_connect sets it to XenbusStateConnected
|
||||
* (if connection went OK).
|
||||
*
|
||||
* If the backend (or toolstack) decides to poke at backend
|
||||
* state (and re-trigger the watch by setting the state repeatedly
|
||||
* to XenbusStateConnected (4)) we need to deal with this.
|
||||
* This is allowed as this is used to communicate to the guest
|
||||
* that the size of disk has changed!
|
||||
*/
|
||||
if ((dev->state != XenbusStateInitialised) &&
|
||||
(dev->state != XenbusStateConnected)) {
|
||||
if (talk_to_blkback(dev, info))
|
||||
break;
|
||||
}
|
||||
|
||||
blkfront_connect(info);
|
||||
break;
|
||||
|
||||
|
|
|
@ -3820,6 +3820,7 @@ static void handle_new_recv_msgs(ipmi_smi_t intf)
|
|||
while (!list_empty(&intf->waiting_rcv_msgs)) {
|
||||
smi_msg = list_entry(intf->waiting_rcv_msgs.next,
|
||||
struct ipmi_smi_msg, link);
|
||||
list_del(&smi_msg->link);
|
||||
if (!run_to_completion)
|
||||
spin_unlock_irqrestore(&intf->waiting_rcv_msgs_lock,
|
||||
flags);
|
||||
|
@ -3829,11 +3830,14 @@ static void handle_new_recv_msgs(ipmi_smi_t intf)
|
|||
if (rv > 0) {
|
||||
/*
|
||||
* To preserve message order, quit if we
|
||||
* can't handle a message.
|
||||
* can't handle a message. Add the message
|
||||
* back at the head, this is safe because this
|
||||
* tasklet is the only thing that pulls the
|
||||
* messages.
|
||||
*/
|
||||
list_add(&smi_msg->link, &intf->waiting_rcv_msgs);
|
||||
break;
|
||||
} else {
|
||||
list_del(&smi_msg->link);
|
||||
if (rv == 0)
|
||||
/* Message handled */
|
||||
ipmi_free_smi_msg(smi_msg);
|
||||
|
|
|
@ -372,26 +372,9 @@ static bool intel_pstate_get_ppc_enable_status(void)
|
|||
return acpi_ppc;
|
||||
}
|
||||
|
||||
/*
|
||||
* The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and
|
||||
* in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and
|
||||
* max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state
|
||||
* ratio, out of it only high 8 bits are used. For example 0x1700 is setting
|
||||
* target ratio 0x17. The _PSS control value stores in a format which can be
|
||||
* directly written to PERF_CTL MSR. But in intel_pstate driver this shift
|
||||
* occurs during write to PERF_CTL (E.g. for cores core_set_pstate()).
|
||||
* This function converts the _PSS control value to intel pstate driver format
|
||||
* for comparison and assignment.
|
||||
*/
|
||||
static int convert_to_native_pstate_format(struct cpudata *cpu, int index)
|
||||
{
|
||||
return cpu->acpi_perf_data.states[index].control >> 8;
|
||||
}
|
||||
|
||||
static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
|
||||
{
|
||||
struct cpudata *cpu;
|
||||
int turbo_pss_ctl;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
|
@ -441,11 +424,10 @@ static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
|
|||
* max frequency, which will cause a reduced performance as
|
||||
* this driver uses real max turbo frequency as the max
|
||||
* frequency. So correct this frequency in _PSS table to
|
||||
* correct max turbo frequency based on the turbo ratio.
|
||||
* correct max turbo frequency based on the turbo state.
|
||||
* Also need to convert to MHz as _PSS freq is in MHz.
|
||||
*/
|
||||
turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0);
|
||||
if (turbo_pss_ctl > cpu->pstate.max_pstate)
|
||||
if (!limits->turbo_disabled)
|
||||
cpu->acpi_perf_data.states[0].core_frequency =
|
||||
policy->cpuinfo.max_freq / 1000;
|
||||
cpu->valid_pss_table = true;
|
||||
|
|
|
@ -242,7 +242,7 @@ struct at_xdmac_lld {
|
|||
u32 mbr_dus; /* Destination Microblock Stride Register */
|
||||
};
|
||||
|
||||
|
||||
/* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */
|
||||
struct at_xdmac_desc {
|
||||
struct at_xdmac_lld lld;
|
||||
enum dma_transfer_direction direction;
|
||||
|
@ -253,7 +253,7 @@ struct at_xdmac_desc {
|
|||
unsigned int xfer_size;
|
||||
struct list_head descs_list;
|
||||
struct list_head xfer_node;
|
||||
};
|
||||
} __aligned(sizeof(u64));
|
||||
|
||||
static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
|
||||
{
|
||||
|
@ -1400,6 +1400,7 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|||
u32 cur_nda, check_nda, cur_ubc, mask, value;
|
||||
u8 dwidth = 0;
|
||||
unsigned long flags;
|
||||
bool initd;
|
||||
|
||||
ret = dma_cookie_status(chan, cookie, txstate);
|
||||
if (ret == DMA_COMPLETE)
|
||||
|
@ -1424,7 +1425,16 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|||
residue = desc->xfer_size;
|
||||
/*
|
||||
* Flush FIFO: only relevant when the transfer is source peripheral
|
||||
* synchronized.
|
||||
* synchronized. Flush is needed before reading CUBC because data in
|
||||
* the FIFO are not reported by CUBC. Reporting a residue of the
|
||||
* transfer length while we have data in FIFO can cause issue.
|
||||
* Usecase: atmel USART has a timeout which means I have received
|
||||
* characters but there is no more character received for a while. On
|
||||
* timeout, it requests the residue. If the data are in the DMA FIFO,
|
||||
* we will return a residue of the transfer length. It means no data
|
||||
* received. If an application is waiting for these data, it will hang
|
||||
* since we won't have another USART timeout without receiving new
|
||||
* data.
|
||||
*/
|
||||
mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
|
||||
value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
|
||||
|
@ -1435,34 +1445,43 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|||
}
|
||||
|
||||
/*
|
||||
* When processing the residue, we need to read two registers but we
|
||||
* can't do it in an atomic way. AT_XDMAC_CNDA is used to find where
|
||||
* we stand in the descriptor list and AT_XDMAC_CUBC is used
|
||||
* to know how many data are remaining for the current descriptor.
|
||||
* Since the dma channel is not paused to not loose data, between the
|
||||
* AT_XDMAC_CNDA and AT_XDMAC_CUBC read, we may have change of
|
||||
* descriptor.
|
||||
* For that reason, after reading AT_XDMAC_CUBC, we check if we are
|
||||
* still using the same descriptor by reading a second time
|
||||
* AT_XDMAC_CNDA. If AT_XDMAC_CNDA has changed, it means we have to
|
||||
* read again AT_XDMAC_CUBC.
|
||||
* The easiest way to compute the residue should be to pause the DMA
|
||||
* but doing this can lead to miss some data as some devices don't
|
||||
* have FIFO.
|
||||
* We need to read several registers because:
|
||||
* - DMA is running therefore a descriptor change is possible while
|
||||
* reading these registers
|
||||
* - When the block transfer is done, the value of the CUBC register
|
||||
* is set to its initial value until the fetch of the next descriptor.
|
||||
* This value will corrupt the residue calculation so we have to skip
|
||||
* it.
|
||||
*
|
||||
* INITD -------- ------------
|
||||
* |____________________|
|
||||
* _______________________ _______________
|
||||
* NDA @desc2 \/ @desc3
|
||||
* _______________________/\_______________
|
||||
* __________ ___________ _______________
|
||||
* CUBC 0 \/ MAX desc1 \/ MAX desc2
|
||||
* __________/\___________/\_______________
|
||||
*
|
||||
* Since descriptors are aligned on 64 bits, we can assume that
|
||||
* the update of NDA and CUBC is atomic.
|
||||
* Memory barriers are used to ensure the read order of the registers.
|
||||
* A max number of retries is set because unlikely it can never ends if
|
||||
* we are transferring a lot of data with small buffers.
|
||||
* A max number of retries is set because unlikely it could never ends.
|
||||
*/
|
||||
cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
|
||||
rmb();
|
||||
cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
|
||||
for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
|
||||
rmb();
|
||||
check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
|
||||
|
||||
if (likely(cur_nda == check_nda))
|
||||
break;
|
||||
|
||||
cur_nda = check_nda;
|
||||
rmb();
|
||||
initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
|
||||
rmb();
|
||||
cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
|
||||
rmb();
|
||||
cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
|
||||
rmb();
|
||||
|
||||
if ((check_nda == cur_nda) && initd)
|
||||
break;
|
||||
}
|
||||
|
||||
if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) {
|
||||
|
@ -1470,6 +1489,19 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|||
goto spin_unlock;
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush FIFO: only relevant when the transfer is source peripheral
|
||||
* synchronized. Another flush is needed here because CUBC is updated
|
||||
* when the controller sends the data write command. It can lead to
|
||||
* report data that are not written in the memory or the device. The
|
||||
* FIFO flush ensures that data are really written.
|
||||
*/
|
||||
if ((desc->lld.mbr_cfg & mask) == value) {
|
||||
at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
|
||||
while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove size of all microblocks already transferred and the current
|
||||
* one. Then add the remaining size to transfer of the current
|
||||
|
|
|
@ -703,8 +703,9 @@ static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
|
|||
goto free_resources;
|
||||
}
|
||||
|
||||
src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
|
||||
PAGE_SIZE, DMA_TO_DEVICE);
|
||||
src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src),
|
||||
(size_t)src & ~PAGE_MASK, PAGE_SIZE,
|
||||
DMA_TO_DEVICE);
|
||||
unmap->addr[0] = src_dma;
|
||||
|
||||
ret = dma_mapping_error(dma_chan->device->dev, src_dma);
|
||||
|
@ -714,8 +715,9 @@ static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
|
|||
}
|
||||
unmap->to_cnt = 1;
|
||||
|
||||
dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
|
||||
PAGE_SIZE, DMA_FROM_DEVICE);
|
||||
dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest),
|
||||
(size_t)dest & ~PAGE_MASK, PAGE_SIZE,
|
||||
DMA_FROM_DEVICE);
|
||||
unmap->addr[1] = dest_dma;
|
||||
|
||||
ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
|
||||
|
|
|
@ -360,6 +360,8 @@ static int palmas_usb_probe(struct platform_device *pdev)
|
|||
|
||||
palmas_enable_irq(palmas_usb);
|
||||
/* perform initial detection */
|
||||
if (palmas_usb->enable_gpio_vbus_detection)
|
||||
palmas_vbus_irq_handler(palmas_usb->gpio_vbus_irq, palmas_usb);
|
||||
palmas_gpio_id_detect(&palmas_usb->wq_detectid.work);
|
||||
device_set_wakeup_capable(&pdev->dev, true);
|
||||
return 0;
|
||||
|
|
|
@ -33,6 +33,7 @@ config ARCH_REQUIRE_GPIOLIB
|
|||
|
||||
menuconfig GPIOLIB
|
||||
bool "GPIO Support"
|
||||
select ANON_INODES
|
||||
help
|
||||
This enables GPIO support through the generic GPIO library.
|
||||
You only need to enable this, if you also want to enable
|
||||
|
@ -530,7 +531,7 @@ menu "Port-mapped I/O GPIO drivers"
|
|||
|
||||
config GPIO_104_DIO_48E
|
||||
tristate "ACCES 104-DIO-48E GPIO support"
|
||||
depends on ISA
|
||||
depends on ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the ACCES 104-DIO-48E series (104-DIO-48E,
|
||||
|
@ -540,7 +541,7 @@ config GPIO_104_DIO_48E
|
|||
|
||||
config GPIO_104_IDIO_16
|
||||
tristate "ACCES 104-IDIO-16 GPIO support"
|
||||
depends on ISA
|
||||
depends on ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the ACCES 104-IDIO-16 family (104-IDIO-16,
|
||||
|
@ -551,7 +552,7 @@ config GPIO_104_IDIO_16
|
|||
|
||||
config GPIO_104_IDI_48
|
||||
tristate "ACCES 104-IDI-48 GPIO support"
|
||||
depends on ISA
|
||||
depends on ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the ACCES 104-IDI-48 family (104-IDI-48A,
|
||||
|
@ -627,7 +628,7 @@ config GPIO_TS5500
|
|||
|
||||
config GPIO_WS16C48
|
||||
tristate "WinSystems WS16C48 GPIO support"
|
||||
depends on ISA
|
||||
depends on ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the WinSystems WS16C48. The base port
|
||||
|
|
|
@ -75,7 +75,7 @@ static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|||
{
|
||||
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
|
||||
const unsigned io_port = offset / 8;
|
||||
const unsigned control_port = io_port / 2;
|
||||
const unsigned int control_port = io_port / 3;
|
||||
const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
|
||||
unsigned long flags;
|
||||
unsigned control;
|
||||
|
@ -115,7 +115,7 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
|||
{
|
||||
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
|
||||
const unsigned io_port = offset / 8;
|
||||
const unsigned control_port = io_port / 2;
|
||||
const unsigned int control_port = io_port / 3;
|
||||
const unsigned mask = BIT(offset % 8);
|
||||
const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
|
||||
const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
|
||||
|
|
|
@ -547,11 +547,11 @@ static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
|
|||
/* disable interrupts and clear status */
|
||||
for (i = 0; i < kona_gpio->num_bank; i++) {
|
||||
/* Unlock the entire bank first */
|
||||
bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
|
||||
bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
|
||||
writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
|
||||
writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
|
||||
/* Now re-lock the bank */
|
||||
bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
|
||||
bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -709,7 +709,13 @@ static int zynq_gpio_probe(struct platform_device *pdev)
|
|||
dev_err(&pdev->dev, "input clock not found.\n");
|
||||
return PTR_ERR(gpio->clk);
|
||||
}
|
||||
ret = clk_prepare_enable(gpio->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to enable clock.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
if (ret < 0)
|
||||
|
@ -747,6 +753,7 @@ err_pm_put:
|
|||
pm_runtime_put(&pdev->dev);
|
||||
err_pm_dis:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_disable_unprepare(gpio->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/io-mapping.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
|
@ -449,7 +449,6 @@ static void gpiodevice_release(struct device *dev)
|
|||
{
|
||||
struct gpio_device *gdev = dev_get_drvdata(dev);
|
||||
|
||||
cdev_del(&gdev->chrdev);
|
||||
list_del(&gdev->list);
|
||||
ida_simple_remove(&gpio_ida, gdev->id);
|
||||
kfree(gdev->label);
|
||||
|
@ -482,7 +481,6 @@ static int gpiochip_setup_dev(struct gpio_device *gdev)
|
|||
|
||||
/* From this point, the .release() function cleans up gpio_device */
|
||||
gdev->dev.release = gpiodevice_release;
|
||||
get_device(&gdev->dev);
|
||||
pr_debug("%s: registered GPIOs %d to %d on device: %s (%s)\n",
|
||||
__func__, gdev->base, gdev->base + gdev->ngpio - 1,
|
||||
dev_name(&gdev->dev), gdev->chip->label ? : "generic");
|
||||
|
@ -770,6 +768,8 @@ void gpiochip_remove(struct gpio_chip *chip)
|
|||
* be removed, else it will be dangling until the last user is
|
||||
* gone.
|
||||
*/
|
||||
cdev_del(&gdev->chrdev);
|
||||
device_del(&gdev->dev);
|
||||
put_device(&gdev->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gpiochip_remove);
|
||||
|
@ -869,7 +869,7 @@ struct gpio_chip *gpiochip_find(void *data,
|
|||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
list_for_each_entry(gdev, &gpio_devices, list)
|
||||
if (match(gdev->chip, data))
|
||||
if (gdev->chip && match(gdev->chip, data))
|
||||
break;
|
||||
|
||||
/* No match? */
|
||||
|
|
|
@ -799,7 +799,6 @@ struct amdgpu_ring {
|
|||
unsigned cond_exe_offs;
|
||||
u64 cond_exe_gpu_addr;
|
||||
volatile u32 *cond_exe_cpu_addr;
|
||||
int vmid;
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -937,8 +936,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned vm_id, uint64_t pd_addr,
|
||||
uint32_t gds_base, uint32_t gds_size,
|
||||
uint32_t gws_base, uint32_t gws_size,
|
||||
uint32_t oa_base, uint32_t oa_size,
|
||||
bool vmid_switch);
|
||||
uint32_t oa_base, uint32_t oa_size);
|
||||
void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
|
||||
uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
|
||||
int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
|
||||
|
@ -1822,6 +1820,8 @@ struct amdgpu_asic_funcs {
|
|||
/* MM block clocks */
|
||||
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
|
||||
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
|
||||
/* query virtual capabilities */
|
||||
u32 (*get_virtual_caps)(struct amdgpu_device *adev);
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -1916,8 +1916,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
|
|||
|
||||
|
||||
/* GPU virtualization */
|
||||
#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
|
||||
#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
|
||||
struct amdgpu_virtualization {
|
||||
bool supports_sr_iov;
|
||||
bool is_virtual;
|
||||
u32 caps;
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -2206,6 +2210,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
|
|||
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
|
||||
#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
|
||||
#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
|
||||
#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
|
||||
#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
|
||||
#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
|
||||
#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
|
||||
|
|
|
@ -1385,6 +1385,15 @@ static int amdgpu_resume(struct amdgpu_device *adev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool amdgpu_device_is_virtual(void)
|
||||
{
|
||||
#ifdef CONFIG_X86
|
||||
return boot_cpu_has(X86_FEATURE_HYPERVISOR);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_device_init - initialize the driver
|
||||
*
|
||||
|
@ -1519,8 +1528,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
|
|||
adev->virtualization.supports_sr_iov =
|
||||
amdgpu_atombios_has_gpu_virtualization_table(adev);
|
||||
|
||||
/* Check if we are executing in a virtualized environment */
|
||||
adev->virtualization.is_virtual = amdgpu_device_is_virtual();
|
||||
adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
|
||||
|
||||
/* Post card if necessary */
|
||||
if (!amdgpu_card_posted(adev)) {
|
||||
if (!amdgpu_card_posted(adev) ||
|
||||
(adev->virtualization.is_virtual &&
|
||||
!adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) {
|
||||
if (!adev->bios) {
|
||||
dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
|
||||
return -EINVAL;
|
||||
|
|
|
@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|||
bool skip_preamble, need_ctx_switch;
|
||||
unsigned patch_offset = ~0;
|
||||
struct amdgpu_vm *vm;
|
||||
int vmid = 0, old_vmid = ring->vmid;
|
||||
struct fence *hwf;
|
||||
uint64_t ctx;
|
||||
|
||||
|
@ -136,11 +135,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|||
if (job) {
|
||||
vm = job->vm;
|
||||
ctx = job->ctx;
|
||||
vmid = job->vm_id;
|
||||
} else {
|
||||
vm = NULL;
|
||||
ctx = 0;
|
||||
vmid = 0;
|
||||
}
|
||||
|
||||
if (!ring->ready) {
|
||||
|
@ -166,8 +163,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|||
r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,
|
||||
job->gds_base, job->gds_size,
|
||||
job->gws_base, job->gws_size,
|
||||
job->oa_base, job->oa_size,
|
||||
(ring->current_ctx == ctx) && (old_vmid != vmid));
|
||||
job->oa_base, job->oa_size);
|
||||
if (r) {
|
||||
amdgpu_ring_undo(ring);
|
||||
return r;
|
||||
|
@ -184,6 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|||
need_ctx_switch = ring->current_ctx != ctx;
|
||||
for (i = 0; i < num_ibs; ++i) {
|
||||
ib = &ibs[i];
|
||||
|
||||
/* drop preamble IBs if we don't have a context switch */
|
||||
if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
|
||||
continue;
|
||||
|
@ -191,7 +188,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|||
amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
|
||||
need_ctx_switch);
|
||||
need_ctx_switch = false;
|
||||
ring->vmid = vmid;
|
||||
}
|
||||
|
||||
if (ring->funcs->emit_hdp_invalidate)
|
||||
|
@ -202,7 +198,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|||
dev_err(adev->dev, "failed to emit fence (%d)\n", r);
|
||||
if (job && job->vm_id)
|
||||
amdgpu_vm_reset_id(adev, job->vm_id);
|
||||
ring->vmid = old_vmid;
|
||||
amdgpu_ring_undo(ring);
|
||||
return r;
|
||||
}
|
||||
|
|
|
@ -298,8 +298,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned vm_id, uint64_t pd_addr,
|
||||
uint32_t gds_base, uint32_t gds_size,
|
||||
uint32_t gws_base, uint32_t gws_size,
|
||||
uint32_t oa_base, uint32_t oa_size,
|
||||
bool vmid_switch)
|
||||
uint32_t oa_base, uint32_t oa_size)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
|
||||
|
@ -313,7 +312,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
|
|||
int r;
|
||||
|
||||
if (ring->funcs->emit_pipeline_sync && (
|
||||
pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || vmid_switch))
|
||||
pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
|
||||
ring->type == AMDGPU_RING_TYPE_COMPUTE))
|
||||
amdgpu_ring_emit_pipeline_sync(ring);
|
||||
|
||||
if (ring->funcs->emit_vm_flush &&
|
||||
|
|
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Reference in New Issue