pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
Currently the PINMUX_DATA_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Geert Uytterhoeven
parent
69f7be1c63
commit
19b593a1cf
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@ -2464,7 +2464,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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static const struct pinmux_data_reg pinmux_data_regs[] = {
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{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
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{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
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0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
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PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
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PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
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@ -2473,9 +2473,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
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PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
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PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
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{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -2484,9 +2484,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, 0, PORT40_DATA,
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PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
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PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
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{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, PORT85_DATA, PORT84_DATA,
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@ -2495,9 +2495,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
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PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
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PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
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{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
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0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
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PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
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PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
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@ -2506,9 +2506,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
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PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
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PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
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{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -2517,9 +2517,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, 0, 0,
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0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
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PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
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{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -2528,9 +2528,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
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PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
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PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
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{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
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0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
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PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
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PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
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@ -2539,9 +2539,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
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PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
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PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
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{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
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0, 0, 0, 0,
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0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
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PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
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@ -2550,9 +2550,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
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PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
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PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
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{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
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0, 0, 0, 0,
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PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
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PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
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@ -2561,9 +2561,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
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PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
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PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
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{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, PORT308_DATA,
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@ -2572,9 +2572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
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PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
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PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
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}
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))
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},
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{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
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{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -2583,7 +2583,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, PORT329_DATA, PORT328_DATA,
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PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
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PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
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}
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))
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},
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{ },
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};
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@ -3534,7 +3534,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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};
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static const struct pinmux_data_reg pinmux_data_regs[] = {
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{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
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{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
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PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
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PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
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PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
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@ -3542,9 +3542,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
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PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
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PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
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PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
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PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
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},
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{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
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{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
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PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
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PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
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PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
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@ -3552,9 +3552,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
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PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
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PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
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PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
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PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
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},
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{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
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{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -3562,9 +3562,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
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PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
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PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
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PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
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PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
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},
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{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
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{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
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PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
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PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
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PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
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@ -3572,9 +3572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0 }
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0, 0, 0, 0 ))
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},
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{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
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{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -3582,9 +3582,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
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PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
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PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
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PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
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PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
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},
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{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
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{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
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PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
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PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
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PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
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@ -3592,9 +3592,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0 }
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0, 0, 0, 0 ))
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},
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{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
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{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
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PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
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PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
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PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
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@ -3602,9 +3602,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
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PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
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PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
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PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
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PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
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},
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{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
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{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
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PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
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PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
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PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
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@ -3612,9 +3612,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
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PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
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PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
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PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
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PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
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},
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{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
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{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -3622,9 +3622,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
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PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
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PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
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PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
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PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
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},
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{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
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{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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@ -3632,7 +3632,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0 }
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0, 0, 0, 0 ))
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},
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{ },
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};
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@ -1525,47 +1525,47 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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};
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static const struct pinmux_data_reg pinmux_data_regs[] = {
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{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
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{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
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PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
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PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
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},
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{ PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) {
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{ PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16, GROUP(
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0, 0, 0, PB12_DATA,
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PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
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PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
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PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
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PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
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},
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{ PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) {
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{ PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16, GROUP(
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0, PC14_DATA, PC13_DATA, PC12_DATA,
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PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
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PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
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PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
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PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
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},
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{ PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) {
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{ PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16, GROUP(
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PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
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PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
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PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
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PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
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PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
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},
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{ PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) {
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{ PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16, GROUP(
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PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
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PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
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PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
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PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
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PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
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},
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{ PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) {
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{ PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16, GROUP(
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0, PF30_DATA, PF29_DATA, PF28_DATA,
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PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
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PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
|
||||
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
|
||||
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) {
|
||||
{ PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16, GROUP(
|
||||
PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
|
||||
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2037,79 +2037,79 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
|
||||
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, PA3_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, PA2_DATA }
|
||||
0, 0, 0, 0, 0, 0, 0, PA2_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
|
||||
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
|
||||
0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
|
||||
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, PB22_DATA, PB21_DATA, PB20_DATA,
|
||||
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
|
||||
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
|
||||
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
|
||||
PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
|
||||
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, 0 }
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
|
||||
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, PC10_DATA, PC9_DATA, PC8_DATA,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
|
||||
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
|
||||
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
|
||||
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
|
||||
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, PE5_DATA, PE4_DATA,
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
|
||||
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
|
||||
0, 0, 0, PF12_DATA,
|
||||
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
|
||||
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, PG24_DATA,
|
||||
PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
|
||||
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
|
||||
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
|
||||
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
|
||||
PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
|
||||
PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
|
||||
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
|
||||
0, 0, 0, PJ12_DATA,
|
||||
PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) {
|
||||
{ PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16, GROUP(
|
||||
0, 0, 0, PK12_DATA,
|
||||
PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
|
||||
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
|
||||
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
|
||||
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2735,79 +2735,79 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
|
||||
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
|
||||
0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
|
||||
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, PB22_DATA, PB21_DATA, PB20_DATA,
|
||||
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
|
||||
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
|
||||
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
|
||||
PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
|
||||
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, 0 }
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
|
||||
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, PC8_DATA,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
|
||||
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
|
||||
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
|
||||
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
|
||||
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16) {
|
||||
{ PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
|
||||
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
|
||||
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
|
||||
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
|
||||
PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
|
||||
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
|
||||
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
|
||||
0, 0, 0, 0,
|
||||
PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
|
||||
PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
|
||||
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
|
||||
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
|
||||
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
|
||||
PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
|
||||
PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
|
||||
},
|
||||
|
||||
{ PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16) {
|
||||
{ PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16, GROUP(
|
||||
PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
|
||||
PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
|
||||
PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
|
||||
PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA }
|
||||
PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
|
||||
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
|
||||
PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
|
||||
PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
|
||||
},
|
||||
|
||||
{ }
|
||||
|
|
|
|||
|
|
@ -4080,7 +4080,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
|
||||
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
|
||||
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
|
||||
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
|
||||
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
|
||||
|
|
@ -4088,9 +4088,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
|
||||
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
|
||||
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
|
||||
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
|
||||
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
|
||||
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
|
||||
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
|
||||
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
|
||||
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
|
||||
|
|
@ -4098,9 +4098,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
|
||||
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
|
||||
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
|
||||
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
|
||||
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
|
||||
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
|
||||
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
|
||||
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
|
||||
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
|
||||
|
|
@ -4108,9 +4108,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
|
||||
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
|
||||
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
|
||||
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
|
||||
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
|
||||
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
|
||||
|
|
@ -4118,9 +4118,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
|
||||
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
|
||||
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
|
||||
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
|
||||
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
|
||||
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
|
||||
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
|
||||
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
|
||||
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
|
||||
|
|
@ -4128,9 +4128,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
|
||||
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
|
||||
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
|
||||
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
|
||||
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
|
||||
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
|
@ -4138,9 +4138,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, PORT164_DATA,
|
||||
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
|
||||
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
|
||||
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
|
||||
PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
|
||||
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
|
||||
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
|
||||
|
|
@ -4148,9 +4148,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
|
||||
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
|
||||
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
|
||||
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
|
||||
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
|
||||
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
|
||||
PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
|
||||
PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
|
||||
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
|
||||
|
|
@ -4158,9 +4158,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
|
||||
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
|
||||
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
|
||||
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
|
||||
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
|
||||
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
|
||||
PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
|
||||
|
|
@ -4168,9 +4168,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
|
||||
PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
|
||||
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
|
||||
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
|
||||
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
|
||||
{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, PORT309_DATA, PORT308_DATA,
|
||||
|
|
@ -4178,7 +4178,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
|
||||
PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
|
||||
PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
|
||||
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
|
||||
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1109,77 +1109,77 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050140, 8, GROUP(
|
||||
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050142, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050142, 8, GROUP(
|
||||
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050144, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050144, 8, GROUP(
|
||||
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
|
||||
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050148, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050148, 8, GROUP(
|
||||
0, PTE6_DATA, PTE5_DATA, PTE4_DATA,
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405014a, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405014a, 8, GROUP(
|
||||
0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405014c, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405014c, 8, GROUP(
|
||||
0, PTG6_DATA, PTG5_DATA, PTG4_DATA,
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405014e, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405014e, 8, GROUP(
|
||||
0, PTH6_DATA, PTH5_DATA, PTH4_DATA,
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050150, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050150, 8, GROUP(
|
||||
0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050152, 8) {
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050152, 8, GROUP(
|
||||
0, 0, 0, 0,
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050154, 8) {
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050154, 8, GROUP(
|
||||
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
|
||||
PTL3_DATA, 0, 0, 0 }
|
||||
PTL3_DATA, 0, 0, 0 ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050156, 8) {
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050156, 8, GROUP(
|
||||
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PPDR", 0xa4050158, 8) {
|
||||
{ PINMUX_DATA_REG("PPDR", 0xa4050158, 8, GROUP(
|
||||
0, 0, 0, PTP4_DATA,
|
||||
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
|
||||
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405015a, 8) {
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405015a, 8, GROUP(
|
||||
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405015c, 8) {
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405015c, 8, GROUP(
|
||||
0, 0, 0, PTS4_DATA,
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa405015e, 8) {
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa405015e, 8, GROUP(
|
||||
0, 0, 0, PTT4_DATA,
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050160, 8) {
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050160, 8, GROUP(
|
||||
0, 0, 0, PTU4_DATA,
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050162, 8) {
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050162, 8, GROUP(
|
||||
0, 0, 0, PTV4_DATA,
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1633,97 +1633,97 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
|
||||
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
|
||||
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
|
||||
PTC7_DATA, 0, PTC5_DATA, PTC4_DATA,
|
||||
PTC3_DATA, PTC2_DATA, 0, PTC0_DATA }
|
||||
PTC3_DATA, PTC2_DATA, 0, PTC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
|
||||
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
|
||||
PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
|
||||
0, 0, PTE1_DATA, PTE0_DATA }
|
||||
0, 0, PTE1_DATA, PTE0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
|
||||
0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
|
||||
0, 0, 0, PTG4_DATA,
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
|
||||
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
|
||||
PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
|
||||
0, 0, PTJ1_DATA, PTJ0_DATA }
|
||||
0, 0, PTJ1_DATA, PTJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
|
||||
0, PTK6_DATA, PTK5_DATA, PTK4_DATA,
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
|
||||
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
|
||||
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
|
||||
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
|
||||
PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
|
||||
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
|
||||
0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
|
||||
0, 0, 0, PTR4_DATA,
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
|
||||
0, 0, 0, PTS4_DATA,
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
|
||||
0, 0, 0, PTT4_DATA,
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
|
||||
0, 0, 0, PTU4_DATA,
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
|
||||
0, 0, 0, PTV4_DATA,
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
|
||||
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
|
||||
0, PTW6_DATA, PTW5_DATA, PTW4_DATA,
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
|
||||
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
|
||||
0, PTX6_DATA, PTX5_DATA, PTX4_DATA,
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
|
||||
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
|
||||
0, PTY6_DATA, PTY5_DATA, PTY4_DATA,
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
|
||||
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
|
||||
0, 0, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1781,97 +1781,97 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
|
||||
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
|
||||
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
|
||||
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
|
||||
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
|
||||
0, 0, PTE5_DATA, PTE4_DATA,
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
|
||||
PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
|
||||
0, 0, PTG5_DATA, PTG4_DATA,
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
|
||||
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
|
||||
PTJ7_DATA, 0, PTJ5_DATA, 0,
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
|
||||
PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
|
||||
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
|
||||
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
|
||||
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
|
||||
PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
|
||||
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
|
||||
0, 0, 0, 0,
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
|
||||
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
|
||||
PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
|
||||
0, 0, PTT5_DATA, PTT4_DATA,
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
|
||||
0, 0, PTU5_DATA, PTU4_DATA,
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
|
||||
PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
|
||||
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
|
||||
PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
|
||||
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
|
||||
PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
|
||||
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
|
||||
PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
|
||||
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
|
||||
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2063,97 +2063,97 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
|
||||
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
|
||||
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
|
||||
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
|
||||
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
|
||||
PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
|
||||
PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
|
||||
0, 0, PTG5_DATA, PTG4_DATA,
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
|
||||
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
|
||||
PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
|
||||
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
|
||||
PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
|
||||
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
|
||||
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
|
||||
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
|
||||
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
|
||||
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
|
||||
PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
|
||||
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
|
||||
PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
|
||||
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
|
||||
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
|
||||
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
|
||||
0, PTS6_DATA, PTS5_DATA, PTS4_DATA,
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
|
||||
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
|
||||
PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
|
||||
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
|
||||
PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
|
||||
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
|
||||
PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
|
||||
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
|
||||
PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
|
||||
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
|
||||
PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
|
||||
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
|
||||
PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
|
||||
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
|
||||
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2425,17 +2425,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
/* GPIO 0 - 5*/
|
||||
{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
|
||||
{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
|
||||
{ PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } },
|
||||
{ PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } },
|
||||
{ PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } },
|
||||
{ PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) {
|
||||
{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
|
||||
{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
|
||||
{ PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
|
||||
{ PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
|
||||
{ PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
|
||||
{ PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
|
||||
GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
|
||||
GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
|
||||
GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2113,109 +2113,109 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffec0034, 8, GROUP(
|
||||
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
|
||||
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffec0036, 8, GROUP(
|
||||
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
|
||||
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffec0038, 8, GROUP(
|
||||
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
|
||||
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffec003a, 8, GROUP(
|
||||
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
|
||||
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffec003c, 8, GROUP(
|
||||
PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
|
||||
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffec003e, 8, GROUP(
|
||||
PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
|
||||
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffec0040, 8, GROUP(
|
||||
PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
|
||||
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffec0042, 8, GROUP(
|
||||
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
|
||||
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
|
||||
{ PINMUX_DATA_REG("PIDR", 0xffec0044, 8, GROUP(
|
||||
PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
|
||||
PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
|
||||
PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffec0046, 8, GROUP(
|
||||
0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
|
||||
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
|
||||
{ PINMUX_DATA_REG("PKDR", 0xffec0048, 8, GROUP(
|
||||
PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
|
||||
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
|
||||
{ PINMUX_DATA_REG("PLDR", 0xffec004a, 8, GROUP(
|
||||
0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
|
||||
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
|
||||
{ PINMUX_DATA_REG("PMDR", 0xffec004c, 8, GROUP(
|
||||
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
|
||||
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
|
||||
{ PINMUX_DATA_REG("PNDR", 0xffec004e, 8, GROUP(
|
||||
0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
|
||||
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
|
||||
{ PINMUX_DATA_REG("PODR", 0xffec0050, 8, GROUP(
|
||||
PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
|
||||
PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
|
||||
PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
|
||||
{ PINMUX_DATA_REG("PPDR", 0xffec0052, 8, GROUP(
|
||||
PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
|
||||
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
|
||||
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
|
||||
{ PINMUX_DATA_REG("PQDR", 0xffec0054, 8, GROUP(
|
||||
0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
|
||||
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
|
||||
{ PINMUX_DATA_REG("PRDR", 0xffec0056, 8, GROUP(
|
||||
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
|
||||
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
|
||||
{ PINMUX_DATA_REG("PSDR", 0xffec0058, 8, GROUP(
|
||||
PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
|
||||
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
|
||||
{ PINMUX_DATA_REG("PTDR", 0xffec005a, 8, GROUP(
|
||||
PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
|
||||
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
|
||||
{ PINMUX_DATA_REG("PUDR", 0xffec005c, 8, GROUP(
|
||||
PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
|
||||
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
|
||||
{ PINMUX_DATA_REG("PVDR", 0xffec005e, 8, GROUP(
|
||||
PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
|
||||
{ PINMUX_DATA_REG("PWDR", 0xffec0060, 8, GROUP(
|
||||
PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
|
||||
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
|
||||
{ PINMUX_DATA_REG("PXDR", 0xffec0062, 8, GROUP(
|
||||
PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
|
||||
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
|
||||
{ PINMUX_DATA_REG("PYDR", 0xffec0064, 8, GROUP(
|
||||
PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
|
||||
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
|
||||
{ PINMUX_DATA_REG("PZDR", 0xffec0066, 8, GROUP(
|
||||
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1185,69 +1185,69 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffe70020, 8, GROUP(
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffe70022, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffe70022, 8, GROUP(
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffe70024, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffe70024, 8, GROUP(
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffe70026, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffe70026, 8, GROUP(
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffe70028, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffe70028, 8, GROUP(
|
||||
0, 0, PE5_DATA, PE4_DATA,
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffe7002a, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffe7002a, 8, GROUP(
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffe7002c, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffe7002c, 8, GROUP(
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffe7002e, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffe7002e, 8, GROUP(
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffe70030, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffe70030, 8, GROUP(
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PKDR", 0xffe70032, 8) {
|
||||
{ PINMUX_DATA_REG("PKDR", 0xffe70032, 8, GROUP(
|
||||
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
|
||||
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
|
||||
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PLDR", 0xffe70034, 8) {
|
||||
{ PINMUX_DATA_REG("PLDR", 0xffe70034, 8, GROUP(
|
||||
PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
|
||||
PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA }
|
||||
PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PMDR", 0xffe70036, 8) {
|
||||
{ PINMUX_DATA_REG("PMDR", 0xffe70036, 8, GROUP(
|
||||
0, 0, 0, 0,
|
||||
0, 0, PM1_DATA, PM0_DATA }
|
||||
0, 0, PM1_DATA, PM0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PNDR", 0xffe70038, 8) {
|
||||
{ PINMUX_DATA_REG("PNDR", 0xffe70038, 8, GROUP(
|
||||
PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
|
||||
PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA }
|
||||
PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PPDR", 0xffe7003a, 8) {
|
||||
{ PINMUX_DATA_REG("PPDR", 0xffe7003a, 8, GROUP(
|
||||
0, 0, PP5_DATA, PP4_DATA,
|
||||
PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA }
|
||||
PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PQDR", 0xffe7003c, 8) {
|
||||
{ PINMUX_DATA_REG("PQDR", 0xffe7003c, 8, GROUP(
|
||||
0, 0, 0, PQ4_DATA,
|
||||
PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA }
|
||||
PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PRDR", 0xffe7003e, 8) {
|
||||
{ PINMUX_DATA_REG("PRDR", 0xffe7003e, 8, GROUP(
|
||||
0, 0, 0, 0,
|
||||
PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA }
|
||||
PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -757,41 +757,41 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
|
||||
PE7_DATA, PE6_DATA,
|
||||
0, 0, 0, 0, 0, 0 }
|
||||
0, 0, 0, 0, 0, 0 ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, 0,
|
||||
0, 0, 0, 0 }
|
||||
0, 0, 0, 0 ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -507,37 +507,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
|
||||
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
|
||||
{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
|
||||
{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
|
||||
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, ))
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
|
||||
{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
|
||||
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -192,12 +192,12 @@ struct pinmux_data_reg {
|
|||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* This macro must be followed by initialization data: For each register bit
|
||||
* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
|
||||
* - ids: For each register bit (from left to right, i.e. MSB to LSB), one
|
||||
* enum ID must be specified, all wrapped using the GROUP() macro.
|
||||
*/
|
||||
#define PINMUX_DATA_REG(name, r, r_width) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.enum_ids = (const u16 [r_width]) \
|
||||
#define PINMUX_DATA_REG(name, r, r_width, ids) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.enum_ids = (const u16 [r_width]) { ids }
|
||||
|
||||
struct pinmux_irq {
|
||||
const short *gpios;
|
||||
|
|
|
|||
Loading…
Reference in New Issue