thunderbolt: Support 1st gen Light Ridge controller
Add support for the 1st gen Light Ridge controller, which is built into these systems: iMac12,1 2011 21.5" iMac12,2 2011 27" Macmini5,1 2011 i5 2.3 GHz Macmini5,2 2011 i5 2.5 GHz Macmini5,3 2011 i7 2.0 GHz MacBookPro8,1 2011 13" MacBookPro8,2 2011 15" MacBookPro8,3 2011 17" MacBookPro9,1 2012 15" MacBookPro9,2 2012 13" Light Ridge (CV82524) was the very first copper Thunderbolt controller, introduced 2010 alongside its fiber-optic cousin Light Peak (CVL2510). Consequently the chip suffers from some teething troubles: - MSI is broken for hotplug signaling on the downstream bridges: The chip just never sends an interrupt. It requests 32 MSIs for each of its six bridges and the pcieport driver only allocates one per bridge. However I've verified that even if 32 MSIs are allocated there's no interrupt on hotplug. The only option is thus to disable MSI, which is also what OS X does. Apparently all Thunderbolt chips up to revision 1 of Cactus Ridge 4C are plagued by this issue so quirk those as well. - The chip supports a maximum hop_count of 32, unlike its successors which support only 12. Fixup ring_interrupt_active() to cope with values >= 32. - Another peculiarity is that the chip supports a maximum of 13 ports whereas its successors support 12. However the additional port (#5) seems to be unusable as reading its TB_CFG_PORT config space results in TB_CFG_ERROR_INVALID_CONFIG_SPACE. Add a quirk to mark the port disabled on the root switch, assuming that's necessary on all Macs using this chip. Tested-by: Lukas Wunner <lukas@wunner.de> [MacBookPro9,1] Tested-by: William Brown <william@blackhats.net.au> [MacBookPro8,2] Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andreas Noever <andreas.noever@gmail.com>
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@ -3185,6 +3185,29 @@ static void quirk_no_pm_reset(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
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DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
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PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
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PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
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/*
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* Thunderbolt controllers with broken MSI hotplug signaling:
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* Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
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* of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
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*/
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static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
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{
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if (pdev->is_hotplug_bridge &&
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(pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
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pdev->revision <= 1))
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pdev->no_msi = 1;
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
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quirk_thunderbolt_hotplug_msi);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
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quirk_thunderbolt_hotplug_msi);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
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quirk_thunderbolt_hotplug_msi);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
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quirk_thunderbolt_hotplug_msi);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
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quirk_thunderbolt_hotplug_msi);
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_ACPI
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/*
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/*
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* Apple: Shutdown Cactus Ridge Thunderbolt controller.
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* Apple: Shutdown Cactus Ridge Thunderbolt controller.
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@ -3267,7 +3290,8 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
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if (!nhi)
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if (!nhi)
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goto out;
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goto out;
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if (nhi->vendor != PCI_VENDOR_ID_INTEL
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if (nhi->vendor != PCI_VENDOR_ID_INTEL
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|| (nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
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|| (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
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nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
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nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
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nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
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|| nhi->subsystem_vendor != 0x2222
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|| nhi->subsystem_vendor != 0x2222
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|| nhi->subsystem_device != 0x1111)
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|| nhi->subsystem_device != 0x1111)
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@ -3278,6 +3302,9 @@ out:
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pci_dev_put(nhi);
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pci_dev_put(nhi);
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pci_dev_put(sibling);
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pci_dev_put(sibling);
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}
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}
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DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
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quirk_apple_wait_for_thunderbolt);
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DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
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DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
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PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
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quirk_apple_wait_for_thunderbolt);
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quirk_apple_wait_for_thunderbolt);
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@ -388,6 +388,11 @@ int tb_drom_read(struct tb_switch *sw)
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sw->ports[4].link_nr = 1;
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sw->ports[4].link_nr = 1;
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sw->ports[3].dual_link_port = &sw->ports[4];
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sw->ports[3].dual_link_port = &sw->ports[4];
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sw->ports[4].dual_link_port = &sw->ports[3];
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sw->ports[4].dual_link_port = &sw->ports[3];
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/* Port 5 is inaccessible on this gen 1 controller */
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if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
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sw->ports[5].disabled = true;
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return 0;
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return 0;
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}
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}
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@ -37,7 +37,8 @@ static int ring_interrupt_index(struct tb_ring *ring)
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*/
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*/
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static void ring_interrupt_active(struct tb_ring *ring, bool active)
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static void ring_interrupt_active(struct tb_ring *ring, bool active)
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{
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{
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int reg = REG_RING_INTERRUPT_BASE + ring_interrupt_index(ring) / 32;
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int reg = REG_RING_INTERRUPT_BASE +
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ring_interrupt_index(ring) / 32 * 4;
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int bit = ring_interrupt_index(ring) & 31;
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int bit = ring_interrupt_index(ring) & 31;
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int mask = 1 << bit;
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int mask = 1 << bit;
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u32 old, new;
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u32 old, new;
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@ -564,7 +565,7 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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/* cannot fail - table is allocated bin pcim_iomap_regions */
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/* cannot fail - table is allocated bin pcim_iomap_regions */
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nhi->iobase = pcim_iomap_table(pdev)[0];
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nhi->iobase = pcim_iomap_table(pdev)[0];
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nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
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nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
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if (nhi->hop_count != 12)
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if (nhi->hop_count != 12 && nhi->hop_count != 32)
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dev_warn(&pdev->dev, "unexpected hop count: %d\n",
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dev_warn(&pdev->dev, "unexpected hop count: %d\n",
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nhi->hop_count);
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nhi->hop_count);
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INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
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INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
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@ -635,6 +636,12 @@ static struct pci_device_id nhi_ids[] = {
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* We have to specify class, the TB bridges use the same device and
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* We have to specify class, the TB bridges use the same device and
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* vendor (sub)id on gen 1 and gen 2 controllers.
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* vendor (sub)id on gen 1 and gen 2 controllers.
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*/
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*/
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{
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.class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
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.subvendor = 0x2222, .subdevice = 0x1111,
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},
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{
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{
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.class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
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.class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
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.vendor = PCI_VENDOR_ID_INTEL,
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.vendor = PCI_VENDOR_ID_INTEL,
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@ -370,7 +370,8 @@ struct tb_switch *tb_switch_alloc(struct tb *tb, u64 route)
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tb_sw_warn(sw, "unknown switch vendor id %#x\n",
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tb_sw_warn(sw, "unknown switch vendor id %#x\n",
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sw->config.vendor_id);
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sw->config.vendor_id);
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if (sw->config.device_id != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
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if (sw->config.device_id != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
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sw->config.device_id != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
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sw->config.device_id != PCI_DEVICE_ID_INTEL_PORT_RIDGE)
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sw->config.device_id != PCI_DEVICE_ID_INTEL_PORT_RIDGE)
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tb_sw_warn(sw, "unsupported switch device id %#x\n",
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tb_sw_warn(sw, "unsupported switch device id %#x\n",
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sw->config.device_id);
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sw->config.device_id);
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