ASoC: AMD: For capture have interrupts on I2S->ACP channel
Having interrupts enabled for ACP<->SYSMEM DMA transfer, we are in for an interrupt storm. For both playback and capture interrupts should be enabled for I2S<->ACP DMA. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -224,13 +224,11 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
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switch (asic_type) {
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switch (asic_type) {
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case CHIP_STONEY:
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case CHIP_STONEY:
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dmadscr[i].xfer_val |=
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dmadscr[i].xfer_val |=
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BIT(22) |
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(ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
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(ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
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(size / 2);
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(size / 2);
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break;
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break;
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default:
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default:
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dmadscr[i].xfer_val |=
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dmadscr[i].xfer_val |=
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BIT(22) |
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(ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
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(ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
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(size / 2);
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(size / 2);
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}
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}
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@ -421,9 +419,9 @@ static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num)
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switch (ch_num) {
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switch (ch_num) {
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case ACP_TO_I2S_DMA_CH_NUM:
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case ACP_TO_I2S_DMA_CH_NUM:
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case ACP_TO_SYSRAM_CH_NUM:
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case I2S_TO_ACP_DMA_CH_NUM:
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case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
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case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
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case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM:
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case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
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dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
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dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
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break;
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break;
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default:
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default:
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@ -705,18 +703,18 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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}
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if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
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if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
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valid_irq = true;
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valid_irq = true;
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snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
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snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
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acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
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acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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}
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if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) {
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if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
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valid_irq = true;
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valid_irq = true;
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snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
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snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
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acp_reg_write((intr_flag &
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acp_reg_write((intr_flag &
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BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16,
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BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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}
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