Add TI CDCE925 I2C controlled clock synthesizer driver
This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Mike Looijmans
Michael Turquette
parent
4d52b2acef
commit
19fbbbbcd3
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@ -0,0 +1,42 @@
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Binding for TO CDCE925 programmable I2C clock synthesizers.
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Reference
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] http://www.ti.com/product/cdce925
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The driver provides clock sources for each output Y1 through Y5.
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Required properties:
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- compatible: Shall be "ti,cdce925"
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- reg: I2C device address.
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- clocks: Points to a fixed parent clock that provides the input frequency.
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- #clock-cells: From common clock bindings: Shall be 1.
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Optional properties:
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- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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board, or to compensate for external influences.
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For both PLL1 and PLL2 an optional child node can be used to specify spread
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spectrum clocking parameters for a board.
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- spread-spectrum: SSC mode as defined in the data sheet.
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- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
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present, the clock runs at the requested frequency on average. Otherwise
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the requested frequency is the maximum value of the SCC range.
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Example:
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clockgen: cdce925pw@64 {
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compatible = "cdce925";
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reg = <0x64>;
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clocks = <&xtal_27Mhz>;
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#clock-cells = <1>;
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xtal-load-pf = <5>;
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/* PLL options to get SSC 1% centered */
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PLL2 {
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spread-spectrum = <4>;
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spread-spectrum-center;
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};
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};
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@ -78,6 +78,23 @@ config COMMON_CLK_SI570
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_CDCE925
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tristate "Clock driver for TI CDCE925 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports the TI CDCE925 programmable clock synthesizer.
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The chip contains two PLLs with spread-spectrum clocking support and
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five output dividers. The driver only supports the following setup,
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and uses a fixed setting for the output muxes.
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Y1 is derived from the input clock
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Y2 and Y3 derive from PLL1
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Y4 and Y5 derive from PLL2
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Given a target output frequency, the driver will set the PLL and
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divider to best approximate the desired output.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS1X/S5M8767 MFD"
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depends on MFD_SEC_CORE
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@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
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obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
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obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
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obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
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obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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@ -0,0 +1,749 @@
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/*
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* Driver for TI Dual PLL CDCE925 clock synthesizer
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*
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* This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1
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* and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve
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* basis. Clients can directly request any frequency that the chip can
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* deliver using the standard clk framework. In addition, the device can
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* be configured and activated via the devicetree.
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*
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* Copyright (C) 2014, Topic Embedded Products
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* Licenced under GPL
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/gcd.h>
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/* The chip has 2 PLLs which can be routed through dividers to 5 outputs.
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* Model this as 2 PLL clocks which are parents to the outputs.
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*/
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#define NUMBER_OF_PLLS 2
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#define NUMBER_OF_OUTPUTS 5
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#define CDCE925_REG_GLOBAL1 0x01
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#define CDCE925_REG_Y1SPIPDIVH 0x02
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#define CDCE925_REG_PDIVL 0x03
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#define CDCE925_REG_XCSEL 0x05
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/* PLL parameters start at 0x10, steps of 0x10 */
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#define CDCE925_OFFSET_PLL 0x10
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/* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
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#define CDCE925_PLL_MUX_OUTPUTS 0x14
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#define CDCE925_PLL_MULDIV 0x18
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#define CDCE925_PLL_FREQUENCY_MIN 80000000ul
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#define CDCE925_PLL_FREQUENCY_MAX 230000000ul
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struct clk_cdce925_chip;
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struct clk_cdce925_output {
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struct clk_hw hw;
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struct clk_cdce925_chip *chip;
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u8 index;
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u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */
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};
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#define to_clk_cdce925_output(_hw) \
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container_of(_hw, struct clk_cdce925_output, hw)
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struct clk_cdce925_pll {
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struct clk_hw hw;
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struct clk_cdce925_chip *chip;
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u8 index;
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u16 m; /* 1..511 */
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u16 n; /* 1..4095 */
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};
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#define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw)
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struct clk_cdce925_chip {
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struct regmap *regmap;
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struct i2c_client *i2c_client;
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struct clk_cdce925_pll pll[NUMBER_OF_PLLS];
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struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS];
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struct clk *dt_clk[NUMBER_OF_OUTPUTS];
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struct clk_onecell_data onecell;
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};
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/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
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static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
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u16 n, u16 m)
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{
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if ((!m || !n) || (m == n))
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return parent_rate; /* In bypass mode runs at same frequency */
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return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
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}
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static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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/* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
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struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
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return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
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}
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static void cdce925_pll_find_rate(unsigned long rate,
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unsigned long parent_rate, u16 *n, u16 *m)
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{
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unsigned long un;
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unsigned long um;
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unsigned long g;
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if (rate <= parent_rate) {
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/* Can always deliver parent_rate in bypass mode */
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rate = parent_rate;
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*n = 0;
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*m = 0;
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} else {
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/* In PLL mode, need to apply min/max range */
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if (rate < CDCE925_PLL_FREQUENCY_MIN)
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rate = CDCE925_PLL_FREQUENCY_MIN;
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else if (rate > CDCE925_PLL_FREQUENCY_MAX)
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rate = CDCE925_PLL_FREQUENCY_MAX;
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g = gcd(rate, parent_rate);
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um = parent_rate / g;
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un = rate / g;
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/* When outside hw range, reduce to fit (rounding errors) */
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while ((un > 4095) || (um > 511)) {
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un >>= 1;
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um >>= 1;
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}
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if (un == 0)
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un = 1;
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if (um == 0)
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um = 1;
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*n = un;
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*m = um;
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}
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}
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static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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u16 n, m;
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cdce925_pll_find_rate(rate, *parent_rate, &n, &m);
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return (long)cdce925_pll_calculate_rate(*parent_rate, n, m);
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}
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static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
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if (!rate || (rate == parent_rate)) {
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data->m = 0; /* Bypass mode */
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data->n = 0;
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return 0;
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}
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if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
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(rate > CDCE925_PLL_FREQUENCY_MAX)) {
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pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
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return -EINVAL;
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}
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if (rate < parent_rate) {
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pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
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rate, parent_rate);
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return -EINVAL;
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}
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cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
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return 0;
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}
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/* calculate p = max(0, 4 - int(log2 (n/m))) */
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static u8 cdce925_pll_calc_p(u16 n, u16 m)
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{
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u8 p;
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u16 r = n / m;
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if (r >= 16)
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return 0;
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p = 4;
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while (r > 1) {
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r >>= 1;
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--p;
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}
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return p;
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}
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/* Returns VCO range bits for VCO1_0_RANGE */
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static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
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{
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struct clk *parent = clk_get_parent(hw->clk);
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unsigned long rate = clk_get_rate(parent);
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rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
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if (rate >= 175000000)
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return 0x3;
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if (rate >= 150000000)
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return 0x02;
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if (rate >= 125000000)
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return 0x01;
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return 0x00;
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}
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/* I2C clock, hence everything must happen in (un)prepare because this
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* may sleep */
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static int cdce925_pll_prepare(struct clk_hw *hw)
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{
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struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
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u16 n = data->n;
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u16 m = data->m;
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u16 r;
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u8 q;
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u8 p;
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u16 nn;
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u8 pll[4]; /* Bits are spread out over 4 byte registers */
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u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
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unsigned i;
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if ((!m || !n) || (m == n)) {
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/* Set PLL mux to bypass mode, leave the rest as is */
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regmap_update_bits(data->chip->regmap,
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reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
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} else {
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/* According to data sheet: */
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/* p = max(0, 4 - int(log2 (n/m))) */
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p = cdce925_pll_calc_p(n, m);
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/* nn = n * 2^p */
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nn = n * BIT(p);
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/* q = int(nn/m) */
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q = nn / m;
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if ((q < 16) || (1 > 64)) {
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pr_debug("%s invalid q=%d\n", __func__, q);
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return -EINVAL;
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}
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r = nn - (m*q);
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if (r > 511) {
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pr_debug("%s invalid r=%d\n", __func__, r);
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return -EINVAL;
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}
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pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
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n, m, p, q, r);
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/* encode into register bits */
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pll[0] = n >> 4;
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pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
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pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
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pll[3] = ((q & 0x07) << 5) | (p << 2) |
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cdce925_pll_calc_range_bits(hw, n, m);
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/* Write to registers */
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for (i = 0; i < ARRAY_SIZE(pll); ++i)
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regmap_write(data->chip->regmap,
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reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
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/* Enable PLL */
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regmap_update_bits(data->chip->regmap,
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reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
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}
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return 0;
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}
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static void cdce925_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
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u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
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regmap_update_bits(data->chip->regmap,
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reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
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}
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static const struct clk_ops cdce925_pll_ops = {
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.prepare = cdce925_pll_prepare,
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.unprepare = cdce925_pll_unprepare,
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.recalc_rate = cdce925_pll_recalc_rate,
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.round_rate = cdce925_pll_round_rate,
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.set_rate = cdce925_pll_set_rate,
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};
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static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
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{
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switch (data->index) {
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case 0:
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regmap_update_bits(data->chip->regmap,
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CDCE925_REG_Y1SPIPDIVH,
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0x03, (pdiv >> 8) & 0x03);
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regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
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break;
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case 1:
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regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
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break;
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case 2:
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regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
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break;
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case 3:
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regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
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break;
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case 4:
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regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
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break;
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}
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}
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static void cdce925_clk_activate(struct clk_cdce925_output *data)
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{
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switch (data->index) {
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case 0:
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regmap_update_bits(data->chip->regmap,
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CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
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break;
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case 1:
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case 2:
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regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
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break;
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case 3:
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case 4:
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regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
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break;
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}
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}
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static int cdce925_clk_prepare(struct clk_hw *hw)
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{
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struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
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cdce925_clk_set_pdiv(data, data->pdiv);
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cdce925_clk_activate(data);
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return 0;
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}
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static void cdce925_clk_unprepare(struct clk_hw *hw)
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{
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struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
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/* Disable clock by setting divider to "0" */
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cdce925_clk_set_pdiv(data, 0);
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}
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static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
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if (data->pdiv)
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return parent_rate / data->pdiv;
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return 0;
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}
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static u16 cdce925_calc_divider(unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned long divider;
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if (!rate)
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return 0;
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if (rate >= parent_rate)
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return 1;
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divider = DIV_ROUND_CLOSEST(parent_rate, rate);
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if (divider > 0x7F)
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divider = 0x7F;
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return (u16)divider;
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}
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static unsigned long cdce925_clk_best_parent_rate(
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struct clk_hw *hw, unsigned long rate)
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{
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struct clk *pll = clk_get_parent(hw->clk);
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struct clk *root = clk_get_parent(pll);
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unsigned long root_rate = clk_get_rate(root);
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unsigned long best_rate_error = rate;
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u16 pdiv_min;
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u16 pdiv_max;
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u16 pdiv_best;
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u16 pdiv_now;
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if (root_rate % rate == 0)
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return root_rate; /* Don't need the PLL, use bypass */
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pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
|
||||
pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);
|
||||
|
||||
if (pdiv_min > pdiv_max)
|
||||
return 0; /* No can do? */
|
||||
|
||||
pdiv_best = pdiv_min;
|
||||
for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
|
||||
unsigned long target_rate = rate * pdiv_now;
|
||||
long pll_rate = clk_round_rate(pll, target_rate);
|
||||
unsigned long actual_rate;
|
||||
unsigned long rate_error;
|
||||
|
||||
if (pll_rate <= 0)
|
||||
continue;
|
||||
actual_rate = pll_rate / pdiv_now;
|
||||
rate_error = abs((long)actual_rate - (long)rate);
|
||||
if (rate_error < best_rate_error) {
|
||||
pdiv_best = pdiv_now;
|
||||
best_rate_error = rate_error;
|
||||
}
|
||||
/* TODO: Consider PLL frequency based on smaller n/m values
|
||||
* and pick the better one if the error is equal */
|
||||
}
|
||||
|
||||
return rate * pdiv_best;
|
||||
}
|
||||
|
||||
static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long l_parent_rate = *parent_rate;
|
||||
u16 divider = cdce925_calc_divider(rate, l_parent_rate);
|
||||
|
||||
if (l_parent_rate / divider != rate) {
|
||||
l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
|
||||
divider = cdce925_calc_divider(rate, l_parent_rate);
|
||||
*parent_rate = l_parent_rate;
|
||||
}
|
||||
|
||||
if (divider)
|
||||
return (long)(l_parent_rate / divider);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
|
||||
|
||||
data->pdiv = cdce925_calc_divider(rate, parent_rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops cdce925_clk_ops = {
|
||||
.prepare = cdce925_clk_prepare,
|
||||
.unprepare = cdce925_clk_unprepare,
|
||||
.recalc_rate = cdce925_clk_recalc_rate,
|
||||
.round_rate = cdce925_clk_round_rate,
|
||||
.set_rate = cdce925_clk_set_rate,
|
||||
};
|
||||
|
||||
|
||||
static u16 cdce925_y1_calc_divider(unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long divider;
|
||||
|
||||
if (!rate)
|
||||
return 0;
|
||||
if (rate >= parent_rate)
|
||||
return 1;
|
||||
|
||||
divider = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
if (divider > 0x3FF) /* Y1 has 10-bit divider */
|
||||
divider = 0x3FF;
|
||||
|
||||
return (u16)divider;
|
||||
}
|
||||
|
||||
static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long l_parent_rate = *parent_rate;
|
||||
u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);
|
||||
|
||||
if (divider)
|
||||
return (long)(l_parent_rate / divider);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
|
||||
|
||||
data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops cdce925_clk_y1_ops = {
|
||||
.prepare = cdce925_clk_prepare,
|
||||
.unprepare = cdce925_clk_unprepare,
|
||||
.recalc_rate = cdce925_clk_recalc_rate,
|
||||
.round_rate = cdce925_clk_y1_round_rate,
|
||||
.set_rate = cdce925_clk_y1_set_rate,
|
||||
};
|
||||
|
||||
|
||||
static struct regmap_config cdce925_regmap_config = {
|
||||
.name = "configuration0",
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.max_register = 0x2F,
|
||||
};
|
||||
|
||||
#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00
|
||||
#define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80
|
||||
|
||||
static int cdce925_regmap_i2c_write(
|
||||
void *context, const void *data, size_t count)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct i2c_client *i2c = to_i2c_client(dev);
|
||||
int ret;
|
||||
u8 reg_data[2];
|
||||
|
||||
if (count != 2)
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* First byte is command code */
|
||||
reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
|
||||
reg_data[1] = ((u8 *)data)[1];
|
||||
|
||||
dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
|
||||
reg_data[0], reg_data[1]);
|
||||
|
||||
ret = i2c_master_send(i2c, reg_data, count);
|
||||
if (likely(ret == count))
|
||||
return 0;
|
||||
else if (ret < 0)
|
||||
return ret;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int cdce925_regmap_i2c_read(void *context,
|
||||
const void *reg, size_t reg_size, void *val, size_t val_size)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct i2c_client *i2c = to_i2c_client(dev);
|
||||
struct i2c_msg xfer[2];
|
||||
int ret;
|
||||
u8 reg_data[2];
|
||||
|
||||
if (reg_size != 1)
|
||||
return -ENOTSUPP;
|
||||
|
||||
xfer[0].addr = i2c->addr;
|
||||
xfer[0].flags = 0;
|
||||
xfer[0].buf = reg_data;
|
||||
if (val_size == 1) {
|
||||
reg_data[0] =
|
||||
CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
|
||||
xfer[0].len = 1;
|
||||
} else {
|
||||
reg_data[0] =
|
||||
CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
|
||||
reg_data[1] = val_size;
|
||||
xfer[0].len = 2;
|
||||
}
|
||||
|
||||
xfer[1].addr = i2c->addr;
|
||||
xfer[1].flags = I2C_M_RD;
|
||||
xfer[1].len = val_size;
|
||||
xfer[1].buf = val;
|
||||
|
||||
ret = i2c_transfer(i2c->adapter, xfer, 2);
|
||||
if (likely(ret == 2)) {
|
||||
dev_dbg(&i2c->dev, "%s(%zu, %u) %#x %#x\n", __func__,
|
||||
reg_size, val_size, reg_data[0], *((u8 *)val));
|
||||
return 0;
|
||||
} else if (ret < 0)
|
||||
return ret;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* The CDCE925 uses a funky way to read/write registers. Bulk mode is
|
||||
* just weird, so just use the single byte mode exclusively. */
|
||||
static struct regmap_bus regmap_cdce925_bus = {
|
||||
.write = cdce925_regmap_i2c_write,
|
||||
.read = cdce925_regmap_i2c_read,
|
||||
};
|
||||
|
||||
static int cdce925_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct clk_cdce925_chip *data;
|
||||
struct device_node *node = client->dev.of_node;
|
||||
const char *parent_name;
|
||||
const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,};
|
||||
struct clk_init_data init;
|
||||
struct clk *clk;
|
||||
u32 value;
|
||||
int i;
|
||||
int err;
|
||||
struct device_node *np_output;
|
||||
char child_name[6];
|
||||
|
||||
dev_dbg(&client->dev, "%s\n", __func__);
|
||||
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->i2c_client = client;
|
||||
data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus,
|
||||
&client->dev, &cdce925_regmap_config);
|
||||
if (IS_ERR(data->regmap)) {
|
||||
dev_err(&client->dev, "failed to allocate register map\n");
|
||||
return PTR_ERR(data->regmap);
|
||||
}
|
||||
i2c_set_clientdata(client, data);
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
if (!parent_name) {
|
||||
dev_err(&client->dev, "missing parent clock\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
dev_dbg(&client->dev, "parent is: %s\n", parent_name);
|
||||
|
||||
if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
|
||||
regmap_write(data->regmap,
|
||||
CDCE925_REG_XCSEL, (value << 3) & 0xF8);
|
||||
/* PWDN bit */
|
||||
regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);
|
||||
|
||||
/* Set input source for Y1 to be the XTAL */
|
||||
regmap_update_bits(data->regmap, 0x02, BIT(7), 0);
|
||||
|
||||
init.ops = &cdce925_pll_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
/* Register PLL clocks */
|
||||
for (i = 0; i < NUMBER_OF_PLLS; ++i) {
|
||||
pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
|
||||
client->dev.of_node->name, i);
|
||||
init.name = pll_clk_name[i];
|
||||
data->pll[i].chip = data;
|
||||
data->pll[i].hw.init = &init;
|
||||
data->pll[i].index = i;
|
||||
clk = devm_clk_register(&client->dev, &data->pll[i].hw);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&client->dev, "Failed register PLL %d\n", i);
|
||||
err = PTR_ERR(clk);
|
||||
goto error;
|
||||
}
|
||||
sprintf(child_name, "PLL%d", i+1);
|
||||
np_output = of_get_child_by_name(node, child_name);
|
||||
if (!np_output)
|
||||
continue;
|
||||
if (!of_property_read_u32(np_output,
|
||||
"clock-frequency", &value)) {
|
||||
err = clk_set_rate(clk, value);
|
||||
if (err)
|
||||
dev_err(&client->dev,
|
||||
"unable to set PLL frequency %ud\n",
|
||||
value);
|
||||
}
|
||||
if (!of_property_read_u32(np_output,
|
||||
"spread-spectrum", &value)) {
|
||||
u8 flag = of_property_read_bool(np_output,
|
||||
"spread-spectrum-center") ? 0x80 : 0x00;
|
||||
regmap_update_bits(data->regmap,
|
||||
0x16 + (i*CDCE925_OFFSET_PLL),
|
||||
0x80, flag);
|
||||
regmap_update_bits(data->regmap,
|
||||
0x12 + (i*CDCE925_OFFSET_PLL),
|
||||
0x07, value & 0x07);
|
||||
}
|
||||
}
|
||||
|
||||
/* Register output clock Y1 */
|
||||
init.ops = &cdce925_clk_y1_ops;
|
||||
init.flags = 0;
|
||||
init.num_parents = 1;
|
||||
init.parent_names = &parent_name; /* Mux Y1 to input */
|
||||
init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name);
|
||||
data->clk[0].chip = data;
|
||||
data->clk[0].hw.init = &init;
|
||||
data->clk[0].index = 0;
|
||||
data->clk[0].pdiv = 1;
|
||||
clk = devm_clk_register(&client->dev, &data->clk[0].hw);
|
||||
kfree(init.name); /* clock framework made a copy of the name */
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&client->dev, "clock registration Y1 failed\n");
|
||||
err = PTR_ERR(clk);
|
||||
goto error;
|
||||
}
|
||||
data->dt_clk[0] = clk;
|
||||
|
||||
/* Register output clocks Y2 .. Y5*/
|
||||
init.ops = &cdce925_clk_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.num_parents = 1;
|
||||
for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) {
|
||||
init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
|
||||
client->dev.of_node->name, i+1);
|
||||
data->clk[i].chip = data;
|
||||
data->clk[i].hw.init = &init;
|
||||
data->clk[i].index = i;
|
||||
data->clk[i].pdiv = 1;
|
||||
switch (i) {
|
||||
case 1:
|
||||
case 2:
|
||||
/* Mux Y2/3 to PLL1 */
|
||||
init.parent_names = &pll_clk_name[0];
|
||||
break;
|
||||
case 3:
|
||||
case 4:
|
||||
/* Mux Y4/5 to PLL2 */
|
||||
init.parent_names = &pll_clk_name[1];
|
||||
break;
|
||||
}
|
||||
clk = devm_clk_register(&client->dev, &data->clk[i].hw);
|
||||
kfree(init.name); /* clock framework made a copy of the name */
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&client->dev, "clock registration failed\n");
|
||||
err = PTR_ERR(clk);
|
||||
goto error;
|
||||
}
|
||||
data->dt_clk[i] = clk;
|
||||
}
|
||||
|
||||
/* Register the output clocks */
|
||||
data->onecell.clk_num = NUMBER_OF_OUTPUTS;
|
||||
data->onecell.clks = data->dt_clk;
|
||||
err = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
|
||||
&data->onecell);
|
||||
if (err)
|
||||
dev_err(&client->dev, "unable to add OF clock provider\n");
|
||||
|
||||
err = 0;
|
||||
|
||||
error:
|
||||
for (i = 0; i < NUMBER_OF_PLLS; ++i)
|
||||
/* clock framework made a copy of the name */
|
||||
kfree(pll_clk_name[i]);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id cdce925_id[] = {
|
||||
{ "cdce925", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, cdce925_id);
|
||||
|
||||
static const struct of_device_id clk_cdce925_of_match[] = {
|
||||
{ .compatible = "ti,cdce925" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
|
||||
|
||||
static struct i2c_driver cdce925_driver = {
|
||||
.driver = {
|
||||
.name = "cdce925",
|
||||
.of_match_table = of_match_ptr(clk_cdce925_of_match),
|
||||
},
|
||||
.probe = cdce925_probe,
|
||||
.id_table = cdce925_id,
|
||||
};
|
||||
module_i2c_driver(cdce925_driver);
|
||||
|
||||
MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
|
||||
MODULE_DESCRIPTION("cdce925 driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue